3 files changed, 10 insertions, 3 deletions
diff --git a/COPYING b/COPYING
new file mode 100644
index 0000000..3aeb771
--- /dev/null
+++ b/COPYING
@@ -0,0 +1,3 @@
+
+Put your project licensing information in this file!
+
diff --git a/README b/README
index e303770..ff2aad0 100644
--- a/README
+++ b/README
@@ -1,5 +1,5 @@
 
-* * < DELTEME > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+* * * DELETE ME * * * * * * * DELETE ME * * * * * * * DELETE ME * * * * * * * *
 
 This folder contains a template Verilog/VHDL HDL project with a basic build
 system for using the Xilinx ISE toolchain to target FPGAs.                  
@@ -10,11 +10,15 @@ minimum you will need to copy ./contrib/Makefile.example to ./Makefile.
                                                                             
 Hint: search this file for "<board>"                                        
 
-* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+^ ^ ^ DELETE ME ^ ^ ^ ^ ^ ^ ^ DELETE ME ^ ^ ^ ^ ^ ^ ^ DELETE ME ^ ^ ^ ^ ^ ^ ^ ^
 
 == About =====================================================================
 
-<fill this part in>
+
+
+  <<<<fill this part in>>>>
+
+
 
 See COPYING for copyright and licensing information.
 
diff --git a/contrib/QUICK_START.txt b/contrib/QUICK_START.txt
index 852f11c..852f11c 100644..100755
--- a/contrib/QUICK_START.txt
+++ b/contrib/QUICK_START.txt