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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-03-14 12:50:17 -0400 |
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| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-03-14 12:50:17 -0400 |
| commit | 7d9fb988443e94507a7d3ca6e0137aaf49af42e1 (patch) | |
| tree | 31e6d5bf72d3df45dc8636283b3b75b861532fbc /README | |
| parent | 0b157a316fce0ebc5ba020e8b8d710a644727ad5 (diff) | |
| download | basic-hdl-template-7d9fb988443e94507a7d3ca6e0137aaf49af42e1.tar.gz basic-hdl-template-7d9fb988443e94507a7d3ca6e0137aaf49af42e1.zip | |
improvements
Diffstat (limited to 'README')
| -rw-r--r-- | README | 6 |
1 files changed, 4 insertions, 2 deletions
@@ -17,6 +17,8 @@ lives in: ./hdl/project.v +Add other verilog synthesis (not testbench) files to ./hdl/*.v + To edit the project with the ISE GUI, try: make ise @@ -29,9 +31,9 @@ Simulate with isim via: make simulate -View the results using isim with: +View the results using the isim GUI with: - make isim_gui + make isim In isim, you can open the "signals.wcfg" in the file menu to reload a the logic analyzer configuration. This cfg file will not be valid if you delete any |