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A very basic project template for Verilog simulation and synthesis using Isim
and Xilinx tools.
Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in
Makefile) via:
make
The toplevel ucf (constraints mapping netlist objects from the verilog
compilation to hardware resources, and place and routing and timing
constraints) is:
./project.ucf
The toplevel verilog module, which does nothing (just sets some pins to zero)
lives in:
./hdl/project.v
Add other verilog synthesis (not testbench) files to ./hdl/*.v
To edit the project with the ISE GUI, try:
make ise
WARNING: the ISE configuration options may or may not be synchronized with the
command line build options. Edit the options in project.opt and build only from
the command line to be safe.
Simulate with isim via:
make simulate
View the results using the isim GUI with:
make isim
In isim, you can open the "signals.wcfg" in the file menu to reload a the logic
analyzer configuration. This cfg file will not be valid if you delete any
signals from your design that are saves in the wcfg.
./testbench/tb.v is the toplevel testbench file for simulation.
Please improve and push!
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