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authorbryan newbold <bnewbold@leaflabs.com>2013-03-13 16:55:03 -0400
committerbryan newbold <bnewbold@leaflabs.com>2013-03-13 16:55:03 -0400
commit1fb122666f83a582b2c77829dcff598bc2c8ee6b (patch)
treec38b197ec46f97990d9efe49dbc20f815a42dd50
parent48d0e230c56be8a2722851556b2b1e039c4847c4 (diff)
downloadbasic-hdl-template-1fb122666f83a582b2c77829dcff598bc2c8ee6b.tar.gz
basic-hdl-template-1fb122666f83a582b2c77829dcff598bc2c8ee6b.zip
some simulation stuff
-rw-r--r--.gitignore3
-rw-r--r--Makefile5
-rw-r--r--contrib/xilinx.mk40
3 files changed, 45 insertions, 3 deletions
diff --git a/.gitignore b/.gitignore
index 4f84d26..195e69e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -60,3 +60,6 @@ webtalk_pn.xml
*.prm
*.psr
*.scr
+tb/simulate_isim
+tb/simulate_isim.prj
+iseconfig/
diff --git a/Makefile b/Makefile
index d434552..fb70c09 100644
--- a/Makefile
+++ b/Makefile
@@ -6,8 +6,11 @@ vendor = xilinx
family = spartan6
part = xc6slx45t-3-fgg484
-iseenvfile = /opt/Xilinx/14.3/ISE_DS/settings64.sh
+# is this build host 64 or 32 bits?
+hostbits = 64
+iseenv= /opt/Xilinx/14.3/ISE_DS/
vfiles = ./hdl/project.v
+tbfiles = ./tb/tb.v
include ./contrib/xilinx.mk
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk
index 8533121..f8773ac 100644
--- a/contrib/xilinx.mk
+++ b/contrib/xilinx.mk
@@ -42,8 +42,11 @@
coregen_work_dir ?= ./coregen-tmp
map_opts ?= -timing -ol high -detail -pr b -register_duplication -w
par_opts ?= -ol high
-iseenvfile?= /opt/Xilinx/14.3/ISE_DS
+hostbits = 64
+iseenv= /opt/Xilinx/14.3/ISE_DS
+iseenvfile?= $(iseenv)/settings$(hostbits).sh
xil_env ?= cd ./build; source $(iseenvfile) > /dev/null
+sim_env ?= cd ./tb; source $(iseenvfile) > /dev/null
flashsize ?= 8192
libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
@@ -179,6 +182,32 @@ junk += $(project)_err.twr $(project)_err.twx
.gitignore: $(mkfiles)
echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore
+tb/simulate_isim.prj: $(tbfiles)
+ rm $@
+ for f in $(vfiles)
+ do
+ echo "verilog unenclib ../$(f)" >> $@
+ done
+ for f in $(tbfiles)
+ do
+ echo "verilog unenclib ../$(f)" >> $@
+ done
+ echo "verilog unenclib ../$(iseenv)/ISE/verilog/src/glbl.v" >> $@
+
+tb/isim: tb/simulate_isim.prj
+ bash -c "$(sim_env); cd ../tb/; vlogcomp -prj simulate_isim.prj"
+
+tb/simulate_isim: tb/isim
+ bash -c "$(sim_env); cd ../tb/; fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim unenclib.tb unenclib.glbl"
+
+simulate: tb/simulate_isim
+
+isim_gui: simulate
+ bash -c "$(sim_env); cd ../tb/; ./simulate_isim"
+
+isim_gui: simulate
+ bash -c "$(sim_env); cd ../tb/; ./simulate_isim -gui -view signals.wcfg"
+
ise:
@echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
@echo "! WARNING: you might need to update ISE's project settings !"
@@ -187,6 +216,13 @@ ise:
@mkdir -p build
bash -c "$(xil_env); ise .. &"
-clean::
+clean: clean_synth clean_sim
+
+clean_sim::
+ rm -f tb/simulate_isim tb/*.log tb/*.cmd tb/*.xmsgs
+ rm -rf tb/isim
+
+clean_synth::
rm -rf build
#rm -rf $(junk)
+