1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
|
# This file oritinally came from excamera's build example.
#
# The top level module should define the variables below then include
# this file. The files listed should be in the same directory as the
# Makefile.
#
# TODO: update these listings
#
# variable description
# ---------- -------------
# project project name (top level module should match this name)
# top_module top level module of the project
# libdir path to library directory
# libs library modules used
# vfiles all local .v files
# xilinx_cores all local .xco files
# vendor vendor of FPGA (xilinx, altera, etc.)
# family FPGA device family (spartan3e)
# part FPGA part name (xc4vfx12-10-sf363)
# flashsize size of flash for mcs file (16384)
# optfile (optional) xst extra opttions file to put in .scr
# map_opts (optional) options to give to map
# par_opts (optional) options to give to par
# intstyle (optional) intstyle option to all tools
#
# files description
# ---------- ------------
# $(project).ucf ucf file
#
# Library modules should have a modules.mk in their root directory,
# namely $(libdir)/<libname>/module.mk, that simply adds to the vfiles
# and xilinx_cores variable.
#
# all the .xco files listed in xilinx_cores will be generated with core, with
# the resulting .v and .ngc files placed back in the same directory as
# the .xco file.
#
# TODO: .xco files are device dependant, should use a template based system
#
# NOTE: DO NOT edit this file to change settings; instead edit Makefile
coregen_work_dir ?= ./coregen-tmp
map_opts ?= -timing -ol high -detail -pr b -register_duplication -w
par_opts ?= -ol high
iseenvfile?= /opt/Xilinx/14.3/ISE_DS
xil_env ?= cd ./build; source $(iseenvfile) > /dev/null
flashsize ?= 8192
libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
mkfiles = Makefile $(libmks) contrib/xilinx.mk
include $(libmks)
corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc))
local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc)))
vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
junk += $(local_corengcs)
.PHONY: default xilinx_cores clean twr etwr ise
default: build/$(project).bit build/$(project).mcs
xilinx_cores: $(corengcs)
twr: $(project).twr
etwr: $(project)_err.twr
define cp_template
$(2): $(1)
cp $(1) $(2)
endef
$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
%.ngc %.v: %.xco
@echo "=== rebuilding $@"
if [ -d $(coregen_work_dir) ]; then \
rm -rf $(coregen_work_dir)/*; \
else \
mkdir -p $(coregen_work_dir); \
fi
cd $(coregen_work_dir); \
bash -c "$(xil_env); \
coregen -b $$OLDPWD/$<; \
cd -
xcodir=`dirname $<`; \
basename=`basename $< .xco`; \
if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \
echo "'$@' wasn't created."; \
exit 1; \
else \
cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \
fi"
junk += $(coregen_work_dir)
date = $(shell date +%F-%H-%M)
# some common junk
junk += *.xrpt
junk += _xmsgs
programming_files: build/$(project).bit build/$(project).mcs
mkdir -p $@/$(date)
mkdir -p $@/latest
for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done
bash -c "$(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - build/$(project).scr > $@/$(date)/$(project).scr"
build/$(project).mcs: build/$(project).bit
bash -c "$(xil_env); promgen -w -s $(flashsize) -p mcs -o $(project).mcs -u 0 $(project).bit"
junk += $(project).mcs $(project).cfi $(project).prm
build/$(project).bit: build/$(project)_par.ncd
bash -c "$(xil_env); \
bitgen $(intstyle) -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit"
junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm
build/$(project)_par.ncd: build/$(project).ncd
bash -c "$(xil_env); \
if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \
:; \
else \
$(MAKE) etwr; \
fi "
junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
junk += $(project)_par_pad.csv $(project)_par_pad.txt
junk += $(project)_par.grf $(project)_par.ptwx
junk += $(project)_par.unroutes $(project)_par.xpi
build/$(project).ncd: build/$(project).ngd
if [ -r $(project)_par.ncd ]; then \
cp $(project)_par.ncd smartguide.ncd; \
smartguide="-smartguide smartguide.ncd"; \
else \
smartguide=""; \
fi; \
bash -c "$(xil_env); \
map $(intstyle) $(map_opts) $$smartguide $(project).ngd "
junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
junk += smartguide.ncd $(project).psr
junk += $(project)_summary.xml $(project)_usage.xml
build/$(project).ngd: build/$(project).ngc $(project).ucf $(project).bmm
bash -c "$(xil_env); \
ngdbuild $(intstyle) $(project).ngc -bm ../$(project).bmm"
junk += $(project).ngd $(project).bld
build/$(project).ngc: $(vfiles) $(local_corengcs) build/$(project).scr build/$(project).prj
bash -c "$(xil_env); xst $(intstyle) -ifn $(project).scr"
junk += xlnx_auto* build/$(top_module).lso $(project).srp
junk += netlist.lst xst $(project).ngc
build/$(project).prj: $(vfiles) $(mkfiles)
for src in $(vfiles); do echo "verilog work ../$$src" >> $(project).tmpprj; done
sort -u $(project).tmpprj > $@
rm -f $(project).tmpprj
junk += $(project).prj
optfile += $(wildcard $(project).opt)
top_module ?= $(project)
build/$(project).scr: $(optfile) $(mkfiles) ./$(project).opt
mkdir -p build
echo "run" > $@
echo "-p $(part)" >> $@
echo "-top $(top_module)" >> $@
echo "-ifn $(project).prj" >> $@
echo "-ofn $(project).ngc" >> $@
cat $(optfile) >> $@
cp $@ build/$(project).xst
junk += $(project).scr
build/$(project).post_map.twr: build/$(project).ncd
bash -c "$(xil_env); trce -e 10 $< $(project).pcf -o $@"
junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr
build/$(project).twr: build/$(project)_par.ncd
bash -c "$(xil_env); trce $< $(project).pcf -o $(project).twr"
junk += $(project).twr $(project).twx smartpreview.twr
build/$(project)_err.twr: build/$(project)_par.ncd
bash -c "$(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr"
junk += $(project)_err.twr $(project)_err.twx
.gitignore: $(mkfiles)
echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore
ise:
@echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
@echo "! WARNING: you might need to update ISE's project settings !"
@echo "! (see README) !"
@echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
@mkdir -p build
bash -c "$(xil_env); ise .. &"
clean::
rm -rf build
#rm -rf $(junk)
|