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authorbryan newbold <bnewbold@leaflabs.com>2013-03-13 17:00:34 -0400
committerbryan newbold <bnewbold@leaflabs.com>2013-03-13 17:00:34 -0400
commit0b157a316fce0ebc5ba020e8b8d710a644727ad5 (patch)
treed9a6ad3318d27f71e94fc4e67da5f9bdc6fdce69
parent1fb122666f83a582b2c77829dcff598bc2c8ee6b (diff)
downloadbasic-hdl-template-0b157a316fce0ebc5ba020e8b8d710a644727ad5.zip
basic-hdl-template-0b157a316fce0ebc5ba020e8b8d710a644727ad5.tar.gz
update README; gitignore ./build
-rw-r--r--.gitignore1
-rw-r--r--README38
2 files changed, 24 insertions, 15 deletions
diff --git a/.gitignore b/.gitignore
index 195e69e..5509696 100644
--- a/.gitignore
+++ b/.gitignore
@@ -63,3 +63,4 @@ webtalk_pn.xml
tb/simulate_isim
tb/simulate_isim.prj
iseconfig/
+build/
diff --git a/README b/README
index 9e5a5ad..cda84b1 100644
--- a/README
+++ b/README
@@ -1,28 +1,37 @@
A very basic project template for Verilog simulation and synthesis using Isim
-and Xilinx tools. Adapted from an actual project, so there is likely a bit of
-unecessary flags and switches on certain commands. I have done my best to remove
-everything a can where things will still build.
+and Xilinx tools.
-Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in one
-of the conf files) via:
+Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in
+Makefile) via:
-./synth_project/make.sh
+ make
-the toplevel ucf (constraints mapping netlist objects from the verilog
-compilation to hardware resources, and place and routing and timing constraints)
-is:
-./synth_project/project.ucf
+The toplevel ucf (constraints mapping netlist objects from the verilog
+compilation to hardware resources, and place and routing and timing
+constraints) is:
-the toplevel verilog module, which does nothing (just sets some pins to zero)
+ ./project.ucf
+
+The toplevel verilog module, which does nothing (just sets some pins to zero)
lives in:
-./hdl/project.v
+ ./hdl/project.v
+
+To edit the project with the ISE GUI, try:
+
+ make ise
+
+WARNING: the ISE configuration options may or may not be synchronized with the
+command line build options. Edit the options in project.opt and build only from
+the command line to be safe.
Simulate with isim via:
-./testbench/fuse.sh
-./testbench/simulate_isim -gui
+ make simulate
+
+View the results using isim with:
+ make isim_gui
In isim, you can open the "signals.wcfg" in the file menu to reload a the logic
analyzer configuration. This cfg file will not be valid if you delete any
@@ -30,5 +39,4 @@ signals from your design that are saves in the wcfg.
./testbench/tb.v is the toplevel testbench file for simulation.
-
Please improve and push!