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diff --git a/hdcp/shuffle_network.v b/hdcp/shuffle_network.v
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+//////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2011, Andrew "bunnie" Huang
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification, 
+// are permitted provided that the following conditions are met:
+//
+//  * Redistributions of source code must retain the above copyright notice, 
+//    this list of conditions and the following disclaimer.
+//  * Redistributions in binary form must reproduce the above copyright notice, 
+//    this list of conditions and the following disclaimer in the documentation and/or 
+//    other materials provided with the distribution.
+//
+//    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY 
+//    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 
+//    OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+//    SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+//    INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+//    LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
+//    PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+//    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+//    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
+//    POSSIBILITY OF SUCH DAMAGE.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+module shuffle_network (
+			input wire clk,
+			input wire reset,
+			input wire din,
+			input wire sel,
+			input wire advance,
+			input wire init_iv,
+			output wire dout
+			);
+
+   reg 				    a, b;
+   
+   always @(posedge clk or posedge reset) begin
+      if( reset == 1 ) begin
+	 a <= 1'b0;
+	 b <= 1'b1;
+      end else begin
+	 if( init_iv ) begin
+	    a <= 1'b0;
+	    b <= 1'b1;
+	 end else if( advance ) begin
+	    a <= sel ? din : b;
+	    b <= sel ? a : din;
+	 end else begin
+	    a <= a;
+	    b <= b;
+	 end
+      end // else: !if( reset == 1 )
+   end // always @ (posedge clk or posedge reset)
+
+   assign dout = sel ? b : a;
+   
+endmodule // shuffle_network