1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
|
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 Perry Hung.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*****************************************************************************/
/**
* @file adc.h
*
* @brief Analog-to-Digital Conversion (ADC) header.
*/
#ifndef _ADC_H_
#define _ADC_H_
#include "util.h"
#include "rcc.h"
#ifdef __cplusplus
extern "C"{
#endif
typedef struct adc_reg_map {
__io uint32 SR; ///< Status register
__io uint32 CR1; ///< Control register 1
__io uint32 CR2; ///< Control register 2
__io uint32 SMPR1; ///< Sample time register 1
__io uint32 SMPR2; ///< Sample time register 2
__io uint32 JOFR1; ///< Injected channel data offset register 1
__io uint32 JOFR2; ///< Injected channel data offset register 2
__io uint32 JOFR3; ///< Injected channel data offset register 3
__io uint32 JOFR4; ///< Injected channel data offset register 4
__io uint32 HTR; ///< Watchdog high threshold register
__io uint32 LTR; ///< Watchdog low threshold register
__io uint32 SQR1; ///< Regular sequence register 1
__io uint32 SQR2; ///< Regular sequence register 2
__io uint32 SQR3; ///< Regular sequence register 3
__io uint32 JSQR; ///< Injected sequence register
__io uint32 JDR1; ///< Injected data register 1
__io uint32 JDR2; ///< Injected data register 2
__io uint32 JDR3; ///< Injected data register 3
__io uint32 JDR4; ///< Injected data register 4
__io uint32 DR; ///< Regular data register
} adc_reg_map;
typedef struct adc_dev {
adc_reg_map *regs;
rcc_clk_id clk_id;
} adc_dev;
extern const adc_dev *ADC1;
extern const adc_dev *ADC2;
#ifdef STM32_HIGH_DENSITY
extern const adc_dev *ADC3;
#endif
/*
* ADC peripheral base addresses
*/
#define ADC1_BASE ((adc_reg_map*)0x40012400)
#define ADC2_BASE ((adc_reg_map*)0x40012800)
#define ADC3_BASE ((adc_reg_map*)0x40013C00)
/*
* Register bit definitions
*/
/* Status register */
#define ADC_SR_AWD BIT(0)
#define ADC_SR_EOC BIT(1)
#define ADC_SR_JEOC BIT(2)
#define ADC_SR_JSTRT BIT(3)
#define ADC_SR_STRT BIT(4)
/* Control register 1 */
#define ADC_CR1_AWDCH (0x1F)
#define ADC_CR1_EOCIE BIT(5)
#define ADC_CR1_AWDIE BIT(6)
#define ADC_CR1_JEOCIE BIT(7)
#define ADC_CR1_SCAN BIT(8)
#define ADC_CR1_AWDSGL BIT(9)
#define ADC_CR1_JAUTO BIT(10)
#define ADC_CR1_DISCEN BIT(11)
#define ADC_CR1_JDISCEN BIT(12)
#define ADC_CR1_DISCNUM (0xE000)
#define ADC_CR1_JAWDEN BIT(22)
#define ADC_CR1_AWDEN BIT(23)
/* Control register 2 */
#define ADC_CR2_ADON BIT(0)
#define ADC_CR2_CONT BIT(1)
#define ADC_CR2_CAL BIT(2)
#define ADC_CR2_RSTCAL BIT(3)
#define ADC_CR2_DMA BIT(8)
#define ADC_CR2_ALIGN BIT(11)
#define ADC_CR2_JEXTSEL (0x7000)
#define ADC_CR2_JEXTTRIG BIT(15)
#define ADC_CR2_EXTSEL (0xE0000)
#define ADC_CR2_EXTTRIG BIT(20)
#define ADC_CR2_JSWSTART BIT(21)
#define ADC_CR2_SWSTART BIT(22)
#define ADC_CR2_TSEREFE BIT(23)
void adc_init(const adc_dev *dev, uint32 flags);
void adc_set_extsel(const adc_dev *dev, uint8 trigger);
/** ADC per-sample conversion times, in ADC clock cycles */
typedef enum {
ADC_SMPR_1_5, ///< 1.5 ADC cycles
ADC_SMPR_7_5, ///< 7.5 ADC cycles
ADC_SMPR_13_5, ///< 13.5 ADC cycles
ADC_SMPR_28_5, ///< 28.5 ADC cycles
ADC_SMPR_41_5, ///< 41.5 ADC cycles
ADC_SMPR_55_5, ///< 55.5 ADC cycles
ADC_SMPR_71_5, ///< 71.5 ADC cycles
ADC_SMPR_239_5 ///< 239.5 ADC cycles
} adc_smp_rate;
void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate);
/**
* @brief Perform a single synchronous software triggered conversion on a
* channel
* @param regs ADC register map
* @param channel channel to convert
* @return conversion result
*/
static inline uint32 adc_read(const adc_dev *dev, uint8 channel) {
adc_reg_map *regs = dev->regs;
/* Set target channel */
regs->SQR3 = channel;
/* Start the conversion */
regs->CR2 |= ADC_CR2_SWSTART;
/* Wait for it to finish */
while((regs->SR & ADC_SR_EOC) == 0)
;
return regs->DR;
}
/**
* @brief Set external trigger conversion mode event for regular channels
* @param dev adc device
* @param enable if 1, conversion on external events is enabled, 0 to disable
*/
static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) {
__write(BITBAND_PERI(&(dev->regs->CR2), 20), enable);
}
/**
* @brief Enable an adc peripheral
* @param regs register map of peripheral to enable
*/
static inline void adc_enable(const adc_dev *dev) {
__write(BITBAND_PERI(&(dev->regs->CR2), 0), 1);
}
/**
* @brief Disable an adc peripheral
* @param regs register map of peripheral to disable
*/
static inline void adc_disable(const adc_dev *dev) {
__write(BITBAND_PERI(&(dev->regs->CR2), 0), 0);
}
/**
* @brief Disable all ADCs
*/
static inline void adc_disable_all(void) {
adc_disable(ADC1);
adc_disable(ADC2);
#ifdef STM32_HIGH_DENSITY
adc_disable(ADC3);
#endif
}
#ifdef __cplusplus
} // extern "C"
#endif
#endif
|