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-rw-r--r--libmaple/stm32f2/include/series/adc.h335
-rw-r--r--libmaple/stm32f2/include/series/dac.h94
-rw-r--r--libmaple/stm32f2/include/series/dma.h810
-rw-r--r--libmaple/stm32f2/include/series/exti.h46
-rw-r--r--libmaple/stm32f2/include/series/flash.h202
-rw-r--r--libmaple/stm32f2/include/series/gpio.h264
-rw-r--r--libmaple/stm32f2/include/series/i2c.h80
-rw-r--r--libmaple/stm32f2/include/series/nvic.h160
-rw-r--r--libmaple/stm32f2/include/series/pwr.h73
-rw-r--r--libmaple/stm32f2/include/series/rcc.h951
-rw-r--r--libmaple/stm32f2/include/series/spi.h88
-rw-r--r--libmaple/stm32f2/include/series/stm32.h77
-rw-r--r--libmaple/stm32f2/include/series/timer.h176
-rw-r--r--libmaple/stm32f2/include/series/usart.h111
14 files changed, 0 insertions, 3467 deletions
diff --git a/libmaple/stm32f2/include/series/adc.h b/libmaple/stm32f2/include/series/adc.h
deleted file mode 100644
index 175fe11..0000000
--- a/libmaple/stm32f2/include/series/adc.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2012 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/adc.h
- * @author Marti Bolivar <mbolivar@leaflabs.com>,
- * @brief STM32F2 ADC support.
- */
-
-#ifndef _LIBMAPLE_STM32F2_ADC_H_
-#define _LIBMAPLE_STM32F2_ADC_H_
-
-#include <libmaple/libmaple_types.h>
-
-/*
- * Devices
- */
-
-extern const struct adc_dev *ADC1;
-extern const struct adc_dev *ADC2;
-extern const struct adc_dev *ADC3;
-
-/*
- * Common register map
- */
-
-/** ADC common register map type */
-typedef struct adc_common_reg_map {
- __io uint32 CSR; /**< Common status register */
- __io uint32 CCR; /**< Common control register */
- __io uint32 CDR; /**<
- * @brief Common regular data register
- * for dual and triple modes */
-} adc_common_reg_map;
-
-/*
- * Register map base pointers
- */
-
-/** ADC1 register map base pointer. */
-#define ADC1_BASE ((struct adc_reg_map*)0x40012000)
-/** ADC2 register map base pointer. */
-#define ADC2_BASE ((struct adc_reg_map*)0x40012100)
-/** ADC3 register map base pointer. */
-#define ADC3_BASE ((struct adc_reg_map*)0x40012200)
-/** ADC common register map base pointer. */
-#define ADC_COMMON_BASE ((struct adc_common_reg_map*)0x40012300)
-
-/*
- * Register bit definitions
- */
-
-/* Status register */
-
-/** Overrun bit. */
-#define ADC_SR_OVR_BIT 5
-/** Overrun. */
-#define ADC_SR_OVR (1U << ADC_SR_OVR_BIT)
-
-/* Control register 1 */
-
-/** Overrun interrupt enable bit. */
-#define ADC_CR1_OVRIE_BIT 26
-
-/** Overrun interrupt error enable. */
-#define ADC_CR1_OVRIE (1U << ADC_CR1_OVRIE_BIT)
-/** Conversion resolution. */
-#define ADC_CR1_RES (0x3U << 24)
-/** Conversion resolution: 12 bit (at least 15 ADCCLK cycles). */
-#define ADC_CR1_RES_12BIT (0x0U << 24)
-/** Conversion resolution: 10 bit (at least 13 ADCCLK cycles). */
-#define ADC_CR1_RES_10BIT (0x1U << 24)
-/** Conversion resolution: 8 bit (at least 11 ADCCLK cycles). */
-#define ADC_CR1_RES_8BIT (0x2U << 24)
-/** Conversion resolution: 6 bit (at least 9 ADCCLK cycles). */
-#define ADC_CR1_RES_6BIT (0x3U << 24)
-
-/* Control register 2 */
-
-#define ADC_CR2_SWSTART_BIT 30
-#define ADC_CR2_JSWSTART_BIT 22
-#define ADC_CR2_ALIGN_BIT 11
-#define ADC_CR2_EOCS_BIT 10
-#define ADC_CR2_DDS_BIT 9
-#define ADC_CR2_DMA_BIT 8
-#define ADC_CR2_CONT_BIT 1
-#define ADC_CR2_ADON_BIT 0
-
-#define ADC_CR2_SWSTART (1U << ADC_CR2_SWSTART_BIT)
-#define ADC_CR2_EXTEN (0x3 << 28)
-#define ADC_CR2_EXTEN_DISABLED (0x0 << 28)
-#define ADC_CR2_EXTEN_RISE (0x1 << 28)
-#define ADC_CR2_EXTEN_FALL (0x2 << 28)
-#define ADC_CR2_EXTEN_RISE_FALL (0x3 << 28)
-#define ADC_CR2_EXTSEL (0xF << 24)
-#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24)
-#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24)
-#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24)
-#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24)
-#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24)
-#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24)
-#define ADC_CR2_EXTSEL_TIM1_TRGO (0x6 << 24)
-#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24)
-#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24)
-#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24)
-#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24)
-#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24)
-#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24)
-#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24)
-#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24)
-#define ADC_CR2_EXTSEL_TIM1_EXTI11 (0xF << 24)
-#define ADC_CR2_JSWSTART (1U << ADC_CR2_JSWSTART_BIT)
-#define ADC_CR2_JEXTEN (0x3 << 20)
-#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20)
-#define ADC_CR2_JEXTEN_RISE (0x1 << 20)
-#define ADC_CR2_JEXTEN_FALL (0x2 << 20)
-#define ADC_CR2_JEXTEN_RISE_FALL (0x3 << 20)
-#define ADC_CR2_JEXTSEL (0xF << 16)
-#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16)
-#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16)
-#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16)
-#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16)
-#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16)
-#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16)
-#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16)
-#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16)
-#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16)
-#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16)
-#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16)
-#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16)
-#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16)
-#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16)
-#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16)
-#define ADC_CR2_JEXTSEL_TIM1_EXTI15 (0xF << 16)
-#define ADC_CR2_ALIGN (1U << ADC_CR2_ALIGN_BIT)
-#define ADC_CR2_ALIGN_RIGHT (0U << ADC_CR2_ALIGN_BIT)
-#define ADC_CR2_ALIGN_LEFT (1U << ADC_CR2_ALIGN_BIT)
-#define ADC_CR2_EOCS (1U << ADC_CR2_EOCS_BIT)
-#define ADC_CR2_EOCS_SEQUENCE (0U << ADC_CR2_EOCS_BIT)
-#define ADC_CR2_EOCS_CONVERSION (1U << ADC_CR2_EOCS_BIT)
-#define ADC_CR2_DDS (1U << ADC_CR2_DDS_BIT)
-#define ADC_CR2_DMA (1U << ADC_CR2_DMA_BIT)
-#define ADC_CR2_CONT (1U << ADC_CR2_CONT_BIT)
-#define ADC_CR2_ADON (1U << ADC_CR2_ADON_BIT)
-
-/* Common status register */
-
-#define ADC_CSR_OVR3_BIT 21
-#define ADC_CSR_STRT3_BIT 20
-#define ADC_CSR_JSTRT3_BIT 19
-#define ADC_CSR_JEOC3_BIT 18
-#define ADC_CSR_EOC3_BIT 17
-#define ADC_CSR_AWD3_BIT 16
-#define ADC_CSR_OVR2_BIT 13
-#define ADC_CSR_STRT2_BIT 12
-#define ADC_CSR_JSTRT2_BIT 11
-#define ADC_CSR_JEOC2_BIT 10
-#define ADC_CSR_EOC2_BIT 9
-#define ADC_CSR_AWD2_BIT 8
-#define ADC_CSR_OVR1_BIT 5
-#define ADC_CSR_STRT1_BIT 4
-#define ADC_CSR_JSTRT1_BIT 3
-#define ADC_CSR_JEOC1_BIT 2
-#define ADC_CSR_EOC1_BIT 1
-#define ADC_CSR_AWD1_BIT 0
-
-#define ADC_CSR_OVR3 (1U << ADC_CSR_OVR3_BIT)
-#define ADC_CSR_STRT3 (1U << ADC_CSR_STRT3_BIT)
-#define ADC_CSR_JSTRT3 (1U << ADC_CSR_JSTRT3_BIT)
-#define ADC_CSR_JEOC3 (1U << ADC_CSR_JEOC3_BIT)
-#define ADC_CSR_EOC3 (1U << ADC_CSR_EOC3_BIT)
-#define ADC_CSR_AWD3 (1U << ADC_CSR_AWD3_BIT)
-#define ADC_CSR_OVR2 (1U << ADC_CSR_OVR2_BIT)
-#define ADC_CSR_STRT2 (1U << ADC_CSR_STRT2_BIT)
-#define ADC_CSR_JSTRT2 (1U << ADC_CSR_JSTRT2_BIT)
-#define ADC_CSR_JEOC2 (1U << ADC_CSR_JEOC2_BIT)
-#define ADC_CSR_EOC2 (1U << ADC_CSR_EOC2_BIT)
-#define ADC_CSR_AWD2 (1U << ADC_CSR_AWD2_BIT)
-#define ADC_CSR_OVR1 (1U << ADC_CSR_OVR1_BIT)
-#define ADC_CSR_STRT1 (1U << ADC_CSR_STRT1_BIT)
-#define ADC_CSR_JSTRT1 (1U << ADC_CSR_JSTRT1_BIT)
-#define ADC_CSR_JEOC1 (1U << ADC_CSR_JEOC1_BIT)
-#define ADC_CSR_EOC1 (1U << ADC_CSR_EOC1_BIT)
-#define ADC_CSR_AWD1 (1U << ADC_CSR_AWD1_BIT)
-
-/* Common control register */
-
-#define ADC_CCR_TSVREFE_BIT 23
-#define ADC_CCR_VBATE_BIT 22
-#define ADC_CCR_DDS_BIT 13
-
-#define ADC_CCR_TSVREFE (1U << ADC_CCR_TSVREFE_BIT)
-#define ADC_CCR_VBATE (1U << ADC_CCR_VBATE_BIT)
-#define ADC_CCR_ADCPRE (0x3 << 16)
-#define ADC_CCR_ADCPRE_PCLK2_DIV_2 (0x0 << 16)
-#define ADC_CCR_ADCPRE_PCLK2_DIV_4 (0x1 << 16)
-#define ADC_CCR_ADCPRE_PCLK2_DIV_6 (0x2 << 16)
-#define ADC_CCR_ADCPRE_PCLK2_DIV_8 (0x3 << 16)
-#define ADC_CCR_DMA (0x3 << 14)
-#define ADC_CCR_DMA_DIS (0x0 << 14)
-#define ADC_CCR_DMA_MODE_1 (0x1 << 14)
-#define ADC_CCR_DMA_MODE_2 (0x2 << 14)
-#define ADC_CCR_DMA_MODE_3 (0x3 << 14)
-#define ADC_CCR_DDS (1U << ADC_CCR_DDS_BIT)
-#define ADC_CCR_DELAY (0xF << 8)
-#define ADC_CCR_DELAY_5 (0x0 << 8)
-#define ADC_CCR_DELAY_6 (0x1 << 8)
-#define ADC_CCR_DELAY_7 (0x2 << 8)
-#define ADC_CCR_DELAY_8 (0x3 << 8)
-#define ADC_CCR_DELAY_9 (0x4 << 8)
-#define ADC_CCR_DELAY_10 (0x5 << 8)
-#define ADC_CCR_DELAY_11 (0x6 << 8)
-#define ADC_CCR_DELAY_12 (0x7 << 8)
-#define ADC_CCR_DELAY_13 (0x8 << 8)
-#define ADC_CCR_DELAY_14 (0x9 << 8)
-#define ADC_CCR_DELAY_15 (0xA << 8)
-#define ADC_CCR_DELAY_16 (0xB << 8)
-#define ADC_CCR_DELAY_17 (0xC << 8)
-#define ADC_CCR_DELAY_18 (0xD << 8)
-#define ADC_CCR_DELAY_19 (0xE << 8)
-#define ADC_CCR_DELAY_20 (0xF << 8)
-/** Multi ADC mode selection. */
-#define ADC_CCR_MULTI 0x1F
-/** All ADCs independent. */
-#define ADC_CCR_MULTI_INDEPENDENT 0x0
-/** Dual mode: combined regular simultaneous/injected simultaneous. */
-#define ADC_CCR_MULTI_DUAL_REG_SIM_INJ_SIM 0x1
-/** Dual mode: combined regular simultaneous/alternate trigger. */
-#define ADC_CCR_MULTI_DUAL_REG_SIM_ALT_TRIG 0x2
-/** Dual mode: injected simultaneous mode only. */
-#define ADC_CCR_MULTI_DUAL_INJ_SIM 0x5
-/** Dual mode: regular simultaneous mode only. */
-#define ADC_CCR_MULTI_DUAL_REG_SIM 0x6
-/** Dual mode: interleaved mode only. */
-#define ADC_CCR_MULTI_DUAL_INTER 0x7
-/** Dual mode: alternate trigger mode only. */
-#define ADC_CCR_MULTI_DUAL_ALT_TRIG 0x9
-/** Triple mode: combined regular simultaneous/injected simultaneous. */
-#define ADC_CCR_MULTI_TRIPLE_REG_SIM_INJ_SIM 0x10
-/** Triple mode: combined regular simultaneous/alternate trigger. */
-#define ADC_CCR_MULTI_TRIPLE_REG_SIM_ALT_TRIG 0x11
-/** Triple mode: injected simultaneous mode only. */
-#define ADC_CCR_MULTI_TRIPLE_INJ_SIM 0x12
-/** Triple mode: regular simultaneous mode only. */
-#define ADC_CCR_MULTI_TRIPLE_REG_SIM 0x15
-/** Triple mode: interleaved mode only. */
-#define ADC_CCR_MULTI_TRIPLE_INTER 0x17
-/** Triple mode: alternate trigger mode only. */
-#define ADC_CCR_MULTI_TRIPLE_ALT_TRIG 0x19
-
-/* Common regular data register for dual and triple modes */
-
-#define ADC_CDR_DATA2 0xFFFF0000
-#define ADC_CDR_DATA1 0xFFFF
-
-/*
- * Other types
- */
-
-/**
- * @brief STM32F2 external event selectors for regular group
- * conversion.
- * @see adc_set_extsel()
- */
-typedef enum adc_extsel_event {
- ADC_EXT_EV_TIM1_CC1 = ADC_CR2_EXTSEL_TIM1_CC1,
- ADC_EXT_EV_TIM1_CC2 = ADC_CR2_EXTSEL_TIM1_CC2,
- ADC_EXT_EV_TIM1_CC3 = ADC_CR2_EXTSEL_TIM1_CC3,
- ADC_EXT_EV_TIM2_CC2 = ADC_CR2_EXTSEL_TIM2_CC2,
- ADC_EXT_EV_TIM2_CC3 = ADC_CR2_EXTSEL_TIM2_CC3,
- ADC_EXT_EV_TIM2_CC4 = ADC_CR2_EXTSEL_TIM2_CC4,
- ADC_EXT_EV_TIM1_TRGO = ADC_CR2_EXTSEL_TIM1_TRGO,
- ADC_EXT_EV_TIM3_CC1 = ADC_CR2_EXTSEL_TIM3_CC1,
- ADC_EXT_EV_TIM3_TRGO = ADC_CR2_EXTSEL_TIM3_TRGO,
- ADC_EXT_EV_TIM4_CC4 = ADC_CR2_EXTSEL_TIM4_CC4,
- ADC_EXT_EV_TIM5_CC1 = ADC_CR2_EXTSEL_TIM5_CC1,
- ADC_EXT_EV_TIM5_CC2 = ADC_CR2_EXTSEL_TIM5_CC2,
- ADC_EXT_EV_TIM5_CC3 = ADC_CR2_EXTSEL_TIM5_CC3,
- ADC_EXT_EV_TIM8_CC1 = ADC_CR2_EXTSEL_TIM8_CC1,
- ADC_EXT_EV_TIM8_TRGO = ADC_CR2_EXTSEL_TIM8_TRGO,
- ADC_EXT_EV_TIM1_EXTI11 = ADC_CR2_EXTSEL_TIM1_EXTI11,
-} adc_extsel_event;
-
-/**
- * @brief STM32F2 sample times, in ADC clock cycles.
- */
-typedef enum adc_smp_rate {
- ADC_SMPR_3, /**< 3 ADC cycles */
- ADC_SMPR_15, /**< 15 ADC cycles */
- ADC_SMPR_28, /**< 28 ADC cycles */
- ADC_SMPR_56, /**< 56 ADC cycles */
- ADC_SMPR_84, /**< 84 ADC cycles */
- ADC_SMPR_112, /**< 112 ADC cycles */
- ADC_SMPR_144, /**< 144 ADC cycles */
- ADC_SMPR_480, /**< 480 ADC cycles */
-} adc_smp_rate;
-
-/**
- * @brief STM32F2 ADC prescalers, as divisors of PCLK2.
- */
-typedef enum adc_prescaler {
- /** PCLK2 divided by 2 */
- ADC_PRE_PCLK2_DIV_2 = ADC_CCR_ADCPRE_PCLK2_DIV_2,
- /** PCLK2 divided by 4 */
- ADC_PRE_PCLK2_DIV_4 = ADC_CCR_ADCPRE_PCLK2_DIV_4,
- /** PCLK2 divided by 6 */
- ADC_PRE_PCLK2_DIV_6 = ADC_CCR_ADCPRE_PCLK2_DIV_6,
- /** PCLK2 divided by 8 */
- ADC_PRE_PCLK2_DIV_8 = ADC_CCR_ADCPRE_PCLK2_DIV_8,
-} adc_prescaler;
-
-#endif
diff --git a/libmaple/stm32f2/include/series/dac.h b/libmaple/stm32f2/include/series/dac.h
deleted file mode 100644
index 0a578ca..0000000
--- a/libmaple/stm32f2/include/series/dac.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2012 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/dac.h
- * @brief STM32F2 DAC support
- */
-
-#ifndef _LIBMAPLE_STM32F2_DAC_H_
-#define _LIBMAPLE_STM32F2_DAC_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <libmaple/libmaple_types.h>
-
-/*
- * Register map type
- */
-
-/** STM32F2 DAC register map type. */
-typedef struct dac_reg_map {
- __io uint32 CR; /**< Control register */
- __io uint32 SWTRIGR; /**< Software trigger register */
- __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
- holding register */
- __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
- holding register */
- __io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
- holding register */
- __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
- holding register */
- __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
- holding register */
- __io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
- holding register */
- __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
- holding register */
- __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
- holding register */
- __io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
- register */
- __io uint32 DOR1; /**< Channel 1 data output register */
- __io uint32 DOR2; /**< Channel 2 data output register */
- __io uint32 SR; /**< Status register */
-} dac_reg_map;
-
-/*
- * Register bit definitions
- */
-
-/* Control register */
-
-#define DAC_CR_DMAUDRIE1 (1U << 13) /* Channel 1 DMA underrun
- * interrupt enable */
-#define DAC_CR_DMAUDRIE2 (1U << 29) /* Channel 2 DMA underrun
- * interrupt enable */
-
-/* Status register */
-
-#define DAC_SR_DMAUDR1 (1U << 13) /* Channel 1 DMA underrun
- * occurred */
-#define DAC_SR_DMAUDR2 (1U << 29) /* Channel 2 DMA underrun
- * ocurred */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/libmaple/stm32f2/include/series/dma.h b/libmaple/stm32f2/include/series/dma.h
deleted file mode 100644
index 43bd1a2..0000000
--- a/libmaple/stm32f2/include/series/dma.h
+++ /dev/null
@@ -1,810 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2012 LeafLabs, LLC
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/dma.h
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F2 DMA series header
- */
-
-#ifndef _LIBMAPLE_STM32F2_DMA_H_
-#define _LIBMAPLE_STM32F2_DMA_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <libmaple/dma_common.h>
-#include <libmaple/libmaple_types.h>
-
-/*
- * Register map and base pointers
- */
-
-/**
- * @brief STM32F2 DMA register map type.
- */
-typedef struct dma_reg_map {
- /* Isn't it nice how on F1, it's CCR1, but on F2, it's S1CR? */
-
- /* Global DMA registers */
- __io uint32 LISR; /**< Low interrupt status register */
- __io uint32 HISR; /**< High interrupt status register */
- __io uint32 LIFCR; /**< Low interrupt flag clear register */
- __io uint32 HIFCR; /**< High interrupt flag clear register */
- /* Stream 0 registers */
- __io uint32 S0CR; /**< Stream 0 control register */
- __io uint32 S0NDTR; /**< Stream 0 number of data register */
- __io uint32 S0PAR; /**< Stream 0 peripheral address register */
- __io uint32 S0M0AR; /**< Stream 0 memory 0 address register */
- __io uint32 S0M1AR; /**< Stream 0 memory 1 address register */
- __io uint32 S0FCR; /**< Stream 0 FIFO control register */
- /* Stream 1 registers */
- __io uint32 S1CR; /**< Stream 1 control register */
- __io uint32 S1NDTR; /**< Stream 1 number of data register */
- __io uint32 S1PAR; /**< Stream 1 peripheral address register */
- __io uint32 S1M0AR; /**< Stream 1 memory 0 address register */
- __io uint32 S1M1AR; /**< Stream 1 memory 1 address register */
- __io uint32 S1FCR; /**< Stream 1 FIFO control register */
- /* Stream 2 registers */
- __io uint32 S2CR; /**< Stream 2 control register */
- __io uint32 S2NDTR; /**< Stream 2 number of data register */
- __io uint32 S2PAR; /**< Stream 2 peripheral address register */
- __io uint32 S2M0AR; /**< Stream 2 memory 0 address register */
- __io uint32 S2M1AR; /**< Stream 2 memory 1 address register */
- __io uint32 S2FCR; /**< Stream 2 FIFO control register */
- /* Stream 3 registers */
- __io uint32 S3CR; /**< Stream 3 control register */
- __io uint32 S3NDTR; /**< Stream 3 number of data register */
- __io uint32 S3PAR; /**< Stream 3 peripheral address register */
- __io uint32 S3M0AR; /**< Stream 3 memory 0 address register */
- __io uint32 S3M1AR; /**< Stream 3 memory 1 address register */
- __io uint32 S3FCR; /**< Stream 3 FIFO control register */
- /* Stream 4 registers */
- __io uint32 S4CR; /**< Stream 4 control register */
- __io uint32 S4NDTR; /**< Stream 4 number of data register */
- __io uint32 S4PAR; /**< Stream 4 peripheral address register */
- __io uint32 S4M0AR; /**< Stream 4 memory 0 address register */
- __io uint32 S4M1AR; /**< Stream 4 memory 1 address register */
- __io uint32 S4FCR; /**< Stream 4 FIFO control register */
- /* Stream 5 registers */
- __io uint32 S5CR; /**< Stream 5 control register */
- __io uint32 S5NDTR; /**< Stream 5 number of data register */
- __io uint32 S5PAR; /**< Stream 5 peripheral address register */
- __io uint32 S5M0AR; /**< Stream 5 memory 0 address register */
- __io uint32 S5M1AR; /**< Stream 5 memory 1 address register */
- __io uint32 S5FCR; /**< Stream 5 FIFO control register */
- /* Stream 6 registers */
- __io uint32 S6CR; /**< Stream 6 control register */
- __io uint32 S6NDTR; /**< Stream 6 number of data register */
- __io uint32 S6PAR; /**< Stream 6 peripheral address register */
- __io uint32 S6M0AR; /**< Stream 6 memory 0 address register */
- __io uint32 S6M1AR; /**< Stream 6 memory 1 address register */
- __io uint32 S6FCR; /**< Stream 6 FIFO control register */
- /* Stream 7 registers */
- __io uint32 S7CR; /**< Stream 7 control register */
- __io uint32 S7NDTR; /**< Stream 7 number of data register */
- __io uint32 S7PAR; /**< Stream 7 peripheral address register */
- __io uint32 S7M0AR; /**< Stream 7 memory 0 address register */
- __io uint32 S7M1AR; /**< Stream 7 memory 1 address register */
- __io uint32 S7FCR; /**< Stream 7 FIFO control register */
-} dma_reg_map;
-
-/** DMA controller 1 register map base pointer */
-#define DMA1_BASE ((struct dma_reg_map*)0x40026000)
-/** DMA controller 2 register map base pointer */
-#define DMA2_BASE ((struct dma_reg_map*)0x40026400)
-
-/**
- * @brief STM32F2 DMA stream (i.e. tube) register map type.
- * Provides access to an individual stream's registers.
- * @see dma_tube_regs()
- */
-typedef struct dma_tube_reg_map {
- __io uint32 SCR; /**< Stream configuration register */
- __io uint32 SNDTR; /**< Stream number of data register */
- __io uint32 SPAR; /**< Stream peripheral address register */
- __io uint32 SM0AR; /**< Stream memory 0 address register */
- __io uint32 SM1AR; /**< Stream memory 1 address register */
- __io uint32 SFCR; /**< Stream FIFO control register */
-} dma_tube_reg_map;
-
-/** DMA1 stream 0 register map base pointer */
-#define DMA1S0_BASE ((struct dma_tube_reg_map*)0x40026010)
-/** DMA1 stream 1 register map base pointer */
-#define DMA1S1_BASE ((struct dma_tube_reg_map*)0x40026028)
-/** DMA1 stream 2 register map base pointer */
-#define DMA1S2_BASE ((struct dma_tube_reg_map*)0x40026040)
-/** DMA1 stream 3 register map base pointer */
-#define DMA1S3_BASE ((struct dma_tube_reg_map*)0x40026058)
-/** DMA1 stream 4 register map base pointer */
-#define DMA1S4_BASE ((struct dma_tube_reg_map*)0x40026070)
-/** DMA1 stream 5 register map base pointer */
-#define DMA1S5_BASE ((struct dma_tube_reg_map*)0x40026088)
-/** DMA1 stream 6 register map base pointer */
-#define DMA1S6_BASE ((struct dma_tube_reg_map*)0x400260A0)
-/** DMA1 stream 7 register map base pointer */
-#define DMA1S7_BASE ((struct dma_tube_reg_map*)0x400260B8)
-
-/** DMA2 stream 0 register map base pointer */
-#define DMA2S0_BASE ((struct dma_tube_reg_map*)0x40026410)
-/** DMA2 stream 1 register map base pointer */
-#define DMA2S1_BASE ((struct dma_tube_reg_map*)0x40026028)
-/** DMA2 stream 2 register map base pointer */
-#define DMA2S2_BASE ((struct dma_tube_reg_map*)0x40026040)
-/** DMA2 stream 3 register map base pointer */
-#define DMA2S3_BASE ((struct dma_tube_reg_map*)0x40026058)
-/** DMA2 stream 4 register map base pointer */
-#define DMA2S4_BASE ((struct dma_tube_reg_map*)0x40026070)
-/** DMA2 stream 5 register map base pointer */
-#define DMA2S5_BASE ((struct dma_tube_reg_map*)0x40026088)
-/** DMA2 stream 6 register map base pointer */
-#define DMA2S6_BASE ((struct dma_tube_reg_map*)0x400260A0)
-/** DMA2 stream 7 register map base pointer */
-#define DMA2S7_BASE ((struct dma_tube_reg_map*)0x400260B8)
-
-/*
- * Register bit definitions
- */
-
-/* Low interrupt status register */
-
-#define DMA_LISR_TCIF3_BIT 27
-#define DMA_LISR_HTIF3_BIT 26
-#define DMA_LISR_TEIF3_BIT 25
-#define DMA_LISR_DMEIF3_BIT 24
-#define DMA_LISR_FEIF3_BIT 22
-#define DMA_LISR_TCIF2_BIT 21
-#define DMA_LISR_HTIF2_BIT 20
-#define DMA_LISR_TEIF2_BIT 19
-#define DMA_LISR_DMEIF2_BIT 18
-#define DMA_LISR_FEIF2_BIT 16
-#define DMA_LISR_TCIF1_BIT 11
-#define DMA_LISR_HTIF1_BIT 10
-#define DMA_LISR_TEIF1_BIT 9
-#define DMA_LISR_DMEIF1_BIT 8
-#define DMA_LISR_FEIF1_BIT 6
-#define DMA_LISR_TCIF0_BIT 5
-#define DMA_LISR_HTIF0_BIT 4
-#define DMA_LISR_TEIF0_BIT 3
-#define DMA_LISR_DMEIF0_BIT 2
-#define DMA_LISR_FEIF0_BIT 0
-
-#define DMA_LISR_TCIF3 (1U << DMA_LISR_TCIF3_BIT)
-#define DMA_LISR_HTIF3 (1U << DMA_LISR_HTIF3_BIT)
-#define DMA_LISR_TEIF3 (1U << DMA_LISR_TEIF3_BIT)
-#define DMA_LISR_DMEIF3 (1U << DMA_LISR_DMEIF3_BIT)
-#define DMA_LISR_FEIF3 (1U << DMA_LISR_FEIF3_BIT)
-#define DMA_LISR_TCIF2 (1U << DMA_LISR_TCIF2_BIT)
-#define DMA_LISR_HTIF2 (1U << DMA_LISR_HTIF2_BIT)
-#define DMA_LISR_TEIF2 (1U << DMA_LISR_TEIF2_BIT)
-#define DMA_LISR_DMEIF2 (1U << DMA_LISR_DMEIF2_BIT)
-#define DMA_LISR_FEIF2 (1U << DMA_LISR_FEIF2_BIT)
-#define DMA_LISR_TCIF1 (1U << DMA_LISR_TCIF1_BIT)
-#define DMA_LISR_HTIF1 (1U << DMA_LISR_HTIF1_BIT)
-#define DMA_LISR_TEIF1 (1U << DMA_LISR_TEIF1_BIT)
-#define DMA_LISR_DMEIF1 (1U << DMA_LISR_DMEIF1_BIT)
-#define DMA_LISR_FEIF1 (1U << DMA_LISR_FEIF1_BIT)
-#define DMA_LISR_TCIF0 (1U << DMA_LISR_TCIF0_BIT)
-#define DMA_LISR_HTIF0 (1U << DMA_LISR_HTIF0_BIT)
-#define DMA_LISR_TEIF0 (1U << DMA_LISR_TEIF0_BIT)
-#define DMA_LISR_DMEIF0 (1U << DMA_LISR_DMEIF0_BIT)
-#define DMA_LISR_FEIF0 (1U << DMA_LISR_FEIF0_BIT)
-
-/* High interrupt status register */
-
-#define DMA_HISR_TCIF7_BIT 27
-#define DMA_HISR_HTIF7_BIT 26
-#define DMA_HISR_TEIF7_BIT 25
-#define DMA_HISR_DMEIF7_BIT 24
-#define DMA_HISR_FEIF7_BIT 22
-#define DMA_HISR_TCIF6_BIT 21
-#define DMA_HISR_HTIF6_BIT 20
-#define DMA_HISR_TEIF6_BIT 19
-#define DMA_HISR_DMEIF6_BIT 18
-#define DMA_HISR_FEIF6_BIT 16
-#define DMA_HISR_TCIF5_BIT 11
-#define DMA_HISR_HTIF5_BIT 10
-#define DMA_HISR_TEIF5_BIT 9
-#define DMA_HISR_DMEIF5_BIT 8
-#define DMA_HISR_FEIF5_BIT 6
-#define DMA_HISR_TCIF4_BIT 5
-#define DMA_HISR_HTIF4_BIT 4
-#define DMA_HISR_TEIF4_BIT 3
-#define DMA_HISR_DMEIF4_BIT 2
-#define DMA_HISR_FEIF4_BIT 0
-
-#define DMA_HISR_TCIF7 (1U << DMA_HISR_TCIF7_BIT)
-#define DMA_HISR_HTIF7 (1U << DMA_HISR_HTIF7_BIT)
-#define DMA_HISR_TEIF7 (1U << DMA_HISR_TEIF7_BIT)
-#define DMA_HISR_DMEIF7 (1U << DMA_HISR_DMEIF7_BIT)
-#define DMA_HISR_FEIF7 (1U << DMA_HISR_FEIF7_BIT)
-#define DMA_HISR_TCIF6 (1U << DMA_HISR_TCIF6_BIT)
-#define DMA_HISR_HTIF6 (1U << DMA_HISR_HTIF6_BIT)
-#define DMA_HISR_TEIF6 (1U << DMA_HISR_TEIF6_BIT)
-#define DMA_HISR_DMEIF6 (1U << DMA_HISR_DMEIF6_BIT)
-#define DMA_HISR_FEIF6 (1U << DMA_HISR_FEIF6_BIT)
-#define DMA_HISR_TCIF5 (1U << DMA_HISR_TCIF5_BIT)
-#define DMA_HISR_HTIF5 (1U << DMA_HISR_HTIF5_BIT)
-#define DMA_HISR_TEIF5 (1U << DMA_HISR_TEIF5_BIT)
-#define DMA_HISR_DMEIF5 (1U << DMA_HISR_DMEIF5_BIT)
-#define DMA_HISR_FEIF5 (1U << DMA_HISR_FEIF5_BIT)
-#define DMA_HISR_TCIF4 (1U << DMA_HISR_TCIF4_BIT)
-#define DMA_HISR_HTIF4 (1U << DMA_HISR_HTIF4_BIT)
-#define DMA_HISR_TEIF4 (1U << DMA_HISR_TEIF4_BIT)
-#define DMA_HISR_DMEIF4 (1U << DMA_HISR_DMEIF4_BIT)
-#define DMA_HISR_FEIF4 (1U << DMA_HISR_FEIF4_BIT)
-
-/* Low interrupt flag clear register */
-
-#define DMA_LIFCR_CTCIF3_BIT 27
-#define DMA_LIFCR_CHTIF3_BIT 26
-#define DMA_LIFCR_CTEIF3_BIT 25
-#define DMA_LIFCR_CDMEIF3_BIT 24
-#define DMA_LIFCR_CFEIF3_BIT 22
-#define DMA_LIFCR_CTCIF2_BIT 21
-#define DMA_LIFCR_CHTIF2_BIT 20
-#define DMA_LIFCR_CTEIF2_BIT 19
-#define DMA_LIFCR_CDMEIF2_BIT 18
-#define DMA_LIFCR_CFEIF2_BIT 16
-#define DMA_LIFCR_CTCIF1_BIT 11
-#define DMA_LIFCR_CHTIF1_BIT 10
-#define DMA_LIFCR_CTEIF1_BIT 9
-#define DMA_LIFCR_CDMEIF1_BIT 8
-#define DMA_LIFCR_CFEIF1_BIT 6
-#define DMA_LIFCR_CTCIF0_BIT 5
-#define DMA_LIFCR_CHTIF0_BIT 4
-#define DMA_LIFCR_CTEIF0_BIT 3
-#define DMA_LIFCR_CDMEIF0_BIT 2
-#define DMA_LIFCR_CFEIF0_BIT 0
-
-#define DMA_LIFCR_CTCIF3 (1U << DMA_LIFCR_CTCIF3_BIT)
-#define DMA_LIFCR_CHTIF3 (1U << DMA_LIFCR_CHTIF3_BIT)
-#define DMA_LIFCR_CTEIF3 (1U << DMA_LIFCR_CTEIF3_BIT)
-#define DMA_LIFCR_CDMEIF3 (1U << DMA_LIFCR_CDMEIF3_BIT)
-#define DMA_LIFCR_CFEIF3 (1U << DMA_LIFCR_CFEIF3_BIT)
-#define DMA_LIFCR_CTCIF2 (1U << DMA_LIFCR_CTCIF2_BIT)
-#define DMA_LIFCR_CHTIF2 (1U << DMA_LIFCR_CHTIF2_BIT)
-#define DMA_LIFCR_CTEIF2 (1U << DMA_LIFCR_CTEIF2_BIT)
-#define DMA_LIFCR_CDMEIF2 (1U << DMA_LIFCR_CDMEIF2_BIT)
-#define DMA_LIFCR_CFEIF2 (1U << DMA_LIFCR_CFEIF2_BIT)
-#define DMA_LIFCR_CTCIF1 (1U << DMA_LIFCR_CTCIF1_BIT)
-#define DMA_LIFCR_CHTIF1 (1U << DMA_LIFCR_CHTIF1_BIT)
-#define DMA_LIFCR_CTEIF1 (1U << DMA_LIFCR_CTEIF1_BIT)
-#define DMA_LIFCR_CDMEIF1 (1U << DMA_LIFCR_CDMEIF1_BIT)
-#define DMA_LIFCR_CFEIF1 (1U << DMA_LIFCR_CFEIF1_BIT)
-#define DMA_LIFCR_CTCIF0 (1U << DMA_LIFCR_CTCIF0_BIT)
-#define DMA_LIFCR_CHTIF0 (1U << DMA_LIFCR_CHTIF0_BIT)
-#define DMA_LIFCR_CTEIF0 (1U << DMA_LIFCR_CTEIF0_BIT)
-#define DMA_LIFCR_CDMEIF0 (1U << DMA_LIFCR_CDMEIF0_BIT)
-#define DMA_LIFCR_CFEIF0 (1U << DMA_LIFCR_CFEIF0_BIT)
-
-/* High interrupt flag clear regsister */
-
-#define DMA_HIFCR_CTCIF7_BIT 27
-#define DMA_HIFCR_CHTIF7_BIT 26
-#define DMA_HIFCR_CTEIF7_BIT 25
-#define DMA_HIFCR_CDMEIF7_BIT 24
-#define DMA_HIFCR_CFEIF7_BIT 22
-#define DMA_HIFCR_CTCIF6_BIT 21
-#define DMA_HIFCR_CHTIF6_BIT 20
-#define DMA_HIFCR_CTEIF6_BIT 19
-#define DMA_HIFCR_CDMEIF6_BIT 18
-#define DMA_HIFCR_CFEIF6_BIT 16
-#define DMA_HIFCR_CTCIF5_BIT 11
-#define DMA_HIFCR_CHTIF5_BIT 10
-#define DMA_HIFCR_CTEIF5_BIT 9
-#define DMA_HIFCR_CDMEIF5_BIT 8
-#define DMA_HIFCR_CFEIF5_BIT 6
-#define DMA_HIFCR_CTCIF4_BIT 5
-#define DMA_HIFCR_CHTIF4_BIT 4
-#define DMA_HIFCR_CTEIF4_BIT 3
-#define DMA_HIFCR_CDMEIF4_BIT 2
-#define DMA_HIFCR_CFEIF4_BIT 0
-
-#define DMA_HIFCR_CTCIF7 (1U << DMA_HIFCR_CTCIF7_BIT)
-#define DMA_HIFCR_CHTIF7 (1U << DMA_HIFCR_CHTIF7_BIT)
-#define DMA_HIFCR_CTEIF7 (1U << DMA_HIFCR_CTEIF7_BIT)
-#define DMA_HIFCR_CDMEIF7 (1U << DMA_HIFCR_CDMEIF7_BIT)
-#define DMA_HIFCR_CFEIF7 (1U << DMA_HIFCR_CFEIF7_BIT)
-#define DMA_HIFCR_CTCIF6 (1U << DMA_HIFCR_CTCIF6_BIT)
-#define DMA_HIFCR_CHTIF6 (1U << DMA_HIFCR_CHTIF6_BIT)
-#define DMA_HIFCR_CTEIF6 (1U << DMA_HIFCR_CTEIF6_BIT)
-#define DMA_HIFCR_CDMEIF6 (1U << DMA_HIFCR_CDMEIF6_BIT)
-#define DMA_HIFCR_CFEIF6 (1U << DMA_HIFCR_CFEIF6_BIT)
-#define DMA_HIFCR_CTCIF5 (1U << DMA_HIFCR_CTCIF5_BIT)
-#define DMA_HIFCR_CHTIF5 (1U << DMA_HIFCR_CHTIF5_BIT)
-#define DMA_HIFCR_CTEIF5 (1U << DMA_HIFCR_CTEIF5_BIT)
-#define DMA_HIFCR_CDMEIF5 (1U << DMA_HIFCR_CDMEIF5_BIT)
-#define DMA_HIFCR_CFEIF5 (1U << DMA_HIFCR_CFEIF5_BIT)
-#define DMA_HIFCR_CTCIF4 (1U << DMA_HIFCR_CTCIF4_BIT)
-#define DMA_HIFCR_CHTIF4 (1U << DMA_HIFCR_CHTIF4_BIT)
-#define DMA_HIFCR_CTEIF4 (1U << DMA_HIFCR_CTEIF4_BIT)
-#define DMA_HIFCR_CDMEIF4 (1U << DMA_HIFCR_CDMEIF4_BIT)
-#define DMA_HIFCR_CFEIF4 (1U << DMA_HIFCR_CFEIF4_BIT)
-
-/* Stream configuration register */
-
-#define DMA_SCR_CT_BIT 19
-#define DMA_SCR_DBM_BIT 18
-#define DMA_SCR_PINCOS_BIT 15
-#define DMA_SCR_MINC_BIT 10
-#define DMA_SCR_PINC_BIT 9
-#define DMA_SCR_CIRC_BIT 8
-#define DMA_SCR_PFCTRL_BIT 5
-#define DMA_SCR_TCIE_BIT 4
-#define DMA_SCR_HTIE_BIT 3
-#define DMA_SCR_TEIE_BIT 2
-#define DMA_SCR_DMEIE_BIT 1
-#define DMA_SCR_EN_BIT 0
-
-#define DMA_SCR_CHSEL (0x7 << 25)
-#define DMA_SCR_CHSEL_CH_0 (0x0 << 25)
-#define DMA_SCR_CHSEL_CH_1 (0x1 << 25)
-#define DMA_SCR_CHSEL_CH_2 (0x2 << 25)
-#define DMA_SCR_CHSEL_CH_3 (0x3 << 25)
-#define DMA_SCR_CHSEL_CH_4 (0x4 << 25)
-#define DMA_SCR_CHSEL_CH_5 (0x5 << 25)
-#define DMA_SCR_CHSEL_CH_6 (0x6 << 25)
-#define DMA_SCR_CHSEL_CH_7 (0x7 << 25)
-#define DMA_SCR_MBURST (0x3 << 23)
-#define DMA_SCR_MBURST_SINGLE (0x0 << 23)
-#define DMA_SCR_MBURST_INCR4 (0x1 << 23)
-#define DMA_SCR_MBURST_INCR8 (0x2 << 23)
-#define DMA_SCR_MBURST_INCR16 (0x3 << 23)
-#define DMA_SCR_PBURST (0x3 << 21)
-#define DMA_SCR_PBURST_SINGLE (0x0 << 21)
-#define DMA_SCR_PBURST_INCR4 (0x1 << 21)
-#define DMA_SCR_PBURST_INCR8 (0x2 << 21)
-#define DMA_SCR_PBURST_INCR16 (0x3 << 21)
-#define DMA_SCR_CT (1U << DMA_SCR_CT_BIT)
-#define DMA_SCR_DBM (1U << DMA_SCR_DBM_BIT)
-#define DMA_SCR_PL (0x3 << 16)
-#define DMA_SCR_PL_LOW (0x0 << 16)
-#define DMA_SCR_PL_MEDIUM (0x1 << 16)
-#define DMA_SCR_PL_HIGH (0x2 << 16)
-#define DMA_SCR_VERY_HIGH (0x3 << 16)
-#define DMA_SCR_PINCOS (1U << DMA_SCR_PINCOS_BIT)
-#define DMA_SCR_MSIZE (0x3 << 13)
-#define DMA_SCR_MSIZE_8BITS (0x0 << 13)
-#define DMA_SCR_MSIZE_16BITS (0x1 << 13)
-#define DMA_SCR_MSIZE_32BITS (0x2 << 13)
-#define DMA_SCR_PSIZE (0x3 << 11)
-#define DMA_SCR_PSIZE_8BITS (0x0 << 11)
-#define DMA_SCR_PSIZE_16BITS (0x1 << 11)
-#define DMA_SCR_PSIZE_32BITS (0x2 << 11)
-#define DMA_SCR_MINC (1U << DMA_SCR_MINC_BIT)
-#define DMA_SCR_PINC (1U << DMA_SCR_PINC_BIT)
-#define DMA_SCR_CIRC (1U << DMA_SCR_CIRC_BIT)
-#define DMA_SCR_DIR (0x3 << 6)
-#define DMA_SCR_DIR_PER_TO_MEM (0x0 << 6)
-#define DMA_SCR_DIR_MEM_TO_PER (0x1 << 6)
-#define DMA_SCR_DIR_MEM_TO_MEM (0x2 << 6)
-#define DMA_SCR_PFCTRL (1U << DMA_SCR_PFCTRL_BIT)
-#define DMA_SCR_TCIE (1U << DMA_SCR_TCIE_BIT)
-#define DMA_SCR_HTIE (1U << DMA_SCR_HTIE_BIT)
-#define DMA_SCR_TEIE (1U << DMA_SCR_TEIE_BIT)
-#define DMA_SCR_DMEIE (1U << DMA_SCR_DMEIE_BIT)
-#define DMA_SCR_EN (1U << DMA_SCR_EN_BIT)
-
-/* Stream FIFO control register */
-
-#define DMA_SFCR_FEIE_BIT 7
-#define DMA_SFCR_DMDIS_BIT 2
-
-#define DMA_SFCR_FEIE (1U << DMA_SFCR_FEIE_BIT)
-#define DMA_SFCR_FS (0x7 << 3)
-#define DMA_SFCR_FS_ZERO_TO_QUARTER (0x0 << 3)
-#define DMA_SFCR_FS_QUARTER_TO_HALF (0x1 << 3)
-#define DMA_SFCR_FS_HALF_TO_THREE_QUARTERS (0x2 << 3)
-#define DMA_SFCR_FS_THREE_QUARTERS_TO_FULL (0x3 << 3)
-#define DMA_SFCR_FS_EMPTY (0x4 << 3)
-#define DMA_SFCR_FS_FULL (0x5 << 3)
-#define DMA_SFCR_DMDIS (1U << DMA_SFCR_DMDIS_BIT)
-#define DMA_SFCR_FTH (0x3 << 0)
-#define DMA_SFCR_FTH_QUARTER_FULL (0x0 << 3)
-#define DMA_SFCR_FTH_HALF_FULL (0x1 << 3)
-#define DMA_SFCR_FTH_THREE_QUARTERS_FULL (0x2 << 3)
-#define DMA_SFCR_FTH_FULL (0x3 << 3)
-
-/*
- * Devices
- */
-
-extern dma_dev *DMA1;
-extern dma_dev *DMA2;
-
-/*
- * Other types needed by, or useful for, <libmaple/dma.h>
- */
-
-/**
- * @brief DMA streams
- * This is also the dma_tube type for STM32F2.
- * @see dma_tube
- */
-typedef enum dma_stream {
- DMA_S0 = 0,
- DMA_S1 = 1,
- DMA_S2 = 2,
- DMA_S3 = 3,
- DMA_S4 = 4,
- DMA_S5 = 5,
- DMA_S6 = 6,
- DMA_S7 = 7,
-} dma_stream;
-
-/** STM32F2 dma_tube (=dma_stream) */
-#define dma_tube dma_stream
-
-/**
- * @brief STM32F2 configuration flags for dma_tube_config.
- * @see struct dma_tube_config
- */
-typedef enum dma_cfg_flags {
- /* NB: flags that aren't SCR bits are treated specially. */
-
- /**
- * Source address increment mode
- *
- * If this flag is set, the source address is incremented (by the
- * source size) after each DMA transfer.
- */
- DMA_CFG_SRC_INC = 1U << 31,
-
- /**
- * Destination address increment mode
- *
- * If this flag is set, the destination address is incremented (by
- * the destination size) after each DMA transfer.
- */
- DMA_CFG_DST_INC = 1U << 30,
-
- /**
- * Circular mode
- *
- * This mode is not available for memory-to-memory transfers.
- */
- DMA_CFG_CIRC = DMA_SCR_CIRC,
-
- /** Transfer complete interrupt enable */
- DMA_CFG_CMPLT_IE = DMA_SCR_TCIE,
- /** Transfer half-complete interrupt enable */
- DMA_CFG_HALF_CMPLT_IE = DMA_SCR_HTIE,
- /** Transfer error interrupt enable */
- DMA_CFG_ERR_IE = DMA_SCR_TEIE,
- /** Direct mode error interrupt enable */
- DMA_CFG_DM_ERR_IE = DMA_SCR_DMEIE,
- /** FIFO error interrupt enable */
- DMA_CFG_FIFO_ERR_IE = (1U << 29),
-} dma_cfg_flags;
-
-/**
- * @brief STM32F2 DMA request sources.
- *
- * IMPORTANT:
- *
- * 1. On STM32F2, a particular dma_request_src is always tied to a
- * single DMA controller, but often can be supported by multiple
- * streams. For example, DMA requests from ADC1 (DMA_REQ_SRC_ADC1) can
- * only be handled by DMA2, but they can go to either stream 0 or
- * stream 4 (though not any other stream). If you try to use a request
- * source with the wrong DMA controller or the wrong stream on
- * STM32F2, dma_tube_cfg() will fail.
- *
- * 2. A single stream can only handle a single request source at a
- * time. If you change a stream's request source later, it will stop
- * serving requests from the old source. However, for some streams,
- * some sources conflict with one another (when they correspond to the
- * same channel on that stream), and on STM32F2, Terrible Super-Bad
- * Things will happen if two conflicting request sources are active at
- * the same time.
- *
- * @see struct dma_tube_config
- * @see dma_tube_cfg()
- */
-typedef enum dma_request_src {
- /* These are constructed like so (though this may change, so user
- * code shouldn't depend on it):
- *
- * Bits 0--2: Channel associated with request source
- *
- * Bits 3--9: rcc_clk_id of DMA controller associated with request source
- *
- * Bits 10--17: Bit mask of streams which can handle that request
- * source. (E.g., bit 10 set means stream 0 can
- * handle the source, bit 11 set means stream 1 can,
- * etc.)
- *
- * Among other things, this is used for error checking in
- * dma_tube_cfg(). If you change this bit encoding, you need to
- * update the helper functions in stm32f2/dma.c.
- */
-#define _DMA_STM32F2_REQ_SRC(stream_mask, clk_id, channel) \
- (((stream_mask) << 10) | ((clk_id) << 3) | (channel))
-#define _DMA_S(n) (1U << (n))
-
- /* DMA1 request sources */
-#define _DMA_1_REQ_SRC(stream_mask, channel) \
- _DMA_STM32F2_REQ_SRC(stream_mask, RCC_DMA1, channel)
-
- /* Channel 0 */
- DMA_REQ_SRC_SPI3_RX = _DMA_1_REQ_SRC(_DMA_S(0) | _DMA_S(2), 0),
- DMA_REQ_SRC_SPI2_RX = _DMA_1_REQ_SRC(_DMA_S(3), 0),
- DMA_REQ_SRC_SPI2_TX = _DMA_1_REQ_SRC(_DMA_S(4), 0),
- DMA_REQ_SRC_SPI3_TX = _DMA_1_REQ_SRC(_DMA_S(5) | _DMA_S(7), 0),
-
- /* Channel 1 */
- DMA_REQ_SRC_I2C1_RX = _DMA_1_REQ_SRC(_DMA_S(0) | _DMA_S(5), 1),
- DMA_REQ_SRC_TIM7_UP = _DMA_1_REQ_SRC(_DMA_S(2) | _DMA_S(4), 1),
- DMA_REQ_SRC_I2C1_TX = _DMA_1_REQ_SRC(_DMA_S(6) | _DMA_S(7), 1),
-
- /* Channel 2 */
- DMA_REQ_SRC_TIM4_CH1 = _DMA_1_REQ_SRC(_DMA_S(0), 2),
- DMA_REQ_SRC_TIM4_CH2 = _DMA_1_REQ_SRC(_DMA_S(3), 2),
- DMA_REQ_SRC_TIM4_UP = _DMA_1_REQ_SRC(_DMA_S(6), 2),
- DMA_REQ_SRC_TIM4_CH3 = _DMA_1_REQ_SRC(_DMA_S(7), 2),
-
- /* Channel 3 */
- DMA_REQ_SRC_TIM2_UP = _DMA_1_REQ_SRC(_DMA_S(1) | _DMA_S(7), 3),
- DMA_REQ_SRC_TIM2_CH3 = _DMA_1_REQ_SRC(_DMA_S(1), 3),
- DMA_REQ_SRC_I2C3_RX = _DMA_1_REQ_SRC(_DMA_S(2), 3),
- DMA_REQ_SRC_I2C3_TX = _DMA_1_REQ_SRC(_DMA_S(4), 3),
- DMA_REQ_SRC_TIM2_CH1 = _DMA_1_REQ_SRC(_DMA_S(5), 3),
- DMA_REQ_SRC_TIM2_CH2 = _DMA_1_REQ_SRC(_DMA_S(6), 3),
- DMA_REQ_SRC_TIM2_CH4 = _DMA_1_REQ_SRC(_DMA_S(6) | _DMA_S(7), 3),
-
- /* Channel 4 */
- DMA_REQ_SRC_UART5_RX = _DMA_1_REQ_SRC(_DMA_S(0), 4),
- DMA_REQ_SRC_USART3_RX = _DMA_1_REQ_SRC(_DMA_S(1), 4),
- DMA_REQ_SRC_UART4_RX = _DMA_1_REQ_SRC(_DMA_S(2), 4),
- DMA_REQ_SRC_USART3_TX = _DMA_1_REQ_SRC(_DMA_S(3), 4),
- DMA_REQ_SRC_UART4_TX = _DMA_1_REQ_SRC(_DMA_S(4), 4),
- DMA_REQ_SRC_USART2_RX = _DMA_1_REQ_SRC(_DMA_S(5), 4),
- DMA_REQ_SRC_USART2_TX = _DMA_1_REQ_SRC(_DMA_S(6), 4),
- DMA_REQ_SRC_UART5_TX = _DMA_1_REQ_SRC(_DMA_S(7), 4),
-
- /* Channel 5 */
- DMA_REQ_SRC_TIM3_CH4 = _DMA_1_REQ_SRC(_DMA_S(2), 5),
- DMA_REQ_SRC_TIM3_UP = _DMA_1_REQ_SRC(_DMA_S(2), 5),
- DMA_REQ_SRC_TIM3_CH1 = _DMA_1_REQ_SRC(_DMA_S(4), 5),
- DMA_REQ_SRC_TIM3_TRIG = _DMA_1_REQ_SRC(_DMA_S(4), 5),
- DMA_REQ_SRC_TIM3_CH2 = _DMA_1_REQ_SRC(_DMA_S(5), 5),
- DMA_REQ_SRC_TIM3_CH3 = _DMA_1_REQ_SRC(_DMA_S(7), 5),
-
- /* Channel 6 */
- DMA_REQ_SRC_TIM5_CH3 = _DMA_1_REQ_SRC(_DMA_S(0), 6),
- DMA_REQ_SRC_TIM5_UP = _DMA_1_REQ_SRC(_DMA_S(0) | _DMA_S(6), 6),
- DMA_REQ_SRC_TIM5_CH4 = _DMA_1_REQ_SRC(_DMA_S(1) | _DMA_S(3), 6),
- DMA_REQ_SRC_TIM5_TRIG = _DMA_1_REQ_SRC(_DMA_S(1) | _DMA_S(3), 6),
- DMA_REQ_SRC_TIM5_CH1 = _DMA_1_REQ_SRC(_DMA_S(2), 6),
- DMA_REQ_SRC_TIM5_CH2 = _DMA_1_REQ_SRC(_DMA_S(4), 6),
-
- /* Channel 7 */
- DMA_REQ_SRC_TIM6_UP = _DMA_1_REQ_SRC(_DMA_S(1), 7),
- DMA_REQ_SRC_I2C2_RX = _DMA_1_REQ_SRC(_DMA_S(2) | _DMA_S(3), 7),
- DMA_REQ_SRC_USART3_TX_ALTERNATE = _DMA_1_REQ_SRC(_DMA_S(4), 7),
- DMA_REQ_SRC_DAC1 = _DMA_1_REQ_SRC(_DMA_S(5), 7),
- DMA_REQ_SRC_DAC2 = _DMA_1_REQ_SRC(_DMA_S(6), 7),
- DMA_REQ_SRC_I2C2_TX = _DMA_1_REQ_SRC(_DMA_S(7), 7),
-#undef _DMA_1_REQ_SRC
-
- /* DMA2 request sources */
-#define _DMA_2_REQ_SRC(stream_mask, channel) \
- _DMA_STM32F2_REQ_SRC(stream_mask, RCC_DMA2, channel)
-
- /* Channel 0 */
- DMA_REQ_SRC_ADC1 = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(4), 0),
- /* You can use these "DMA_REQ_SRC_TIMx_CHx_ALTERNATE" if you know
- * what you're doing, but the other ones (for channels 6 and 7),
- * are better, in that they don't conflict with one another. */
- DMA_REQ_SRC_TIM8_CH1_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(2), 0),
- DMA_REQ_SRC_TIM8_CH2_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(2), 0),
- DMA_REQ_SRC_TIM8_CH3_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(2), 0),
- DMA_REQ_SRC_TIM1_CH1_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(6), 0),
- DMA_REQ_SRC_TIM1_CH2_ALTERNATE = _DMA_2_REQ_SRC(_DMA_S(6), 0),
- DMA_REQ_SRC_TIM1_CH3_ALTENRATE = _DMA_2_REQ_SRC(_DMA_S(6), 0),
-
- /* Channel 1 */
- DMA_REQ_SRC_DCMI = _DMA_2_REQ_SRC(_DMA_S(1) | _DMA_S(7), 1),
- DMA_REQ_SRC_ADC2 = _DMA_2_REQ_SRC(_DMA_S(2) | _DMA_S(3), 1),
-
- /* Channel 2 */
- DMA_REQ_SRC_ADC3 = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(1), 2),
- DMA_REQ_SRC_CRYP_OUT = _DMA_2_REQ_SRC(_DMA_S(5), 2),
- DMA_REQ_SRC_CRYP_IN = _DMA_2_REQ_SRC(_DMA_S(6), 2),
- DMA_REQ_SRC_HASH_IN = _DMA_2_REQ_SRC(_DMA_S(7), 2),
-
- /* Channel 3 */
- DMA_REQ_SRC_SPI1_RX = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(2), 3),
- DMA_REQ_SRC_SPI1_TX = _DMA_2_REQ_SRC(_DMA_S(3) | _DMA_S(5), 3),
-
- /* Channel 4 */
- DMA_REQ_SRC_USART1_RX = _DMA_2_REQ_SRC(_DMA_S(2) | _DMA_S(5), 4),
- DMA_REQ_SRC_SDIO = _DMA_2_REQ_SRC(_DMA_S(3) | _DMA_S(6), 4),
- DMA_REQ_SRC_USART1_TX = _DMA_2_REQ_SRC(_DMA_S(7), 4),
-
- /* Channel 5 */
- DMA_REQ_SRC_USART6_RX = _DMA_2_REQ_SRC(_DMA_S(1) | _DMA_S(2), 5),
- DMA_REQ_SRC_USART6_TX = _DMA_2_REQ_SRC(_DMA_S(6) | _DMA_S(7), 5),
-
- /* Channel 6 */
- DMA_REQ_SRC_TIM1_TRIG = _DMA_2_REQ_SRC(_DMA_S(0) | _DMA_S(4), 6),
- DMA_REQ_SRC_TIM1_CH1 = _DMA_2_REQ_SRC(_DMA_S(1) | _DMA_S(3), 6),
- DMA_REQ_SRC_TIM1_CH2 = _DMA_2_REQ_SRC(_DMA_S(3), 6),
- DMA_REQ_SRC_TIM1_CH4 = _DMA_2_REQ_SRC(_DMA_S(4), 6),
- DMA_REQ_SRC_TIM1_COM = _DMA_2_REQ_SRC(_DMA_S(4), 6),
- DMA_REQ_SRC_TIM1_UP = _DMA_2_REQ_SRC(_DMA_S(5), 6),
- DMA_REQ_SRC_TIM1_CH3 = _DMA_2_REQ_SRC(_DMA_S(6), 6),
-
- /* Channel 7 */
- DMA_REQ_SRC_TIM8_UP = _DMA_2_REQ_SRC(_DMA_S(1), 7),
- DMA_REQ_SRC_TIM8_CH1 = _DMA_2_REQ_SRC(_DMA_S(2), 7),
- DMA_REQ_SRC_TIM8_CH2 = _DMA_2_REQ_SRC(_DMA_S(3), 7),
- DMA_REQ_SRC_TIM8_CH3 = _DMA_2_REQ_SRC(_DMA_S(4), 7),
- DMA_REQ_SRC_TIM8_CH4 = _DMA_2_REQ_SRC(_DMA_S(7), 7),
- DMA_REQ_SRC_TIM8_TRIG = _DMA_2_REQ_SRC(_DMA_S(7), 7),
- DMA_REQ_SRC_TIM8_COM = _DMA_2_REQ_SRC(_DMA_S(7), 7),
-#undef _DMA_2_REQ_SRC
-#undef _DMA_S
-} dma_request_src;
-
-/*
- * Tube conveniences
- */
-
-static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev,
- dma_tube tube) {
- ASSERT(DMA_S0 <= tube && tube <= DMA_S7);
- switch (dev->clk_id) {
- case RCC_DMA1:
- return DMA1S0_BASE + (int)tube;
- case RCC_DMA2:
- return DMA2S0_BASE + (int)tube;
- default:
- /* Can't happen */
- ASSERT(0);
- return 0;
- }
-}
-
-static inline uint8 dma_is_enabled(dma_dev *dev, dma_tube tube) {
- return dma_tube_regs(dev, tube)->SCR & DMA_SCR_EN;
-}
-
-/* F2-only; available because of double-buffering. */
-void dma_set_mem_n_addr(dma_dev *dev, dma_tube tube, int n,
- __io void *address);
-
-/**
- * @brief Set memory 0 address.
- * Availability: STM32F2.
- *
- * @param dev DMA device
- * @param tube Tube whose memory 0 address to set
- * @param addr Address to use as memory 0
- */
-static __always_inline void
-dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
- dma_set_mem_n_addr(dev, tube, 0, addr);
-}
-
-/**
- * @brief Set memory 1 address.
- * Availability: STM32F2.
- *
- * @param dev DMA device
- * @param tube Tube whose memory 1 address to set
- * @param addr Address to use as memory 1
- */
-static __always_inline void
-dma_set_mem1_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
- dma_set_mem_n_addr(dev, tube, 1, addr);
-}
-
-/* Assume the user means SM0AR in a non-double-buffered configuration. */
-static __always_inline void
-dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
- dma_set_mem0_addr(dev, tube, addr);
-}
-
-/* SM0AR and SM1AR are treated as though they have the same size */
-static inline dma_xfer_size dma_get_mem_size(dma_dev *dev, dma_tube tube) {
- return (dma_xfer_size)(dma_tube_regs(dev, tube)->SCR >> 13);
-}
-
-static inline dma_xfer_size dma_get_per_size(dma_dev *dev, dma_tube tube) {
- return (dma_xfer_size)(dma_tube_regs(dev, tube)->SCR >> 11);
-}
-
-void dma_enable_fifo(dma_dev *dev, dma_tube tube);
-void dma_disable_fifo(dma_dev *dev, dma_tube tube);
-
-static __always_inline int dma_is_fifo_enabled(dma_dev *dev, dma_tube tube) {
- return dma_tube_regs(dev, tube)->SFCR & DMA_SFCR_DMDIS;
-}
-
-/*
- * TODO:
- * - Double-buffer configuration function
- * - FIFO configuration function
- * - MBURST/PBURST configuration function
- */
-
-/*
- * ISR/IFCR conveniences.
- */
-
-/* (undocumented) helper for reading LISR/HISR and writing
- * LIFCR/HIFCR. For these registers,
- *
- * S0, S4: bits start at bit 0
- * S1, S5: 6
- * S2, S6: 16
- * S3, S7: 22
- *
- * I can't imagine why ST didn't just use a byte for each group. The
- * bits fit, and it would have made functions like these simpler and
- * faster. Oh well. */
-static __always_inline uint32 _dma_sr_fcr_shift(dma_tube tube) {
- switch (tube) {
- case DMA_S0: /* fall through */
- case DMA_S4:
- return 0;
- case DMA_S1: /* fall through */
- case DMA_S5:
- return 6;
- case DMA_S2: /* fall through */
- case DMA_S6:
- return 16;
- case DMA_S3: /* fall through */
- case DMA_S7:
- return 22;
- }
- /* Can't happen */
- ASSERT(0);
- return 0;
-}
-
-static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_tube tube) {
- dma_reg_map *regs = dev->regs;
- __io uint32 *isr = tube > DMA_S3 ? &regs->HISR : &regs->LISR;
- return (*isr >> _dma_sr_fcr_shift(tube)) & 0x3D;
-}
-
-static inline void dma_clear_isr_bits(dma_dev *dev, dma_tube tube) {
- dma_reg_map *regs = dev->regs;
- __io uint32 *ifcr = tube > DMA_S3 ? &regs->HIFCR : &regs->LIFCR;
- *ifcr = (0x3D << _dma_sr_fcr_shift(tube));
-}
-
-#undef _DMA_IRQ_BIT_SHIFT
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/libmaple/stm32f2/include/series/exti.h b/libmaple/stm32f2/include/series/exti.h
deleted file mode 100644
index 4643fcf..0000000
--- a/libmaple/stm32f2/include/series/exti.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2012 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f1/include/series/exti.h
- * @brief STM32F2 external interrupts
- */
-
-#ifndef _LIBMAPLE_STM32F2_EXTI_H_
-#define _LIBMAPLE_STM32F2_EXTI_H_
-
-#ifdef __cpluspus
-extern "C" {
-#endif
-
-struct exti_reg_map;
-#define EXTI_BASE ((struct exti_reg_map*)0x40013C00)
-
-#ifdef __cpluspus
-}
-#endif
-
-#endif
diff --git a/libmaple/stm32f2/include/series/flash.h b/libmaple/stm32f2/include/series/flash.h
deleted file mode 100644
index a3c3933..0000000
--- a/libmaple/stm32f2/include/series/flash.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2011 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/flash.h
- * @brief STM32F2 Flash header.
- *
- * Provides register map, base pointer, and register bit definitions
- * for the Flash controller on the STM32F2 series, along with
- * series-specific configuration values.
- */
-
-#ifndef _LIBMAPLE_STM32F2_FLASH_H_
-#define _LIBMAPLE_STM32F2_FLASH_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <libmaple/libmaple_types.h>
-
-/*
- * Register map
- */
-
-/** @brief STM32F2 Flash register map type */
-typedef struct flash_reg_map {
- __io uint32 ACR; /**< Access control register */
- __io uint32 KEYR; /**< Key register */
- __io uint32 OPTKEYR; /**< Option key register */
- __io uint32 SR; /**< Status register */
- __io uint32 CR; /**< Control register */
- __io uint32 OPTCR; /**< Option control register */
-} flash_reg_map;
-
-#define FLASH_BASE ((struct flash_reg_map*)0x40023C00)
-
-/*
- * Register bit definitions
- */
-
-/* Access control register */
-
-#define FLASH_ACR_DCRST_BIT 12
-#define FLASH_ACR_ICRST_BIT 11
-#define FLASH_ACR_DCEN_BIT 10
-#define FLASH_ACR_ICEN_BIT 9
-#define FLASH_ACR_PRFTEN_BIT 8
-
-#define FLASH_ACR_DCRST (1U << FLASH_ACR_DCRST_BIT)
-#define FLASH_ACR_ICRST (1U << FLASH_ACR_ICRST_BIT)
-#define FLASH_ACR_DCEN (1U << FLASH_ACR_DCEN_BIT)
-#define FLASH_ACR_ICEN (1U << FLASH_ACR_ICEN_BIT)
-#define FLASH_ACR_PRFTEN (1U << FLASH_ACR_PRFTEN_BIT)
-#define FLASH_ACR_LATENCY 0x7
-#define FLASH_ACR_LATENCY_0WS 0x0
-#define FLASH_ACR_LATENCY_1WS 0x1
-#define FLASH_ACR_LATENCY_2WS 0x2
-#define FLASH_ACR_LATENCY_3WS 0x3
-#define FLASH_ACR_LATENCY_4WS 0x4
-#define FLASH_ACR_LATENCY_5WS 0x5
-#define FLASH_ACR_LATENCY_6WS 0x6
-#define FLASH_ACR_LATENCY_7WS 0x7
-
-/* Key register */
-
-#define FLASH_KEYR_KEY1 0x45670123
-#define FLASH_KEYR_KEY2 0xCDEF89AB
-
-/* Option key register */
-
-#define FLASH_OPTKEYR_OPTKEY1 0x08192A3B
-#define FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F
-
-/* Status register */
-
-#define FLASH_SR_BSY_BIT 16
-#define FLASH_SR_PGSERR_BIT 7
-#define FLASH_SR_PGPERR_BIT 6
-#define FLASH_SR_PGAERR_BIT 5
-#define FLASH_SR_WRPERR_BIT 4
-#define FLASH_SR_OPERR_BIT 1
-#define FLASH_SR_EOP_BIT 0
-
-#define FLASH_SR_BSY (1U << FLASH_SR_BSY_BIT)
-#define FLASH_SR_PGSERR (1U << FLASH_SR_PGSERR_BIT)
-#define FLASH_SR_PGPERR (1U << FLASH_SR_PGPERR_BIT)
-#define FLASH_SR_PGAERR (1U << FLASH_SR_PGAERR_BIT)
-#define FLASH_SR_WRPERR (1U << FLASH_SR_WRPERR_BIT)
-#define FLASH_SR_OPERR (1U << FLASH_SR_OPERR_BIT)
-#define FLASH_SR_EOP (1U << FLASH_SR_EOP_BIT)
-
-/* Control register */
-
-#define FLASH_CR_LOCK_BIT 31
-#define FLASH_CR_ERRIE_BIT 25
-#define FLASH_CR_EOPIE_BIT 24
-#define FLASH_CR_STRT_BIT 16
-#define FLASH_CR_MER_BIT 2
-#define FLASH_CR_SER_BIT 1
-#define FLASH_CR_PG_BIT 0
-
-#define FLASH_CR_LOCK (1U << FLASH_CR_LOCK_BIT)
-#define FLASH_CR_ERRIE (1U << FLASH_CR_ERRIE_BIT)
-#define FLASH_CR_EOPIE (1U << FLASH_CR_EOPIE_BIT)
-#define FLASH_CR_STRT (1U << FLASH_CR_STRT_BIT)
-
-#define FLASH_CR_PSIZE (0x3 << 8)
-#define FLASH_CR_PSIZE_MUL8 (0x0 << 8)
-#define FLASH_CR_PSIZE_MUL16 (0x1 << 8)
-#define FLASH_CR_PSIZE_MUL32 (0x2 << 8)
-#define FLASH_CR_PSIZE_MUL64 (0x3 << 8)
-
-#define FLASH_CR_SNB (0xF << 3)
-#define FLASH_CR_SNB_0 (0x0 << 3)
-#define FLASH_CR_SNB_1 (0x1 << 3)
-#define FLASH_CR_SNB_2 (0x2 << 3)
-#define FLASH_CR_SNB_3 (0x3 << 3)
-#define FLASH_CR_SNB_4 (0x4 << 3)
-#define FLASH_CR_SNB_5 (0x5 << 3)
-#define FLASH_CR_SNB_6 (0x6 << 3)
-#define FLASH_CR_SNB_7 (0x7 << 3)
-#define FLASH_CR_SNB_8 (0x8 << 3)
-#define FLASH_CR_SNB_9 (0x9 << 3)
-#define FLASH_CR_SNB_10 (0xA << 3)
-#define FLASH_CR_SNB_11 (0xB << 3)
-
-#define FLASH_CR_MER (1U << FLASH_CR_MER_BIT)
-#define FLASH_CR_SER (1U << FLASH_CR_SER_BIT)
-#define FLASH_CR_PG (1U << FLASH_CR_PG_BIT)
-
-/* Option control register */
-
-#define FLASH_OPTCR_NRST_STDBY_BIT 7
-#define FLASH_OPTCR_NRST_STOP_BIT 6
-#define FLASH_OPTCR_WDG_SW_BIT 5
-#define FLASH_OPTCR_OPTSTRT_BIT 1
-#define FLASH_OPTCR_OPTLOCK_BIT 0
-
-#define FLASH_OPTCR_NWRP (0x3FF << 16)
-
-/* Excluded: The many level 1 values */
-#define FLASH_OPTCR_RDP (0xFF << 8)
-#define FLASH_OPTCR_RDP_LEVEL0 (0xAA << 8)
-#define FLASH_OPTCR_RDP_LEVEL2 (0xCC << 8)
-
-#define FLASH_OPTCR_USER (0x7 << 5)
-#define FLASH_OPTCR_nRST_STDBY (1U << FLASH_OPTCR_nRST_STDBY_BIT)
-#define FLASH_OPTCR_nRST_STOP (1U << FLASH_OPTCR_nRST_STOP_BIT)
-#define FLASH_OPTCR_WDG_SW (1U << FLASH_OPTCR_WDG_SW_BIT)
-
-#define FLASH_OPTCR_BOR_LEV (0x3 << 2)
-#define FLASH_OPTCR_BOR_LEVEL3 (0x0 << 2)
-#define FLASH_OPTCR_BOR_LEVEL2 (0x1 << 2)
-#define FLASH_OPTCR_BOR_LEVEL1 (0x2 << 2)
-#define FLASH_OPTCR_BOR_OFF (0x3 << 2)
-
-#define FLASH_OPTCR_OPTSTRT (1U << FLASH_OPTCR_OPTSTRT_BIT)
-#define FLASH_OPTCR_OPTLOCK (1U << FLASH_OPTCR_OPTLOCK_BIT)
-
-/*
- * Series-specific configuration values
- */
-
-/* Note that this value depends on a 2.7V--3.6V supply voltage */
-#define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_3
-
-/* Flash memory features available via ACR. */
-enum {
- FLASH_PREFETCH = 0x100,
- FLASH_ICACHE = 0x200,
- FLASH_DCACHE = 0x400,
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/libmaple/stm32f2/include/series/gpio.h b/libmaple/stm32f2/include/series/gpio.h
deleted file mode 100644
index 4d0d98c..0000000
--- a/libmaple/stm32f2/include/series/gpio.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2011, 2012 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
-*****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/gpio.h
- * @brief STM32F2 GPIO support.
- */
-
-#ifndef _LIBMAPLE_STM32F2_GPIO_H_
-#define _LIBMAPLE_STM32F2_GPIO_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <libmaple/libmaple_types.h>
-
-/*
- * GPIO register maps and devices
- */
-
-/** GPIO register map type */
-typedef struct gpio_reg_map {
- __io uint32 MODER; /**< Mode register */
- __io uint32 OTYPER; /**< Output type register */
- __io uint32 OSPEEDR; /**< Output speed register */
- __io uint32 PUPDR; /**< Pull-up/pull-down register */
- __io uint32 IDR; /**< Input data register */
- __io uint32 ODR; /**< Output data register */
- __io uint32 BSRR; /**< Bit set/reset register */
- __io uint32 LCKR; /**< Configuration lock register */
- __io uint32 AFRL; /**< Alternate function low register */
- __io uint32 AFRH; /**< Alternate function high register */
-} gpio_reg_map;
-
-/** GPIO port A register map base pointer */
-#define GPIOA_BASE ((struct gpio_reg_map*)0x40020000)
-/** GPIO port B register map base pointer */
-#define GPIOB_BASE ((struct gpio_reg_map*)0x40020400)
-/** GPIO port C register map base pointer */
-#define GPIOC_BASE ((struct gpio_reg_map*)0x40020800)
-/** GPIO port D register map base pointer */
-#define GPIOD_BASE ((struct gpio_reg_map*)0x40020C00)
-/** GPIO port E register map base pointer */
-#define GPIOE_BASE ((struct gpio_reg_map*)0x40021000)
-/** GPIO port F register map base pointer */
-#define GPIOF_BASE ((struct gpio_reg_map*)0x40021400)
-/** GPIO port G register map base pointer */
-#define GPIOG_BASE ((struct gpio_reg_map*)0x40021800)
-/** GPIO port H register map base pointer */
-#define GPIOH_BASE ((struct gpio_reg_map*)0x40021C00)
-/** GPIO port I register map base pointer */
-#define GPIOI_BASE ((struct gpio_reg_map*)0x40022000)
-
-struct gpio_dev;
-extern struct gpio_dev* const GPIOA;
-extern struct gpio_dev gpioa;
-extern struct gpio_dev* const GPIOB;
-extern struct gpio_dev gpiob;
-extern struct gpio_dev* const GPIOC;
-extern struct gpio_dev gpioc;
-extern struct gpio_dev* const GPIOD;
-extern struct gpio_dev gpiod;
-extern struct gpio_dev* const GPIOE;
-extern struct gpio_dev gpioe;
-extern struct gpio_dev* const GPIOF;
-extern struct gpio_dev gpiof;
-extern struct gpio_dev* const GPIOG;
-extern struct gpio_dev gpiog;
-extern struct gpio_dev* const GPIOH;
-extern struct gpio_dev gpioh;
-extern struct gpio_dev* const GPIOI;
-extern struct gpio_dev gpioi;
-
-/*
- * Register bit definitions
- *
- * Currently, we only provide masks to be used for shifting for some
- * registers, rather than repeating the same values 16 times.
- */
-
-/* Mode register */
-
-#define GPIO_MODER_INPUT 0x0
-#define GPIO_MODER_OUTPUT 0x1
-#define GPIO_MODER_AF 0x2
-#define GPIO_MODER_ANALOG 0x3
-
-/* Output type register */
-
-#define GPIO_OTYPER_PP 0x0
-#define GPIO_OTYPER_OD 0x1
-
-/* Output speed register */
-
-#define GPIO_OSPEEDR_LOW 0x0
-#define GPIO_OSPEEDR_MED 0x1
-#define GPIO_OSPEEDR_FAST 0x2
-#define GPIO_OSPEEDR_HIGH 0x3
-
-/* Pull-up/pull-down register */
-
-#define GPIO_PUPDR_NOPUPD 0x0
-#define GPIO_PUPDR_PU 0x1
-#define GPIO_PUPDR_PD 0x2
-
-/* Alternate function register low */
-
-#define GPIO_AFRL_AF0 (0xFU << 0)
-#define GPIO_AFRL_AF1 (0xFU << 4)
-#define GPIO_AFRL_AF2 (0xFU << 8)
-#define GPIO_AFRL_AF3 (0xFU << 12)
-#define GPIO_AFRL_AF4 (0xFU << 16)
-#define GPIO_AFRL_AF5 (0xFU << 20)
-#define GPIO_AFRL_AF6 (0xFU << 24)
-#define GPIO_AFRL_AF7 (0xFU << 28)
-
-/* Alternate function register high */
-
-#define GPIO_AFRH_AF8 (0xFU << 0)
-#define GPIO_AFRH_AF9 (0xFU << 4)
-#define GPIO_AFRH_AF10 (0xFU << 8)
-#define GPIO_AFRH_AF11 (0xFU << 12)
-#define GPIO_AFRH_AF12 (0xFU << 16)
-#define GPIO_AFRH_AF13 (0xFU << 20)
-#define GPIO_AFRH_AF14 (0xFU << 24)
-#define GPIO_AFRH_AF15 (0xFU << 28)
-
-/*
- * GPIO routines
- */
-
-/**
- * @brief GPIO pin modes
- */
-typedef enum gpio_pin_mode {
- GPIO_MODE_INPUT = GPIO_MODER_INPUT, /**< Input mode */
- GPIO_MODE_OUTPUT = GPIO_MODER_OUTPUT, /**< Output mode */
- GPIO_MODE_AF = GPIO_MODER_AF, /**< Alternate function mode */
- GPIO_MODE_ANALOG = GPIO_MODER_ANALOG, /**< Analog mode */
-} gpio_pin_mode;
-
-/**
- * @brief Additional flags to be used when setting a pin's mode.
- *
- * Beyond the basic modes (input, general purpose output, alternate
- * function, and analog), there are three parameters that can affect a
- * pin's mode:
- *
- * 1. Output type: push/pull or open-drain. This only has an effect
- * for output modes. Choices are: GPIO_MODEF_TYPE_PP (the default)
- * and GPIO_MODEF_TYPE_OD.
- *
- * 2. Output speed: specifies the frequency at which a pin changes
- * state. This only has an effect for output modes. Choices are:
- * GPIO_MODEF_SPEED_LOW (default), GPIO_MODEF_SPEED_MED,
- * GPIO_MODEF_SPEED_FAST, and GPIO_MODEF_SPEED_HIGH.
- *
- * 3. Push/pull setting: All GPIO pins have weak pull-up and pull-down
- * resistors that can be enabled when the pin's mode is
- * set. Choices are: GPIO_MODEF_PUPD_NONE (default),
- * GPIO_MODEF_PUPD_PU, and GPIO_MODEF_PUPD_PD.
- */
-typedef enum gpio_mode_flags {
- /* Output type in bit 0 */
- GPIO_MODEF_TYPE_PP = GPIO_OTYPER_PP, /**< Output push/pull (default).
- Applies only when the mode
- specifies output. */
- GPIO_MODEF_TYPE_OD = GPIO_OTYPER_OD, /**< Output open drain.
- Applies only when the mode
- specifies output. */
-
- /* Speed in bits 2:1 */
- GPIO_MODEF_SPEED_LOW = GPIO_OSPEEDR_LOW << 1, /**< Low speed (default):
- 2 MHz. */
- GPIO_MODEF_SPEED_MED = GPIO_OSPEEDR_MED << 1, /**< Medium speed: 25 MHz. */
- GPIO_MODEF_SPEED_FAST = GPIO_OSPEEDR_FAST << 1, /**< Fast speed: 50 MHz. */
- GPIO_MODEF_SPEED_HIGH = GPIO_OSPEEDR_HIGH << 1, /**< High speed:
- 100 MHz on 30 pF,
- 80 MHz on 15 pF. */
-
- /* Pull-up/pull-down in bits 4:3 */
- GPIO_MODEF_PUPD_NONE = GPIO_PUPDR_NOPUPD << 3, /**< No pull-up/pull-down
- (default). */
- GPIO_MODEF_PUPD_PU = GPIO_PUPDR_PU << 3, /**< Pull-up */
- GPIO_MODEF_PUPD_PD = GPIO_PUPDR_PD << 3, /**< Pull-down */
-} gpio_mode_flags;
-
-void gpio_set_modef(struct gpio_dev *dev,
- uint8 bit,
- gpio_pin_mode mode,
- unsigned flags);
-
-/**
- * @brief Set the mode of a GPIO pin.
- *
- * Calling this function is equivalent to calling gpio_set_modef(dev,
- * pin, mode, GPIO_MODE_SPEED_HIGH). Note that this overrides the
- * default speed.
- *
- * @param dev GPIO device.
- * @param bit Bit on the device whose mode to set, 0--15.
- * @param mode Mode to set the pin to.
- */
-static inline void gpio_set_mode(struct gpio_dev *dev,
- uint8 bit,
- gpio_pin_mode mode) {
- gpio_set_modef(dev, bit, mode, GPIO_MODEF_SPEED_HIGH);
-}
-
-/**
- * @brief GPIO alternate functions.
- * Use these to select an alternate function for a pin.
- * @see gpio_set_af()
- */
-typedef enum gpio_af {
- GPIO_AF_SYS = 0, /**< System. */
- GPIO_AF_TIM_1_2 = 1, /**< Timers 1 and 2. */
- GPIO_AF_TIM_3_4_5 = 2, /**< Timers 3, 4, and 5. */
- GPIO_AF_TIM_8_9_10_11 = 3, /**< Timers 8 through 11. */
- GPIO_AF_I2C = 4, /**< I2C 1, 2, and 3. */
- GPIO_AF_SPI_1_2 = 5, /**< SPI1, SPI2/I2S2. */
- GPIO_AF_SPI3 = 6, /**< SPI3/I2S3. */
- GPIO_AF_USART_1_2_3 = 7, /**< USART 1, 2, and 3. */
- GPIO_AF_USART_4_5_6 = 8, /**< UART 4 and 5, USART 6. */
- GPIO_AF_CAN_1_2_TIM_12_13_14 = 9, /**<
- * CAN 1 and 2, timers 12, 13, and 14. */
- GPIO_AF_USB_OTG_FS_HS = 10, /**< USB OTG HS and FS. */
- GPIO_AF_ETH = 11, /**< Ethernet MII and RMII. */
- GPIO_AF_FSMC_SDIO_OTG_FS = 12, /**< FSMC, SDIO, and USB OTG FS. */
- GPIO_AF_DCMI = 13, /**< DCMI. */
- GPIO_AF_EVENTOUT = 15, /**< EVENTOUT. */
-} gpio_af;
-
-void gpio_set_af(struct gpio_dev *dev, uint8 bit, gpio_af af);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/libmaple/stm32f2/include/series/i2c.h b/libmaple/stm32f2/include/series/i2c.h
deleted file mode 100644
index b231256..0000000
--- a/libmaple/stm32f2/include/series/i2c.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung (from <libmaple/i2c.h>).
- * Copyright (c) 2012 LeafLabs, LLC.
- * Copyright (c) 2014 Google, Inc.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-#ifndef _LIBMAPLE_STM32F2_I2C_H_
-#define _LIBMAPLE_STM32F2_I2C_H_
-
-#include <libmaple/i2c_common.h>
-#include <libmaple/stm32.h>
-
-/*
- * Register maps
- */
-
-/** I2C register map type */
-typedef struct i2c_reg_map {
- __io uint32 CR1; /**< Control register 1 */
- __io uint32 CR2; /**< Control register 2 */
- __io uint32 OAR1; /**< Own address register 1 */
- __io uint32 OAR2; /**< Own address register 2 */
- __io uint32 DR; /**< Data register */
- __io uint32 SR1; /**< Status register 1 */
- __io uint32 SR2; /**< Status register 2 */
- __io uint32 CCR; /**< Clock control register */
- __io uint32 TRISE; /**< TRISE (rise time) register */
- __io uint32 FLTR; /**< Noise filter register */
-} i2c_reg_map;
-
-/** I2C1 register map base pointer */
-#define I2C1_BASE ((struct i2c_reg_map*)0x40005400)
-/** I2C2 register map base pointer */
-#define I2C2_BASE ((struct i2c_reg_map*)0x40005800)
-/** I2C3 register map base pointer */
-#define I2C3_BASE ((struct i2c_reg_map*)0x40005C00)
-
-/*
- * Devices
- */
-
-extern i2c_dev* const I2C1;
-extern i2c_dev* const I2C2;
-extern i2c_dev* const I2C3;
-
-/*
- * For internal use
- */
-
-static inline uint32 _i2c_bus_clk(i2c_dev *dev) {
- /* All the I2C peripherals are on APB1 */
- return STM32_PCLK1 / (1000 * 1000);
-}
-
-#undef _I2C_HAVE_IRQ_FIXUP
-#undef _I2C_HAVE_DEPRECATED_I2C_REMAP
-
-#endif /* _LIBMAPLE_STM32F1_I2C_H_ */
diff --git a/libmaple/stm32f2/include/series/nvic.h b/libmaple/stm32f2/include/series/nvic.h
deleted file mode 100644
index dc03806..0000000
--- a/libmaple/stm32f2/include/series/nvic.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2011 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/nvic.h
- * @brief STM32F2 nested vectored interrupt controller (NVIC) header.
- */
-
-#ifndef _LIBMAPLE_STM32F2_NVIC_H_
-#define _LIBMAPLE_STM32F2_NVIC_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/**
- * @brief STM32F2 interrupt vector table interrupt numbers.
- */
-typedef enum nvic_irq_num {
- NVIC_NMI = -14, /**< Non-maskable interrupt */
- NVIC_HARDFAULT = -13, /**< Hard fault (all class of fault) */
- NVIC_MEM_MANAGE = -12, /**< Memory management */
- NVIC_BUS_FAULT = -11, /**< Bus fault: prefetch fault, memory
- access fault. */
- NVIC_USAGE_FAULT = -10, /**< Usage fault: Undefined instruction
- or illegal state. */
- NVIC_SVC = -5, /**< System service call via SWI
- instruction */
- NVIC_DEBUG_MON = -4, /**< Debug monitor */
- NVIC_PEND_SVC = -2, /**< Pendable request for system
- service */
- NVIC_SYSTICK = -1, /**< System tick timer */
- NVIC_WWDG = 0, /**< Window watchdog interrupt */
- NVIC_PVD = 1, /**< PVD through EXTI line detection */
- NVIC_TAMP_STAMP = 2, /**< Tamper and TimeStamp */
- NVIC_RTC_WKUP = 3, /**< Real-time clock wakeup */
- NVIC_FLASH = 4, /**< Flash */
- NVIC_RCC = 5, /**< Reset and clock control */
- NVIC_EXTI0 = 6, /**< EXTI line 0 */
- NVIC_EXTI1 = 7, /**< EXTI line 1 */
- NVIC_EXTI2 = 8, /**< EXTI line 2 */
- NVIC_EXTI3 = 9, /**< EXTI line 3 */
- NVIC_EXTI4 = 10, /**< EXTI line 4 */
- NVIC_DMA1_STREAM0 = 11, /**< DMA1 stream 0 */
- NVIC_DMA1_STREAM1 = 12, /**< DMA1 stream 1 */
- NVIC_DMA1_STREAM2 = 13, /**< DMA1 stream 2 */
- NVIC_DMA1_STREAM3 = 14, /**< DMA1 stream 3 */
- NVIC_DMA1_STREAM4 = 15, /**< DMA1 stream 4 */
- NVIC_DMA1_STREAM5 = 16, /**< DMA1 stream 5 */
- NVIC_DMA1_STREAM6 = 17, /**< DMA1 stream 6 */
- NVIC_ADC = 18, /**< ADC */
- NVIC_CAN1_TX = 19, /**< CAN1 TX */
- NVIC_CAN1_RX0 = 20, /**< CAN1 RX0 */
- NVIC_CAN1_RX1 = 21, /**< CAN1 RX1 */
- NVIC_CAN1_SCE = 22, /**< CAN1 SCE */
- NVIC_EXTI_9_5 = 23, /**< EXTI lines [9:5] */
- NVIC_TIMER1_BRK_TIMER9 = 24, /**< Timer 1 break and timer 9 */
- NVIC_TIMER1_UP_TIMER10 = 25, /**< Timer 1 update and timer 10 */
- NVIC_TIMER1_TRG_COM_TIMER11 = 26, /**< Timer 1 trigger and commutation and
- timer 11.*/
- NVIC_TIMER1_CC = 27, /**< Timer 1 capture and compare */
- NVIC_TIMER2 = 28, /**< Timer 2 */
- NVIC_TIMER3 = 29, /**< Timer 3 */
- NVIC_TIMER4 = 30, /**< Timer 4 */
- NVIC_I2C1_EV = 31, /**< I2C1 event */
- NVIC_I2C1_ER = 32, /**< I2C2 error */
- NVIC_I2C2_EV = 33, /**< I2C2 event */
- NVIC_I2C2_ER = 34, /**< I2C2 error */
- NVIC_SPI1 = 35, /**< SPI1 */
- NVIC_SPI2 = 36, /**< SPI2 */
- NVIC_USART1 = 37, /**< USART1 */
- NVIC_USART2 = 38, /**< USART2 */
- NVIC_USART3 = 39, /**< USART3 */
- NVIC_EXTI_15_10 = 40, /**< EXTI lines [15:10] */
- NVIC_RTCALARM = 41, /**< RTC alarms A and B through EXTI */
- NVIC_OTG_FS_WKUP = 42, /**< USB on-the-go full-speed wakeup
- through EXTI*/
- NVIC_TIMER8_BRK_TIMER12 = 43, /**< Timer 8 break and timer 12 */
- NVIC_TIMER8_UP_TIMER13 = 44, /**< Timer 8 update and timer 13 */
- NVIC_TIMER8_TRG_COM_TIMER14 = 45, /**< Timer 8 trigger and commutation and
- timer 14 */
- NVIC_TIMER8_CC = 46, /**< Timer 8 capture and compare */
- NVIC_DMA1_STREAM7 = 47, /**< DMA1 stream 7 */
- NVIC_FSMC = 48, /**< FSMC */
- NVIC_SDIO = 49, /**< SDIO */
- NVIC_TIMER5 = 50, /**< Timer 5 */
- NVIC_SPI3 = 51, /**< SPI3 */
- NVIC_UART4 = 52, /**< UART4 */
- NVIC_UART5 = 53, /**< UART5 */
- NVIC_TIMER6_DAC = 54, /**< Timer 6 and DAC underrun */
- NVIC_TIMER7 = 55, /**< Timer 7 */
- NVIC_DMA2_STREAM0 = 56, /**< DMA2 stream 0 */
- NVIC_DMA2_STREAM1 = 57, /**< DMA2 stream 1 */
- NVIC_DMA2_STREAM2 = 58, /**< DMA2 stream 2 */
- NVIC_DMA2_STREAM3 = 59, /**< DMA2 stream 3 */
- NVIC_DMA2_STREAM4 = 60, /**< DMA2 stream 4 */
- NVIC_ETH = 61, /**< Ethernet */
- NVIC_ETH_WKUP = 62, /**< Ethernet wakeup through EXTI */
- NVIC_CAN2_TX = 63, /**< CAN2 TX */
- NVIC_CAN2_RX0 = 64, /**< CAN2 RX0 */
- NVIC_CAN2_RX1 = 65, /**< CAN2 RX1 */
- NVIC_CAN2_SCE = 66, /**< CAN2 SCE */
- NVIC_OTG_FS = 67, /**< USB on-the-go full-speed */
- NVIC_DMA2_STREAM5 = 68, /**< DMA2 stream 5 */
- NVIC_DMA2_STREAM6 = 69, /**< DMA2 stream 6 */
- NVIC_DMA2_STREAM7 = 70, /**< DMA2 stream 7 */
- NVIC_USART6 = 71, /**< USART6 */
- NVIC_I2C3_EV = 72, /**< I2C3 event */
- NVIC_I2C3_ER = 73, /**< I2C3 error */
- NVIC_OTG_HS_EP1_OUT = 74, /**< USB on-the-go high-speed
- endpoint 1 OUT */
- NVIC_OTG_HS_EP1_IN = 75, /**< USB on-the-go high-speed
- endpoint 1 IN */
- NVIC_OTG_HS_WKUP = 76, /**< USB on-the-go high-speed wakeup
- through EXTI*/
- NVIC_OTG_HS = 77, /**< USB on-the-go high-speed */
- NVIC_DCMI = 78, /**< DCMI */
- NVIC_CRYP = 79, /**< Cryptographic processor */
- NVIC_HASH_RNG = 80, /**< Hash and random number
- generation */
-
- /* Fake enumerator values, for compatiblity with F1.
- * TODO decide if this is actually a good idea. */
- NVIC_TIMER6 = NVIC_TIMER6_DAC, /**< For compatibility with STM32F1. */
-} nvic_irq_num;
-
-static inline void nvic_irq_disable_all(void) {
- NVIC_BASE->ICER[0] = 0xFFFFFFFF;
- NVIC_BASE->ICER[1] = 0xFFFFFFFF;
- NVIC_BASE->ICER[2] = 0xFFFFFFFF;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/libmaple/stm32f2/include/series/pwr.h b/libmaple/stm32f2/include/series/pwr.h
deleted file mode 100644
index 96353a4..0000000
--- a/libmaple/stm32f2/include/series/pwr.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2012 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/pwr.h
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F2 Power control (PWR) support.
- */
-
-#ifndef _LIBMAPLE_STM32F2_PWR_H_
-#define _LIBMAPLE_STM32F2_PWR_H_
-
-/*
- * Additional register bits
- */
-
-/* Control register */
-
-/**
- * @brief Flash power down in stop mode bit.
- * Availability: STM32F2 */
-#define PWR_CR_FPDS_BIT 9
-/**
- * @brief Flash power down in stop mode.
- * Availability: STM32F2 */
-#define PWR_CR_FPDS (1U << PWR_CR_FPDS_BIT)
-
-/* PVD level selection */
-#define PWR_CR_PLS_2_0V (0x0 << 5)
-#define PWR_CR_PLS_2_1V (0x1 << 5)
-#define PWR_CR_PLS_2_3V (0x2 << 5)
-#define PWR_CR_PLS_2_5V (0x3 << 5)
-#define PWR_CR_PLS_2_6V (0x4 << 5)
-#define PWR_CR_PLS_2_7V (0x5 << 5)
-#define PWR_CR_PLS_2_8V (0x6 << 5)
-#define PWR_CR_PLS_2_9V (0x7 << 5)
-
-/* Control/Status register */
-
-/** Backup regulator enable bit. */
-#define PWR_CSR_BRE_BIT 9
-/** Backup regulator ready bit. */
-#define PWR_CSR_BRR_BIT 3
-
-/** Backup regulator enable. */
-#define PWR_CSR_BRE (1U << PWR_CSR_BRE_BIT)
-/** Backup regulator ready. */
-#define PWR_CSR_BRR (1U << PWR_CSR_BRR_BIT)
-
-#endif
diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h
deleted file mode 100644
index 441a5a8..0000000
--- a/libmaple/stm32f2/include/series/rcc.h
+++ /dev/null
@@ -1,951 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2011 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/rcc.h
- * @brief STM32F2 reset and clock control (RCC) support.
- */
-
-#ifndef _LIBMAPLE_STM32F2_RCC_H_
-#define _LIBMAPLE_STM32F2_RCC_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <libmaple/libmaple_types.h>
-
-/*
- * Register map
- */
-
-/** STM32F2 RCC register map type */
-typedef struct rcc_reg_map {
- __io uint32 CR; /**< Clock control register */
- __io uint32 PLLCFGR; /**< PLL configuration register */
- __io uint32 CFGR; /**< Clock configuration register */
- __io uint32 CIR; /**< Clock interrupt register */
- __io uint32 AHB1RSTR; /**< AHB1 peripheral reset register */
- __io uint32 AHB2RSTR; /**< AHB2 peripheral reset register */
- __io uint32 AHB3RSTR; /**< AHB3 peripheral reset register */
- const uint32 RESERVED1; /**< Reserved */
- __io uint32 APB1RSTR; /**< APB1 peripheral reset register */
- __io uint32 APB2RSTR; /**< APB2 peripheral reset register */
- const uint32 RESERVED2; /**< Reserved */
- const uint32 RESERVED3; /**< Reserved */
- __io uint32 AHB1ENR; /**< AHB1 peripheral clock enable register */
- __io uint32 AHB2ENR; /**< AHB2 peripheral clock enable register */
- __io uint32 AHB3ENR; /**< AHB3 peripheral clock enable register */
- const uint32 RESERVED4; /**< Reserved */
- __io uint32 APB1ENR; /**< APB1 peripheral clock enable register */
- __io uint32 APB2ENR; /**< APB2 peripheral clock enable register */
- const uint32 RESERVED5; /**< Reserved */
- const uint32 RESERVED6; /**< Reserved */
- __io uint32 AHB1LPENR; /**< AHB1 peripheral clock enable in
- low power mode register */
- __io uint32 AHB2LPENR; /**< AHB2 peripheral clock enable in
- low power mode register */
- __io uint32 AHB3LPENR; /**< AHB3 peripheral clock enable in
- low power mode register */
- const uint32 RESERVED7; /**< Reserved */
- __io uint32 APB1LPENR; /**< APB1 peripheral clock enable in
- low power mode register */
- __io uint32 APB2LPENR; /**< APB2 peripheral clock enable in
- low power mode register */
- const uint32 RESERVED8; /**< Reserved */
- const uint32 RESERVED9; /**< Reserved */
- __io uint32 BDCR; /**< Backup domain control register */
- __io uint32 CSR; /**< Clock control and status register */
- const uint32 RESERVED10; /**< Reserved */
- const uint32 RESERVED11; /**< Reserved */
- __io uint32 SSCGR; /**< Spread spectrum clock generation
- register */
- __io uint32 PLLI2SCFGR; /**< PLLI2S configuration register */
-} rcc_reg_map;
-
-#define RCC_BASE ((struct rcc_reg_map*)0x40023800)
-
-/*
- * Register bit definitions
- */
-
-/* Clock control register */
-
-#define RCC_CR_PLLI2SRDY_BIT 27
-#define RCC_CR_PLLI2SON_BIT 26
-#define RCC_CR_PLLRDY_BIT 25
-#define RCC_CR_PLLON_BIT 24
-#define RCC_CR_CSSON_BIT 19
-#define RCC_CR_HSEBYP_BIT 18
-#define RCC_CR_HSERDY_BIT 17
-#define RCC_CR_HSEON_BIT 16
-#define RCC_CR_HSIRDY_BIT 1
-#define RCC_CR_HSION_BIT 0
-
-#define RCC_CR_PLLI2SRDY (1U << RCC_CR_PLLI2SRDY_BIT)
-#define RCC_CR_PLLI2SON (1U << RCC_CR_PLLI2SON_BIT)
-#define RCC_CR_PLLRDY (1U << RCC_CR_PLLRDY_BIT)
-#define RCC_CR_PLLON (1U << RCC_CR_PLLON_BIT)
-#define RCC_CR_CSSON (1U << RCC_CR_CSSON_BIT)
-#define RCC_CR_HSEBYP (1U << RCC_CR_HSEBYP_BIT)
-#define RCC_CR_HSERDY (1U << RCC_CR_HSERDY_BIT)
-#define RCC_CR_HSEON (1U << RCC_CR_HSEON_BIT)
-#define RCC_CR_HSICAL (0xFF << 8)
-#define RCC_CR_HSITRIM (0x1F << 3)
-#define RCC_CR_HSIRDY (1U << RCC_CR_HSIRDY_BIT)
-#define RCC_CR_HSION (1U << RCC_CR_HSION_BIT)
-
-/* PLL configuration register */
-
-#define RCC_PLLCFGR_PLLSRC_BIT 22
-
-#define RCC_PLLCFGR_PLLQ (0xF << 24)
-#define RCC_PLLCFGR_PLLSRC (1U << RCC_PLLCFGR_PLLSRC_BIT)
-#define RCC_PLLCFGR_PLLSRC_HSI (0x0 << RCC_PLLCFGR_PLLSRC_BIT)
-#define RCC_PLLCFGR_PLLSRC_HSE (0x1 << RCC_PLLCFGR_PLLSRC_BIT)
-#define RCC_PLLCFGR_PLLP (0x3 << 16)
-#define RCC_PLLCFGR_PLLN (0x1FF << 6)
-#define RCC_PLLCFGR_PLLM 0x1F
-
-/* Clock configuration register */
-
-#define RCC_CFGR_I2SSRC_BIT 23
-
-#define RCC_CFGR_MCO2 (0x3 << 30)
-#define RCC_CFGR_MCO2_SYSCLK (0x0 << 30)
-#define RCC_CFGR_MCO2_PLLI2S (0x1 << 30)
-#define RCC_CFGR_MCO2_HSE (0x2 << 30)
-#define RCC_CFGR_MCO2_PLL (0x3 << 30)
-
-#define RCC_CFGR_MCO2PRE (0x7 << 27)
-#define RCC_CFGR_MCO2PRE_DIV_1 (0x0 << 27)
-#define RCC_CFGR_MCO2PRE_DIV_2 (0x4 << 27)
-#define RCC_CFGR_MCO2PRE_DIV_3 (0x5 << 27)
-#define RCC_CFGR_MCO2PRE_DIV_4 (0x6 << 27)
-#define RCC_CFGR_MCO2PRE_DIV_5 (0x7 << 27)
-
-#define RCC_CFGR_MCO1PRE (0x7 << 24)
-#define RCC_CFGR_MCO1PRE_DIV_1 (0x0 << 24)
-#define RCC_CFGR_MCO1PRE_DIV_2 (0x4 << 24)
-#define RCC_CFGR_MCO1PRE_DIV_3 (0x5 << 24)
-#define RCC_CFGR_MCO1PRE_DIV_4 (0x6 << 24)
-#define RCC_CFGR_MCO1PRE_DIV_5 (0x7 << 24)
-
-#define RCC_CFGR_I2SSRC (1U << RCC_CFGR_I2SSRC_BIT)
-#define RCC_CFGR_I2SSRC_PLLI2S (0 << RCC_CFGR_I2SSRC_BIT)
-#define RCC_CFGR_I2SSRC_I2S_CKIN (1 << RCC_CFGR_I2SSRC_BIT)
-
-#define RCC_CFGR_MCO1 (0x3 << 21)
-#define RCC_CFGR_MCO1_HSI (0x0 << 21)
-#define RCC_CFGR_MCO1_LSE (0x1 << 21)
-#define RCC_CFGR_MCO1_HSE (0x2 << 21)
-#define RCC_CFGR_MCO1_PLL (0x3 << 21)
-
-#define RCC_CFGR_RTCPRE (0x1F << 16)
-
-/* Skipped: all the 0b0xx values meaning "not divided" */
-#define RCC_CFGR_PPRE2 (0x7 << 13)
-#define RCC_CFGR_PPRE2_AHB_DIV_2 (0x4 << 13)
-#define RCC_CFGR_PPRE2_AHB_DIV_4 (0x5 << 13)
-#define RCC_CFGR_PPRE2_AHB_DIV_8 (0x6 << 13)
-#define RCC_CFGR_PPRE2_AHB_DIV_16 (0x7 << 13)
-
-/* Skipped: all the 0b0xx values meaning "not divided" */
-#define RCC_CFGR_PPRE1 (0x7 << 10)
-#define RCC_CFGR_PPRE1_AHB_DIV_2 (0x4 << 10)
-#define RCC_CFGR_PPRE1_AHB_DIV_4 (0x5 << 10)
-#define RCC_CFGR_PPRE1_AHB_DIV_8 (0x6 << 10)
-#define RCC_CFGR_PPRE1_AHB_DIV_16 (0x7 << 10)
-
-/* Skipped: all the 0b0xxx values meaning "not divided" */
-#define RCC_CFGR_HPRE (0xF << 4)
-#define RCC_CFGR_HPRE_SYSCLK_DIV_2 (0x8 << 4)
-#define RCC_CFGR_HPRE_SYSCLK_DIV_4 (0x9 << 4)
-#define RCC_CFGR_HPRE_SYSCLK_DIV_8 (0xA << 4)
-#define RCC_CFGR_HPRE_SYSCLK_DIV_16 (0xB << 4)
-#define RCC_CFGR_HPRE_SYSCLK_DIV_64 (0xC << 4)
-#define RCC_CFGR_HPRE_SYSCLK_DIV_128 (0xD << 4)
-#define RCC_CFGR_HPRE_SYSCLK_DIV_256 (0xE << 4)
-#define RCC_CFGR_HPRE_SYSCLK_DIV_512 (0xF << 4)
-
-#define RCC_CFGR_SWS (0x3 << 2)
-#define RCC_CFGR_SWS_HSI (0x0 << 2)
-#define RCC_CFGR_SWS_HSE (0x1 << 2)
-#define RCC_CFGR_SWS_PLL (0x2 << 2)
-
-#define RCC_CFGR_SW 0x3
-#define RCC_CFGR_SW_HSI 0x0
-#define RCC_CFGR_SW_HSE 0x1
-#define RCC_CFGR_SW_PLL 0x2
-
-/* Clock interrupt register */
-
-#define RCC_CIR_CSSC_BIT 23
-
-#define RCC_CIR_PLLI2SRDYC_BIT 21
-#define RCC_CIR_PLLRDYC_BIT 20
-#define RCC_CIR_HSERDYC_BIT 19
-#define RCC_CIR_HSIRDYC_BIT 18
-#define RCC_CIR_LSERDYC_BIT 17
-#define RCC_CIR_LSIRDYC_BIT 16
-
-#define RCC_CIR_PLLI2SRDYIE_BIT 13
-#define RCC_CIR_PLLRDYIE_BIT 12
-#define RCC_CIR_HSERDYIE_BIT 11
-#define RCC_CIR_HSIRDYIE_BIT 10
-#define RCC_CIR_LSERDYIE_BIT 9
-#define RCC_CIR_LSIRDYIE_BIT 8
-
-#define RCC_CIR_CSSF_BIT 7
-
-#define RCC_CIR_PLLI2SRDYF_BIT 5
-#define RCC_CIR_PLLRDYF_BIT 4
-#define RCC_CIR_HSERDYF_BIT 3
-#define RCC_CIR_HSIRDYF_BIT 2
-#define RCC_CIR_LSERDYF_BIT 1
-#define RCC_CIR_LSIRDYF_BIT 0
-
-#define RCC_CIR_CSSC (1U << RCC_CIR_CSSC_BIT)
-
-#define RCC_CIR_PLLI2SRDYC (1U << RCC_CIR_PLLI2SRDYC_BIT)
-#define RCC_CIR_PLLRDYC (1U << RCC_CIR_PLLRDYC_BIT)
-#define RCC_CIR_HSERDYC (1U << RCC_CIR_HSERDYC_BIT)
-#define RCC_CIR_HSIRDYC (1U << RCC_CIR_HSIRDYC_BIT)
-#define RCC_CIR_LSERDYC (1U << RCC_CIR_LSERDYC_BIT)
-#define RCC_CIR_LSIRDYC (1U << RCC_CIR_LSIRDYC_BIT)
-
-#define RCC_CIR_PLLI2SRDYIE (1U << RCC_CIR_PLLI2SRDYIE_BIT)
-#define RCC_CIR_PLLRDYIE (1U << RCC_CIR_PLLRDYIE_BIT)
-#define RCC_CIR_HSERDYIE (1U << RCC_CIR_HSERDYIE_BIT)
-#define RCC_CIR_HSIRDYIE (1U << RCC_CIR_HSIRDYIE_BIT)
-#define RCC_CIR_LSERDYIE (1U << RCC_CIR_LSERDYIE_BIT)
-#define RCC_CIR_LSIRDYIE (1U << RCC_CIR_LSIRDYIE_BIT)
-
-#define RCC_CIR_CSSF (1U << RCC_CIR_CSSF_BIT)
-
-#define RCC_CIR_PLLI2SRDYF (1U << RCC_CIR_PLLI2SRDYF_BIT)
-#define RCC_CIR_PLLRDYF (1U << RCC_CIR_PLLRDYF_BIT)
-#define RCC_CIR_HSERDYF (1U << RCC_CIR_HSERDYF_BIT)
-#define RCC_CIR_HSIRDYF (1U << RCC_CIR_HSIRDYF_BIT)
-#define RCC_CIR_LSERDYF (1U << RCC_CIR_LSERDYF_BIT)
-#define RCC_CIR_LSIRDYF (1U << RCC_CIR_LSIRDYF_BIT)
-
-/* AHB1 peripheral reset register */
-
-#define RCC_AHB1RSTR_OTGHSRST_BIT 29
-#define RCC_AHB1RSTR_ETHMACRST_BIT 25
-#define RCC_AHB1RSTR_DMA2RST_BIT 22
-#define RCC_AHB1RSTR_DMA1RST_BIT 21
-#define RCC_AHB1RSTR_CRCRST_BIT 12
-#define RCC_AHB1RSTR_GPIOIRST_BIT 8
-#define RCC_AHB1RSTR_GPIOHRST_BIT 7
-#define RCC_AHB1RSTR_GPIOGRST_BIT 6
-#define RCC_AHB1RSTR_GPIOFRST_BIT 5
-#define RCC_AHB1RSTR_GPIOERST_BIT 4
-#define RCC_AHB1RSTR_GPIODRST_BIT 3
-#define RCC_AHB1RSTR_GPIOCRST_BIT 2
-#define RCC_AHB1RSTR_GPIOBRST_BIT 1
-#define RCC_AHB1RSTR_GPIOARST_BIT 0
-
-#define RCC_AHB1RSTR_OTGHSRST (1U << RCC_AHB1RSTR_OTGHSRST_BIT)
-#define RCC_AHB1RSTR_ETHMACRST (1U << RCC_AHB1RSTR_ETHMACRST_BIT)
-#define RCC_AHB1RSTR_DMA2RST (1U << RCC_AHB1RSTR_DMA2RST_BIT)
-#define RCC_AHB1RSTR_DMA1RST (1U << RCC_AHB1RSTR_DMA1RST_BIT)
-#define RCC_AHB1RSTR_CRCRST (1U << RCC_AHB1RSTR_CRCRST_BIT)
-#define RCC_AHB1RSTR_GPIOIRST (1U << RCC_AHB1RSTR_GPIOIRST_BIT)
-#define RCC_AHB1RSTR_GPIOHRST (1U << RCC_AHB1RSTR_GPIOHRST_BIT)
-#define RCC_AHB1RSTR_GPIOGRST (1U << RCC_AHB1RSTR_GPIOGRST_BIT)
-#define RCC_AHB1RSTR_GPIOFRST (1U << RCC_AHB1RSTR_GPIOFRST_BIT)
-#define RCC_AHB1RSTR_GPIOERST (1U << RCC_AHB1RSTR_GPIOERST_BIT)
-#define RCC_AHB1RSTR_GPIODRST (1U << RCC_AHB1RSTR_GPIODRST_BIT)
-#define RCC_AHB1RSTR_GPIOCRST (1U << RCC_AHB1RSTR_GPIOCRST_BIT)
-#define RCC_AHB1RSTR_GPIOBRST (1U << RCC_AHB1RSTR_GPIOBRST_BIT)
-#define RCC_AHB1RSTR_GPIOARST (1U << RCC_AHB1RSTR_GPIOARST_BIT)
-
-/* AHB2 peripheral reset register */
-
-#define RCC_AHB2RSTR_OTGFSRST_BIT 7
-#define RCC_AHB2RSTR_RNGRST_BIT 6
-#define RCC_AHB2RSTR_HASHRST_BIT 5
-#define RCC_AHB2RSTR_CRYPRST_BIT 4
-#define RCC_AHB2RSTR_DCMIRST_BIT 0
-
-#define RCC_AHB2RSTR_OTGFSRST (1U << RCC_AHB2RSTR_OTGFSRST_BIT)
-#define RCC_AHB2RSTR_RNGRST (1U << RCC_AHB2RSTR_RNGRST_BIT)
-#define RCC_AHB2RSTR_HASHRST (1U << RCC_AHB2RSTR_HASHRST_BIT)
-#define RCC_AHB2RSTR_CRYPRST (1U << RCC_AHB2RSTR_CRYPRST_BIT)
-#define RCC_AHB2RSTR_DCMIRST (1U << RCC_AHB2RSTR_DCMIRST_BIT)
-
-/* AHB3 peripheral reset register */
-
-#define RCC_AHB3RSTR_FSMCRST_BIT 0
-
-#define RCC_AHB3RSTR_FSMCRST (1U << RCC_AHB3RSTR_FSMCRST_BIT)
-
-/* APB1 peripheral reset register */
-
-#define RCC_APB1RSTR_DACRST_BIT 29
-#define RCC_APB1RSTR_PWRRST_BIT 28
-#define RCC_APB1RSTR_CAN2RST_BIT 26
-#define RCC_APB1RSTR_CAN1RST_BIT 25
-#define RCC_APB1RSTR_I2C3RST_BIT 23
-#define RCC_APB1RSTR_I2C2RST_BIT 22
-#define RCC_APB1RSTR_I2C1RST_BIT 21
-#define RCC_APB1RSTR_UART5RST_BIT 20
-#define RCC_APB1RSTR_UART4RST_BIT 19
-#define RCC_APB1RSTR_UART3RST_BIT 18
-#define RCC_APB1RSTR_UART2RST_BIT 17
-#define RCC_APB1RSTR_SPI3RST_BIT 15
-#define RCC_APB1RSTR_SPI2RST_BIT 14
-#define RCC_APB1RSTR_WWDGRST_BIT 11
-#define RCC_APB1RSTR_TIM14RST_BIT 8
-#define RCC_APB1RSTR_TIM13RST_BIT 7
-#define RCC_APB1RSTR_TIM12RST_BIT 6
-#define RCC_APB1RSTR_TIM7RST_BIT 5
-#define RCC_APB1RSTR_TIM6RST_BIT 4
-#define RCC_APB1RSTR_TIM5RST_BIT 3
-#define RCC_APB1RSTR_TIM4RST_BIT 2
-#define RCC_APB1RSTR_TIM3RST_BIT 1
-#define RCC_APB1RSTR_TIM2RST_BIT 0
-
-#define RCC_APB1RSTR_DACRST (1U << RCC_APB1RSTR_DACRST_BIT)
-#define RCC_APB1RSTR_PWRRST (1U << RCC_APB1RSTR_PWRRST_BIT)
-#define RCC_APB1RSTR_CAN2RST (1U << RCC_APB1RSTR_CAN2RST_BIT)
-#define RCC_APB1RSTR_CAN1RST (1U << RCC_APB1RSTR_CAN1RST_BIT)
-#define RCC_APB1RSTR_I2C3RST (1U << RCC_APB1RSTR_I2C3RST_BIT)
-#define RCC_APB1RSTR_I2C2RST (1U << RCC_APB1RSTR_I2C2RST_BIT)
-#define RCC_APB1RSTR_I2C1RST (1U << RCC_APB1RSTR_I2C1RST_BIT)
-#define RCC_APB1RSTR_UART5RST (1U << RCC_APB1RSTR_UART5RST_BIT)
-#define RCC_APB1RSTR_UART4RST (1U << RCC_APB1RSTR_UART4RST_BIT)
-#define RCC_APB1RSTR_UART3RST (1U << RCC_APB1RSTR_UART3RST_BIT)
-#define RCC_APB1RSTR_UART2RST (1U << RCC_APB1RSTR_UART2RST_BIT)
-#define RCC_APB1RSTR_SPI3RST (1U << RCC_APB1RSTR_SPI3RST_BIT)
-#define RCC_APB1RSTR_SPI2RST (1U << RCC_APB1RSTR_SPI2RST_BIT)
-#define RCC_APB1RSTR_WWDGRST (1U << RCC_APB1RSTR_WWDGRST_BIT)
-#define RCC_APB1RSTR_TIM14RST (1U << RCC_APB1RSTR_TIM14RST_BIT)
-#define RCC_APB1RSTR_TIM13RST (1U << RCC_APB1RSTR_TIM13RST_BIT)
-#define RCC_APB1RSTR_TIM12RST (1U << RCC_APB1RSTR_TIM12RST_BIT)
-#define RCC_APB1RSTR_TIM7RST (1U << RCC_APB1RSTR_TIM7RST_BIT)
-#define RCC_APB1RSTR_TIM6RST (1U << RCC_APB1RSTR_TIM6RST_BIT)
-#define RCC_APB1RSTR_TIM5RST (1U << RCC_APB1RSTR_TIM5RST_BIT)
-#define RCC_APB1RSTR_TIM4RST (1U << RCC_APB1RSTR_TIM4RST_BIT)
-#define RCC_APB1RSTR_TIM3RST (1U << RCC_APB1RSTR_TIM3RST_BIT)
-#define RCC_APB1RSTR_TIM2RST (1U << RCC_APB1RSTR_TIM2RST_BIT)
-
-/* APB2 peripheral reset register */
-
-#define RCC_APB2RSTR_TIM11RST_BIT 18
-#define RCC_APB2RSTR_TIM10RST_BIT 17
-#define RCC_APB2RSTR_TIM9RST_BIT 16
-#define RCC_APB2RSTR_SYSCFGRST_BIT 14
-#define RCC_APB2RSTR_SPI1RST_BIT 12
-#define RCC_APB2RSTR_SDIORST_BIT 11
-#define RCC_APB2RSTR_ADCRST_BIT 8
-#define RCC_APB2RSTR_USART6RST_BIT 5
-#define RCC_APB2RSTR_USART1RST_BIT 4
-#define RCC_APB2RSTR_TIM8RST_BIT 1
-#define RCC_APB2RSTR_TIM1RST_BIT 0
-
-#define RCC_APB2RSTR_TIM11RST (1U << RCC_APB2RSTR_TIM11RST_BIT)
-#define RCC_APB2RSTR_TIM10RST (1U << RCC_APB2RSTR_TIM10RST_BIT)
-#define RCC_APB2RSTR_TIM9RST (1U << RCC_APB2RSTR_TIM9RST_BIT)
-#define RCC_APB2RSTR_SYSCFGRST (1U << RCC_APB2RSTR_SYSCFGRST_BIT)
-#define RCC_APB2RSTR_SPI1RST (1U << RCC_APB2RSTR_SPI1RST_BIT)
-#define RCC_APB2RSTR_SDIORST (1U << RCC_APB2RSTR_SDIORST_BIT)
-#define RCC_APB2RSTR_ADCRST (1U << RCC_APB2RSTR_ADCRST_BIT)
-#define RCC_APB2RSTR_USART6RST (1U << RCC_APB2RSTR_USART6RST_BIT)
-#define RCC_APB2RSTR_USART1RST (1U << RCC_APB2RSTR_USART1RST_BIT)
-#define RCC_APB2RSTR_TIM8RST (1U << RCC_APB2RSTR_TIM8RST_BIT)
-#define RCC_APB2RSTR_TIM1RST (1U << RCC_APB2RSTR_TIM1RST_BIT)
-
-/* AHB1 peripheral clock enable register */
-
-#define RCC_AHB1ENR_OTGHSULPIEN_BIT 30
-#define RCC_AHB1ENR_OTGHSEN_BIT 29
-#define RCC_AHB1ENR_ETHMACPTPEN_BIT 28
-#define RCC_AHB1ENR_ETHMACRXEN_BIT 27
-#define RCC_AHB1ENR_ETHMACTXEN_BIT 26
-#define RCC_AHB1ENR_ETHMACEN_BIT 25
-#define RCC_AHB1ENR_DMA2EN_BIT 22
-#define RCC_AHB1ENR_DMA1EN_BIT 21
-#define RCC_AHB1ENR_BKPSRAMEN_BIT 18
-#define RCC_AHB1ENR_CRCEN_BIT 12
-#define RCC_AHB1ENR_GPIOIEN_BIT 8
-#define RCC_AHB1ENR_GPIOHEN_BIT 7
-#define RCC_AHB1ENR_GPIOGEN_BIT 6
-#define RCC_AHB1ENR_GPIOFEN_BIT 5
-#define RCC_AHB1ENR_GPIOEEN_BIT 4
-#define RCC_AHB1ENR_GPIODEN_BIT 3
-#define RCC_AHB1ENR_GPIOCEN_BIT 2
-#define RCC_AHB1ENR_GPIOBEN_BIT 1
-#define RCC_AHB1ENR_GPIOAEN_BIT 0
-
-#define RCC_AHB1ENR_OTGHSULPIEN (1U << RCC_AHB1ENR_OTGHSULPIEN_BIT)
-#define RCC_AHB1ENR_OTGHSEN (1U << RCC_AHB1ENR_OTGHSEN_BIT)
-#define RCC_AHB1ENR_ETHMACPTPEN (1U << RCC_AHB1ENR_ETHMACPTPEN_BIT)
-#define RCC_AHB1ENR_ETHMACRXEN (1U << RCC_AHB1ENR_ETHMACRXEN_BIT)
-#define RCC_AHB1ENR_ETHMACTXEN (1U << RCC_AHB1ENR_ETHMACTXEN_BIT)
-#define RCC_AHB1ENR_ETHMACEN (1U << RCC_AHB1ENR_ETHMACEN_BIT)
-#define RCC_AHB1ENR_DMA2EN (1U << RCC_AHB1ENR_DMA2EN_BIT)
-#define RCC_AHB1ENR_DMA1EN (1U << RCC_AHB1ENR_DMA1EN_BIT)
-#define RCC_AHB1ENR_BKPSRAMEN (1U << RCC_AHB1ENR_BKPSRAMEN_BIT)
-#define RCC_AHB1ENR_CRCEN (1U << RCC_AHB1ENR_CRCEN_BIT)
-#define RCC_AHB1ENR_GPIOIEN (1U << RCC_AHB1ENR_GPIOIEN_BIT)
-#define RCC_AHB1ENR_GPIOHEN (1U << RCC_AHB1ENR_GPIOHEN_BIT)
-#define RCC_AHB1ENR_GPIOGEN (1U << RCC_AHB1ENR_GPIOGEN_BIT)
-#define RCC_AHB1ENR_GPIOFEN (1U << RCC_AHB1ENR_GPIOFEN_BIT)
-#define RCC_AHB1ENR_GPIOEEN (1U << RCC_AHB1ENR_GPIOEEN_BIT)
-#define RCC_AHB1ENR_GPIODEN (1U << RCC_AHB1ENR_GPIODEN_BIT)
-#define RCC_AHB1ENR_GPIOCEN (1U << RCC_AHB1ENR_GPIOCEN_BIT)
-#define RCC_AHB1ENR_GPIOBEN (1U << RCC_AHB1ENR_GPIOBEN_BIT)
-#define RCC_AHB1ENR_GPIOAEN (1U << RCC_AHB1ENR_GPIOAEN_BIT)
-
-/* AHB2 peripheral clock enable register */
-
-#define RCC_AHB2ENR_OTGFSEN_BIT 7
-#define RCC_AHB2ENR_RNGEN_BIT 6
-#define RCC_AHB2ENR_HASHEN_BIT 5
-#define RCC_AHB2ENR_CRYPEN_BIT 4
-#define RCC_AHB2ENR_DCMIEN_BIT 0
-
-#define RCC_AHB2ENR_OTGFSEN (1U << RCC_AHB2ENR_OTGFSEN_BIT)
-#define RCC_AHB2ENR_RNGEN (1U << RCC_AHB2ENR_RNGEN_BIT)
-#define RCC_AHB2ENR_HASHEN (1U << RCC_AHB2ENR_HASHEN_BIT)
-#define RCC_AHB2ENR_CRYPEN (1U << RCC_AHB2ENR_CRYPEN_BIT)
-#define RCC_AHB2ENR_DCMIEN (1U << RCC_AHB2ENR_DCMIEN_BIT)
-
-/* AHB3 peripheral clock enable register */
-
-#define RCC_AHB3ENR_FSMCEN_BIT 0
-
-#define RCC_AHB3ENR_FSMCEN (1U << RCC_AHB3ENR_FSMCEN_BIT)
-
-/* APB1 peripheral clock enable register */
-
-#define RCC_APB1ENR_DACEN_BIT 29
-#define RCC_APB1ENR_PWREN_BIT 28
-#define RCC_APB1ENR_CAN2EN_BIT 26
-#define RCC_APB1ENR_CAN1EN_BIT 25
-#define RCC_APB1ENR_I2C3EN_BIT 23
-#define RCC_APB1ENR_I2C2EN_BIT 22
-#define RCC_APB1ENR_I2C1EN_BIT 21
-#define RCC_APB1ENR_UART5EN_BIT 20
-#define RCC_APB1ENR_UART4EN_BIT 19
-#define RCC_APB1ENR_USART3EN_BIT 18
-#define RCC_APB1ENR_USART2EN_BIT 17
-#define RCC_APB1ENR_SPI3EN_BIT 15
-#define RCC_APB1ENR_SPI2EN_BIT 14
-#define RCC_APB1ENR_WWDGEN_BIT 11
-#define RCC_APB1ENR_TIM14EN_BIT 8
-#define RCC_APB1ENR_TIM13EN_BIT 7
-#define RCC_APB1ENR_TIM12EN_BIT 6
-#define RCC_APB1ENR_TIM7EN_BIT 5
-#define RCC_APB1ENR_TIM6EN_BIT 4
-#define RCC_APB1ENR_TIM5EN_BIT 3
-#define RCC_APB1ENR_TIM4EN_BIT 2
-#define RCC_APB1ENR_TIM3EN_BIT 1
-#define RCC_APB1ENR_TIM2EN_BIT 0
-
-#define RCC_APB1ENR_DACEN (1U << RCC_APB1ENR_DACEN_BIT)
-#define RCC_APB1ENR_PWREN (1U << RCC_APB1ENR_PWREN_BIT)
-#define RCC_APB1ENR_CAN2EN (1U << RCC_APB1ENR_CAN2EN_BIT)
-#define RCC_APB1ENR_CAN1EN (1U << RCC_APB1ENR_CAN1EN_BIT)
-#define RCC_APB1ENR_I2C3EN (1U << RCC_APB1ENR_I2C3EN_BIT)
-#define RCC_APB1ENR_I2C2EN (1U << RCC_APB1ENR_I2C2EN_BIT)
-#define RCC_APB1ENR_I2C1EN (1U << RCC_APB1ENR_I2C1EN_BIT)
-#define RCC_APB1ENR_UART5EN (1U << RCC_APB1ENR_UART5EN_BIT)
-#define RCC_APB1ENR_UART4EN (1U << RCC_APB1ENR_UART4EN_BIT)
-#define RCC_APB1ENR_USART3EN (1U << RCC_APB1ENR_USART3EN_BIT)
-#define RCC_APB1ENR_USART2EN (1U << RCC_APB1ENR_USART2EN_BIT)
-#define RCC_APB1ENR_SPI3EN (1U << RCC_APB1ENR_SPI3EN_BIT)
-#define RCC_APB1ENR_SPI2EN (1U << RCC_APB1ENR_SPI2EN_BIT)
-#define RCC_APB1ENR_WWDGEN (1U << RCC_APB1ENR_WWDGEN_BIT)
-#define RCC_APB1ENR_TIM14EN (1U << RCC_APB1ENR_TIM14EN_BIT)
-#define RCC_APB1ENR_TIM13EN (1U << RCC_APB1ENR_TIM13EN_BIT)
-#define RCC_APB1ENR_TIM12EN (1U << RCC_APB1ENR_TIM12EN_BIT)
-#define RCC_APB1ENR_TIM7EN (1U << RCC_APB1ENR_TIM7EN_BIT)
-#define RCC_APB1ENR_TIM6EN (1U << RCC_APB1ENR_TIM6EN_BIT)
-#define RCC_APB1ENR_TIM5EN (1U << RCC_APB1ENR_TIM5EN_BIT)
-#define RCC_APB1ENR_TIM4EN (1U << RCC_APB1ENR_TIM4EN_BIT)
-#define RCC_APB1ENR_TIM3EN (1U << RCC_APB1ENR_TIM3EN_BIT)
-#define RCC_APB1ENR_TIM2EN (1U << RCC_APB1ENR_TIM2EN_BIT)
-
-/* APB2 peripheral clock enable register */
-
-#define RCC_APB2ENR_TIM11EN_BIT 18
-#define RCC_APB2ENR_TIM10EN_BIT 17
-#define RCC_APB2ENR_TIM9EN_BIT 16
-#define RCC_APB2ENR_SYSCFGEN_BIT 14
-#define RCC_APB2ENR_SPI1EN_BIT 12
-#define RCC_APB2ENR_SDIOEN_BIT 11
-#define RCC_APB2ENR_ADC3EN_BIT 10
-#define RCC_APB2ENR_ADC2EN_BIT 9
-#define RCC_APB2ENR_ADC1EN_BIT 8
-#define RCC_APB2ENR_USART6EN_BIT 5
-#define RCC_APB2ENR_USART1EN_BIT 4
-#define RCC_APB2ENR_TIM8EN_BIT 1
-#define RCC_APB2ENR_TIM1EN_BIT 0
-
-#define RCC_APB2ENR_TIM11EN (1U << RCC_APB2ENR_TIM11EN_BIT)
-#define RCC_APB2ENR_TIM10EN (1U << RCC_APB2ENR_TIM10EN_BIT)
-#define RCC_APB2ENR_TIM9EN (1U << RCC_APB2ENR_TIM9EN_BIT)
-#define RCC_APB2ENR_SYSCFGEN (1U << RCC_APB2ENR_SYSCFGEN_BIT)
-#define RCC_APB2ENR_SPI1EN (1U << RCC_APB2ENR_SPI1EN_BIT)
-#define RCC_APB2ENR_SDIOEN (1U << RCC_APB2ENR_SDIOEN_BIT)
-#define RCC_APB2ENR_ADC3EN (1U << RCC_APB2ENR_ADC3EN_BIT)
-#define RCC_APB2ENR_ADC2EN (1U << RCC_APB2ENR_ADC2EN_BIT)
-#define RCC_APB2ENR_ADC1EN (1U << RCC_APB2ENR_ADC1EN_BIT)
-#define RCC_APB2ENR_USART6EN (1U << RCC_APB2ENR_USART6EN_BIT)
-#define RCC_APB2ENR_USART1EN (1U << RCC_APB2ENR_USART1EN_BIT)
-#define RCC_APB2ENR_TIM8EN (1U << RCC_APB2ENR_TIM8EN_BIT)
-#define RCC_APB2ENR_TIM1EN (1U << RCC_APB2ENR_TIM1EN_BIT)
-
-/* AHB1 peripheral clock enable in low power mode register */
-
-#define RCC_AHB1LPENR_OTGHSULPILPEN_BIT 30
-#define RCC_AHB1LPENR_OTGHSLPEN_BIT 29
-#define RCC_AHB1LPENR_ETHMACPTPLPEN_BIT 28
-#define RCC_AHB1LPENR_ETHMACRXLPEN_BIT 27
-#define RCC_AHB1LPENR_ETHMACTXLPEN_BIT 26
-#define RCC_AHB1LPENR_ETHMACLPEN_BIT 25
-#define RCC_AHB1LPENR_DMA2LPEN_BIT 22
-#define RCC_AHB1LPENR_DMA1LPEN_BIT 21
-#define RCC_AHB1LPENR_BKPSRAMLPEN_BIT 18
-#define RCC_AHB1LPENR_SRAM2LPEN_BIT 17
-#define RCC_AHB1LPENR_SRAM1LPEN_BIT 16
-#define RCC_AHB1LPENR_FLITFLPEN_BIT 15
-#define RCC_AHB1LPENR_CRCLPEN_BIT 12
-#define RCC_AHB1LPENR_GPIOILPEN_BIT 8
-#define RCC_AHB1LPENR_GPIOGLPEN_BIT 6
-#define RCC_AHB1LPENR_GPIOFLPEN_BIT 5
-#define RCC_AHB1LPENR_GPIOELPEN_BIT 4
-#define RCC_AHB1LPENR_GPIODLPEN_BIT 3
-#define RCC_AHB1LPENR_GPIOCLPEN_BIT 2
-#define RCC_AHB1LPENR_GPIOBLPEN_BIT 1
-#define RCC_AHB1LPENR_GPIOALPEN_BIT 0
-
-#define RCC_AHB1LPENR_OTGHSULPILPEN (1U << RCC_AHB1LPENR_OTGHSULPILPEN_BIT)
-#define RCC_AHB1LPENR_OTGHSLPEN (1U << RCC_AHB1LPENR_OTGHSLPEN_BIT)
-#define RCC_AHB1LPENR_ETHMACPTPLPEN (1U << RCC_AHB1LPENR_ETHMACPTPLPEN_BIT)
-#define RCC_AHB1LPENR_ETHMACRXLPEN (1U << RCC_AHB1LPENR_ETHMACRXLPEN_BIT)
-#define RCC_AHB1LPENR_ETHMACTXLPEN (1U << RCC_AHB1LPENR_ETHMACTXLPEN_BIT)
-#define RCC_AHB1LPENR_ETHMACLPEN (1U << RCC_AHB1LPENR_ETHMACLPEN_BIT)
-#define RCC_AHB1LPENR_DMA2LPEN (1U << RCC_AHB1LPENR_DMA2LPEN_BIT)
-#define RCC_AHB1LPENR_DMA1LPEN (1U << RCC_AHB1LPENR_DMA1LPEN_BIT)
-#define RCC_AHB1LPENR_BKPSRAMLPEN (1U << RCC_AHB1LPENR_BKPSRAMLPEN_BIT)
-#define RCC_AHB1LPENR_SRAM2LPEN (1U << RCC_AHB1LPENR_SRAM2LPEN_BIT)
-#define RCC_AHB1LPENR_SRAM1LPEN (1U << RCC_AHB1LPENR_SRAM1LPEN_BIT)
-#define RCC_AHB1LPENR_FLITFLPEN (1U << RCC_AHB1LPENR_FLITFLPEN_BIT)
-#define RCC_AHB1LPENR_CRCLPEN (1U << RCC_AHB1LPENR_CRCLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOILPEN (1U << RCC_AHB1LPENR_GPIOILPEN_BIT)
-#define RCC_AHB1LPENR_GPIOGLPEN (1U << RCC_AHB1LPENR_GPIOGLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOFLPEN (1U << RCC_AHB1LPENR_GPIOFLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOELPEN (1U << RCC_AHB1LPENR_GPIOELPEN_BIT)
-#define RCC_AHB1LPENR_GPIODLPEN (1U << RCC_AHB1LPENR_GPIODLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOCLPEN (1U << RCC_AHB1LPENR_GPIOCLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOBLPEN (1U << RCC_AHB1LPENR_GPIOBLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOALPEN (1U << RCC_AHB1LPENR_GPIOALPEN_BIT)
-
-/* AHB2 peripheral clock enable in low power mode register */
-
-#define RCC_AHB2LPENR_OTGFSLPEN_BIT 7
-#define RCC_AHB2LPENR_RNGLPEN_BIT 6
-#define RCC_AHB2LPENR_HASHLPEN_BIT 5
-#define RCC_AHB2LPENR_CRYPLPEN_BIT 4
-#define RCC_AHB2LPENR_DCMILPEN_BIT 0
-
-#define RCC_AHB2LPENR_OTGFSLPEN (1U << RCC_AHB2LPENR_OTGFSLPEN_BIT)
-#define RCC_AHB2LPENR_RNGLPEN (1U << RCC_AHB2LPENR_RNGLPEN_BIT)
-#define RCC_AHB2LPENR_HASHLPEN (1U << RCC_AHB2LPENR_HASHLPEN_BIT)
-#define RCC_AHB2LPENR_CRYPLPEN (1U << RCC_AHB2LPENR_CRYPLPEN_BIT)
-#define RCC_AHB2LPENR_DCMILPEN (1U << RCC_AHB2LPENR_DCMILPEN_BIT)
-
-/* AHB3 peripheral clock enable in low power mode register */
-
-#define RCC_AHB3LPENR_FSMCLPEN_BIT 0
-
-#define RCC_AHB3LPENR_FSMCLPEN (1U << RCC_AHB3LPENR_FSMCLPEN_BIT)
-
-/* APB1 peripheral clock enable in low power mode register */
-
-#define RCC_APB1LPENR_DACLPEN_BIT 29
-#define RCC_APB1LPENR_PWRLPEN_BIT 28
-#define RCC_APB1LPENR_CAN2LPEN_BIT 26
-#define RCC_APB1LPENR_CAN1LPEN_BIT 25
-#define RCC_APB1LPENR_I2C3LPEN_BIT 23
-#define RCC_APB1LPENR_I2C2LPEN_BIT 22
-#define RCC_APB1LPENR_I2C1LPEN_BIT 21
-#define RCC_APB1LPENR_UART5LPEN_BIT 20
-#define RCC_APB1LPENR_UART4LPEN_BIT 19
-#define RCC_APB1LPENR_USART3LPEN_BIT 18
-#define RCC_APB1LPENR_USART2LPEN_BIT 17
-#define RCC_APB1LPENR_SPI3LPEN_BIT 15
-#define RCC_APB1LPENR_SPI2LPEN_BIT 14
-#define RCC_APB1LPENR_WWDGLPEN_BIT 11
-#define RCC_APB1LPENR_TIM14LPEN_BIT 8
-#define RCC_APB1LPENR_TIM13LPEN_BIT 7
-#define RCC_APB1LPENR_TIM12LPEN_BIT 6
-#define RCC_APB1LPENR_TIM7LPEN_BIT 5
-#define RCC_APB1LPENR_TIM6LPEN_BIT 4
-#define RCC_APB1LPENR_TIM5LPEN_BIT 3
-#define RCC_APB1LPENR_TIM4LPEN_BIT 2
-#define RCC_APB1LPENR_TIM3LPEN_BIT 1
-#define RCC_APB1LPENR_TIM2LPEN_BIT 0
-
-#define RCC_APB1LPENR_DACLPEN (1U << RCC_APB1LPENR_DACLPEN_BIT)
-#define RCC_APB1LPENR_PWRLPEN (1U << RCC_APB1LPENR_PWRLPEN_BIT)
-#define RCC_APB1LPENR_CAN2LPEN (1U << RCC_APB1LPENR_CAN2LPEN_BIT)
-#define RCC_APB1LPENR_CAN1LPEN (1U << RCC_APB1LPENR_CAN1LPEN_BIT)
-#define RCC_APB1LPENR_I2C3LPEN (1U << RCC_APB1LPENR_I2C3LPEN_BIT)
-#define RCC_APB1LPENR_I2C2LPEN (1U << RCC_APB1LPENR_I2C2LPEN_BIT)
-#define RCC_APB1LPENR_I2C1LPEN (1U << RCC_APB1LPENR_I2C1LPEN_BIT)
-#define RCC_APB1LPENR_UART5LPEN (1U << RCC_APB1LPENR_UART5LPEN_BIT)
-#define RCC_APB1LPENR_UART4LPEN (1U << RCC_APB1LPENR_UART4LPEN_BIT)
-#define RCC_APB1LPENR_USART3LPEN (1U << RCC_APB1LPENR_USART3LPEN_BIT)
-#define RCC_APB1LPENR_USART2LPEN (1U << RCC_APB1LPENR_USART2LPEN_BIT)
-#define RCC_APB1LPENR_SPI3LPEN (1U << RCC_APB1LPENR_SPI3LPEN_BIT)
-#define RCC_APB1LPENR_SPI2LPEN (1U << RCC_APB1LPENR_SPI2LPEN_BIT)
-#define RCC_APB1LPENR_WWDGLPEN (1U << RCC_APB1LPENR_WWDGLPEN_BIT)
-#define RCC_APB1LPENR_TIM14LPEN (1U << RCC_APB1LPENR_TIM14LPEN_BIT)
-#define RCC_APB1LPENR_TIM13LPEN (1U << RCC_APB1LPENR_TIM13LPEN_BIT)
-#define RCC_APB1LPENR_TIM12LPEN (1U << RCC_APB1LPENR_TIM12LPEN_BIT)
-#define RCC_APB1LPENR_TIM7LPEN (1U << RCC_APB1LPENR_TIM7LPEN_BIT)
-#define RCC_APB1LPENR_TIM6LPEN (1U << RCC_APB1LPENR_TIM6LPEN_BIT)
-#define RCC_APB1LPENR_TIM5LPEN (1U << RCC_APB1LPENR_TIM5LPEN_BIT)
-#define RCC_APB1LPENR_TIM4LPEN (1U << RCC_APB1LPENR_TIM4LPEN_BIT)
-#define RCC_APB1LPENR_TIM3LPEN (1U << RCC_APB1LPENR_TIM3LPEN_BIT)
-#define RCC_APB1LPENR_TIM2LPEN (1U << RCC_APB1LPENR_TIM2LPEN_BIT)
-
-/* APB2 peripheral clock enable in low power mode register */
-
-#define RCC_APB2LPENR_TIM11LPEN_BIT 18
-#define RCC_APB2LPENR_TIM10LPEN_BIT 17
-#define RCC_APB2LPENR_TIM9LPEN_BIT 16
-#define RCC_APB2LPENR_SYSCFGLPEN_BIT 14
-#define RCC_APB2LPENR_SPI1LPEN_BIT 12
-#define RCC_APB2LPENR_SDIOLPEN_BIT 11
-#define RCC_APB2LPENR_ADC3LPEN_BIT 10
-#define RCC_APB2LPENR_ADC2LPEN_BIT 9
-#define RCC_APB2LPENR_ADC1LPEN_BIT 8
-#define RCC_APB2LPENR_USART6LPEN_BIT 5
-#define RCC_APB2LPENR_USART1LPEN_BIT 4
-#define RCC_APB2LPENR_TIM8LPEN_BIT 1
-#define RCC_APB2LPENR_TIM1LPEN_BIT 0
-
-#define RCC_APB2LPENR_TIM11LPEN (1U << RCC_APB2LPENR_TIM11LPEN_BIT)
-#define RCC_APB2LPENR_TIM10LPEN (1U << RCC_APB2LPENR_TIM10LPEN_BIT)
-#define RCC_APB2LPENR_TIM9LPEN (1U << RCC_APB2LPENR_TIM9LPEN_BIT)
-#define RCC_APB2LPENR_SYSCFGLPEN (1U << RCC_APB2LPENR_SYSCFGLPEN_BIT)
-#define RCC_APB2LPENR_SPI1LPEN (1U << RCC_APB2LPENR_SPI1LPEN_BIT)
-#define RCC_APB2LPENR_SDIOLPEN (1U << RCC_APB2LPENR_SDIOLPEN_BIT)
-#define RCC_APB2LPENR_ADC3LPEN (1U << RCC_APB2LPENR_ADC3LPEN_BIT)
-#define RCC_APB2LPENR_ADC2LPEN (1U << RCC_APB2LPENR_ADC2LPEN_BIT)
-#define RCC_APB2LPENR_ADC1LPEN (1U << RCC_APB2LPENR_ADC1LPEN_BIT)
-#define RCC_APB2LPENR_USART6LPEN (1U << RCC_APB2LPENR_USART6LPEN_BIT)
-#define RCC_APB2LPENR_USART1LPEN (1U << RCC_APB2LPENR_USART1LPEN_BIT)
-#define RCC_APB2LPENR_TIM8LPEN (1U << RCC_APB2LPENR_TIM8LPEN_BIT)
-#define RCC_APB2LPENR_TIM1LPEN (1U << RCC_APB2LPENR_TIM1LPEN_BIT)
-
-/* Backup domain control register */
-
-#define RCC_BDCR_BDRST_BIT 16
-#define RCC_BDCR_RTCEN_BIT 15
-#define RCC_BDCR_LSEBYP_BIT 2
-#define RCC_BDCR_LSERDY_BIT 1
-#define RCC_BDCR_LSEON_BIT 0
-
-#define RCC_BDCR_BDRST (1U << RCC_BDCR_BDRST_BIT)
-#define RCC_BDCR_RTCEN (1U << RCC_BDCR_RTCEN_BIT)
-#define RCC_BDCR_RTCSEL (0x3 << 8)
-#define RCC_BDCR_RTCSEL_NOCLOCK (0x0 << 8)
-#define RCC_BDCR_RTCSEL_LSE (0x1 << 8)
-#define RCC_BDCR_RTCSEL_LSI (0x2 << 8)
-#define RCC_BDCR_RTCSEL_HSE_DIV (0x3 << 8)
-#define RCC_BDCR_LSEBYP (1U << RCC_BDCR_LSEBYP_BIT)
-#define RCC_BDCR_LSERDY (1U << RCC_BDCR_LSERDY_BIT)
-#define RCC_BDCR_LSEON (1U << RCC_BDCR_LSEON_BIT)
-
-/* Clock control and status register */
-
-#define RCC_CSR_LPWRRSTF_BIT 31
-#define RCC_CSR_WWDGRSTF_BIT 30
-#define RCC_CSR_IWDGRSTF_BIT 29
-#define RCC_CSR_SFTRSTF_BIT 28
-#define RCC_CSR_PORRSTF_BIT 27
-#define RCC_CSR_PINRSTF_BIT 26
-#define RCC_CSR_BORRSTF_BIT 25
-#define RCC_CSR_RMVF_BIT 24
-#define RCC_CSR_LSIRDY_BIT 1
-#define RCC_CSR_LSION_BIT 0
-
-#define RCC_CSR_LPWRRSTF (1U << RCC_CSR_LPWRRSTF_BIT)
-#define RCC_CSR_WWDGRSTF (1U << RCC_CSR_WWDGRSTF_BIT)
-#define RCC_CSR_IWDGRSTF (1U << RCC_CSR_IWDGRSTF_BIT)
-#define RCC_CSR_SFTRSTF (1U << RCC_CSR_SFTRSTF_BIT)
-#define RCC_CSR_PORRSTF (1U << RCC_CSR_PORRSTF_BIT)
-#define RCC_CSR_PINRSTF (1U << RCC_CSR_PINRSTF_BIT)
-#define RCC_CSR_BORRSTF (1U << RCC_CSR_BORRSTF_BIT)
-#define RCC_CSR_RMVF (1U << RCC_CSR_RMVF_BIT)
-#define RCC_CSR_LSIRDY (1U << RCC_CSR_LSIRDY_BIT)
-#define RCC_CSR_LSION (1U << RCC_CSR_LSION_BIT)
-
-/* Spread spectrum clock generation register */
-
-#define RCC_SSCGR_SSCGEN_BIT 31
-#define RCC_SSCGR_SPREADSEL_BIT 30
-
-#define RCC_SSCGR_SSCGEN (1U << RCC_SSCGR_SSCGEN_BIT)
-#define RCC_SSCGR_SPREADSEL (1U << RCC_SSCGR_SPREADSEL_BIT)
-#define RCC_SSCGR_SPREADSEL_CENTER (0x0 << RCC_SSCGR_SPREADSEL_BIT)
-#define RCC_SSCGR_SPREADSEL_DOWN (0x1 << RCC_SSCGR_SPREADSEL_BIT)
-#define RCC_SSCGR_INCSTEP (0xFFF << 16)
-#define RCC_SSCGR_MODPER 0xFFFF
-
-/* PLLI2S configuration register */
-
-#define RCC_PLLI2SCFGR_PLLI2SR (0x7 << 28)
-#define RCC_PLLI2SCFGR_PLLI2SN (0x1FF << 6)
-
-/*
- * Clock sources, domains, and peripheral clock IDs.
- */
-
-/**
- * @brief STM32F2 clock sources.
- */
-typedef enum rcc_clk {
- RCC_CLK_PLLI2S = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
- RCC_CR_PLLI2SON_BIT), /**< Dedicated PLL
- for I2S. */
- RCC_CLK_PLL = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
- RCC_CR_PLLON_BIT), /**< Main PLL, clocked by
- HSI or HSE. */
- RCC_CLK_HSE = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
- RCC_CR_HSEON_BIT), /**< High speed external. */
- RCC_CLK_HSI = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
- RCC_CR_HSION_BIT), /**< High speed internal. */
- RCC_CLK_LSE = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) |
- RCC_BDCR_LSEON_BIT), /**< Low-speed external
- * (32.768 KHz). */
- RCC_CLK_LSI = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) |
- RCC_CSR_LSION_BIT), /**< Low-speed internal
- * (approximately 32 KHz). */
-} rcc_clk;
-
-/**
- * @brief STM32F2 rcc_clk_id.
- */
-typedef enum rcc_clk_id {
- RCC_ADC1,
- RCC_ADC2,
- RCC_ADC3,
- RCC_BKPSRAM,
- RCC_CAN1,
- RCC_CAN2,
- RCC_CRC,
- RCC_CRYP,
- RCC_DAC,
- RCC_DCMI,
- RCC_DMA1,
- RCC_DMA2,
- RCC_ETHMAC,
- RCC_ETHMACPTP,
- RCC_ETHMACRX,
- RCC_ETHMACTX,
- RCC_FSMC,
- RCC_GPIOA,
- RCC_GPIOB,
- RCC_GPIOC,
- RCC_GPIOD,
- RCC_GPIOE,
- RCC_GPIOF,
- RCC_GPIOG,
- RCC_GPIOH,
- RCC_GPIOI,
- RCC_HASH,
- RCC_I2C1,
- RCC_I2C2,
- RCC_I2C3,
- RCC_OTGFS,
- RCC_OTGHS,
- RCC_OTGHSULPI,
- RCC_PWR,
- RCC_RNG,
- RCC_SDIO,
- RCC_SPI1,
- RCC_SPI2,
- RCC_SPI3,
- RCC_SYSCFG,
- RCC_TIMER1,
- RCC_TIMER10,
- RCC_TIMER11,
- RCC_TIMER12,
- RCC_TIMER13,
- RCC_TIMER14,
- RCC_TIMER2,
- RCC_TIMER3,
- RCC_TIMER4,
- RCC_TIMER5,
- RCC_TIMER6,
- RCC_TIMER7,
- RCC_TIMER8,
- RCC_TIMER9,
- RCC_USART1,
- RCC_USART2,
- RCC_USART3,
- RCC_UART4,
- RCC_UART5,
- RCC_USART6,
- RCC_WWDG,
-} rcc_clk_id;
-
-/**
- * @brief STM32F2 PLL entry clock source
- * @see rcc_configure_pll()
- */
-typedef enum rcc_pllsrc {
- RCC_PLLSRC_HSI = 0,
- RCC_PLLSRC_HSE = RCC_PLLCFGR_PLLSRC,
-} rcc_pllsrc;
-
-/**
- * @brief STM32F2 Peripheral clock domains.
- */
-typedef enum rcc_clk_domain {
- RCC_APB1,
- RCC_APB2,
- RCC_AHB1,
- RCC_AHB2,
- RCC_AHB3,
-} rcc_clk_domain;
-
-/*
- * Prescalers and dividers.
- */
-
-/**
- * @brief STM32F2 Prescaler identifiers.
- */
-typedef enum rcc_prescaler {
- RCC_PRESCALER_MCO2,
- RCC_PRESCALER_MCO1,
- RCC_PRESCALER_RTC,
- RCC_PRESCALER_APB2,
- RCC_PRESCALER_APB1,
- RCC_PRESCALER_AHB
-} rcc_prescaler;
-
-/**
- * @brief STM32F2 MCO2 prescaler dividers.
- */
-typedef enum rcc_mco2_divider {
- RCC_MCO2_DIV_1 = RCC_CFGR_MCO2PRE_DIV_1,
- RCC_MCO2_DIV_2 = RCC_CFGR_MCO2PRE_DIV_2,
- RCC_MCO2_DIV_3 = RCC_CFGR_MCO2PRE_DIV_3,
- RCC_MCO2_DIV_4 = RCC_CFGR_MCO2PRE_DIV_4,
- RCC_MCO2_DIV_5 = RCC_CFGR_MCO2PRE_DIV_5,
-} rcc_mco2_divider;
-
-/**
- * @brief STM32F2 MCO1 prescaler dividers.
- */
-typedef enum rcc_mco1_divider {
- RCC_MCO1_DIV_1 = RCC_CFGR_MCO1PRE_DIV_1,
- RCC_MCO1_DIV_2 = RCC_CFGR_MCO1PRE_DIV_2,
- RCC_MCO1_DIV_3 = RCC_CFGR_MCO1PRE_DIV_3,
- RCC_MCO1_DIV_4 = RCC_CFGR_MCO1PRE_DIV_4,
- RCC_MCO1_DIV_5 = RCC_CFGR_MCO1PRE_DIV_5,
-} rcc_mco1_divider;
-
-/**
- * @brief STM32F2 RTC prescaler dividers.
- */
-typedef enum rcc_rtc_divider { /* FIXME [0.0.13] TODO */
- RCC_RTC_DIV_TODO = 0xFFFFFFFF,
-} rcc_rtc_divider;
-
-/**
- * @brief STM32F2 AP2 prescaler dividers.
- */
-typedef enum rcc_apb2_divider {
- RCC_APB2_HCLK_DIV_1 = 0,
- RCC_APB2_HCLK_DIV_2 = RCC_CFGR_PPRE2_AHB_DIV_2,
- RCC_APB2_HCLK_DIV_4 = RCC_CFGR_PPRE2_AHB_DIV_4,
- RCC_APB2_HCLK_DIV_8 = RCC_CFGR_PPRE2_AHB_DIV_8,
- RCC_APB2_HCLK_DIV_16 = RCC_CFGR_PPRE2_AHB_DIV_16,
-} rcc_apb2_divider;
-
-/**
- * @brief STM32F2 APB1 prescaler dividers.
- */
-typedef enum rcc_apb1_divider {
- RCC_APB1_HCLK_DIV_1 = 0,
- RCC_APB1_HCLK_DIV_2 = RCC_CFGR_PPRE1_AHB_DIV_2,
- RCC_APB1_HCLK_DIV_4 = RCC_CFGR_PPRE1_AHB_DIV_4,
- RCC_APB1_HCLK_DIV_8 = RCC_CFGR_PPRE1_AHB_DIV_8,
- RCC_APB1_HCLK_DIV_16 = RCC_CFGR_PPRE1_AHB_DIV_16,
-} rcc_apb1_divider;
-
-/**
- * @brief STM32F2 AHB prescaler dividers.
- */
-typedef enum rcc_ahb_divider {
- RCC_AHB_SYSCLK_DIV_1 = 0,
- RCC_AHB_SYSCLK_DIV_2 = RCC_CFGR_HPRE_SYSCLK_DIV_2,
- RCC_AHB_SYSCLK_DIV_4 = RCC_CFGR_HPRE_SYSCLK_DIV_4,
- RCC_AHB_SYSCLK_DIV_8 = RCC_CFGR_HPRE_SYSCLK_DIV_8,
- RCC_AHB_SYSCLK_DIV_16 = RCC_CFGR_HPRE_SYSCLK_DIV_16,
- RCC_AHB_SYSCLK_DIV_64 = RCC_CFGR_HPRE_SYSCLK_DIV_64,
- RCC_AHB_SYSCLK_DIV_128 = RCC_CFGR_HPRE_SYSCLK_DIV_128,
- RCC_AHB_SYSCLK_DIV_256 = RCC_CFGR_HPRE_SYSCLK_DIV_256,
- RCC_AHB_SYSCLK_DIV_512 = RCC_CFGR_HPRE_SYSCLK_DIV_512,
-} rcc_ahb_divider;
-
-/**
- * @brief STM32F2 PLL configuration values.
- * Point to one of these with the "data" field in a struct rcc_pll_cfg.
- * @see struct rcc_pll_cfg.
- */
-typedef struct stm32f2_rcc_pll_data {
- uint8 pllq; /**<
- * @brief PLLQ value.
- * Allowed values: 4, 5, ..., 15. */
- uint8 pllp; /**<
- * @brief PLLP value.
- * Allowed values: 2, 4, 6, 8. */
- uint16 plln; /**<
- * @brief PLLN value.
- * Allowed values: 192, 193, ..., 432. */
- uint8 pllm; /**<
- * @brief PLLM value.
- * Allowed values: 2, 3, ..., 63. */
-} stm32f2_rcc_pll_data;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/libmaple/stm32f2/include/series/spi.h b/libmaple/stm32f2/include/series/spi.h
deleted file mode 100644
index 7b9f94a..0000000
--- a/libmaple/stm32f2/include/series/spi.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2012 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/spi.h
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F2 SPI/I2S series header.
- */
-
-#ifndef _LIBMAPLE_STM32F2_SPI_H_
-#define _LIBMAPLE_STM32F2_SPI_H_
-
-#include <libmaple/gpio.h> /* for gpio_af */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Register map base pointers
- */
-
-struct spi_reg_map;
-
-#define SPI1_BASE ((struct spi_reg_map*)0x40013000)
-#define SPI2_BASE ((struct spi_reg_map*)0x40003800)
-#define SPI3_BASE ((struct spi_reg_map*)0x40003C00)
-
-/*
- * Register bit definitions
- */
-
-/* Control register 2 */
-
-#define SPI_CR2_FRF_BIT 4
-
-#define SPI_CR2_FRF (1U << SPI_CR2_FRF_BIT)
-
-/* Status register */
-
-#define SPI_SR_TIFRFE_BIT 8
-
-#define SPI_SR_TIFRFE (1U << SPI_SR_TIFRFE_BIT)
-
-/*
- * Device pointers
- */
-
-struct spi_dev;
-
-extern struct spi_dev *SPI1;
-extern struct spi_dev *SPI2;
-extern struct spi_dev *SPI3;
-
-/*
- * Routines
- */
-
-gpio_af spi_get_af(struct spi_dev *dev);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/libmaple/stm32f2/include/series/stm32.h b/libmaple/stm32f2/include/series/stm32.h
deleted file mode 100644
index 180ab30..0000000
--- a/libmaple/stm32f2/include/series/stm32.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2011 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/stm32.h
- * @brief STM32F2 chip- and series-specific definitions.
- */
-
-#ifndef _LIBMAPLE_STM32F2_STM32_H_
-#define _LIBMAPLE_STM32F2_STM32_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Chip configuration
- */
-
-#ifndef STM32_PCLK1
-#define STM32_PCLK1 30000000U
-#endif
-
-#ifndef STM32_PCLK2
-#define STM32_PCLK2 60000000U
-#endif
-
-#ifndef STM32_DELAY_US_MULT
-#define STM32_DELAY_US_MULT 20 /* FIXME: dummy value. */
-#endif
-
-/*
- * Series- and MCU-specific values
- */
-
-#define STM32_MCU_SERIES STM32_SERIES_F2
-#define STM32_NR_INTERRUPTS 81
-#define STM32_HAVE_FSMC 1
-#define STM32_HAVE_USB 1
-#define STM32_HAVE_DAC 1
-
-#if defined(MCU_STM32F207IC) || defined(MCU_STM32F207IG)
-# define STM32_NR_GPIO_PORTS 9
-# define STM32_TIMER_MASK 0x7FFE /* TIMER1-TIMER14. */
-# define STM32_SRAM_END ((void*)0x20020000)
-#else
-#warning "Unsupported or unspecified STM32F2 MCU."
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/libmaple/stm32f2/include/series/timer.h b/libmaple/stm32f2/include/series/timer.h
deleted file mode 100644
index a7ac276..0000000
--- a/libmaple/stm32f2/include/series/timer.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2011,2012 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/timer.h
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F2 timer support.
- */
-
-#ifndef _LIBMAPLE_STM32F2_TIMER_H_
-#define _LIBMAPLE_STM32F2_TIMER_H_
-
-#include <libmaple/libmaple_types.h>
-#include <libmaple/gpio.h> /* for gpio_af */
-
-/*
- * Register maps and base pointers
- */
-
-/**
- * @brief STM32F2 general purpose timer register map type
- *
- * Note that not all general purpose timers have all of these
- * registers. Consult your chip's reference manual for the details.
- */
-typedef struct timer_gen_reg_map {
- __io uint32 CR1; /**< Control register 1 */
- __io uint32 CR2; /**< Control register 2 */
- __io uint32 SMCR; /**< Slave mode control register */
- __io uint32 DIER; /**< DMA/Interrupt enable register */
- __io uint32 SR; /**< Status register */
- __io uint32 EGR; /**< Event generation register */
- __io uint32 CCMR1; /**< Capture/compare mode register 1 */
- __io uint32 CCMR2; /**< Capture/compare mode register 2 */
- __io uint32 CCER; /**< Capture/compare enable register */
- __io uint32 CNT; /**< Counter */
- __io uint32 PSC; /**< Prescaler */
- __io uint32 ARR; /**< Auto-reload register */
- const uint32 RESERVED1; /**< Reserved */
- __io uint32 CCR1; /**< Capture/compare register 1 */
- __io uint32 CCR2; /**< Capture/compare register 2 */
- __io uint32 CCR3; /**< Capture/compare register 3 */
- __io uint32 CCR4; /**< Capture/compare register 4 */
- const uint32 RESERVED2; /**< Reserved */
- __io uint32 DCR; /**< DMA control register */
- __io uint32 DMAR; /**< DMA address for full transfer */
- __io uint32 OR; /**< Option register. */
-} timer_gen_reg_map;
-
-struct timer_adv_reg_map;
-struct timer_bas_reg_map;
-
-/** Timer 1 register map base pointer */
-#define TIMER1_BASE ((struct timer_adv_reg_map*)0x40010000)
-/** Timer 2 register map base pointer */
-#define TIMER2_BASE ((struct timer_gen_reg_map*)0x40000000)
-/** Timer 3 register map base pointer */
-#define TIMER3_BASE ((struct timer_gen_reg_map*)0x40000400)
-/** Timer 4 register map base pointer */
-#define TIMER4_BASE ((struct timer_gen_reg_map*)0x40000800)
-/** Timer 5 register map base pointer */
-#define TIMER5_BASE ((struct timer_gen_reg_map*)0x40000C00)
-/** Timer 6 register map base pointer */
-#define TIMER6_BASE ((struct timer_bas_reg_map*)0x40001000)
-/** Timer 7 register map base pointer */
-#define TIMER7_BASE ((struct timer_bas_reg_map*)0x40001400)
-/** Timer 8 register map base pointer */
-#define TIMER8_BASE ((struct timer_adv_reg_map*)0x40010400)
-/** Timer 9 register map base pointer */
-#define TIMER9_BASE ((struct timer_gen_reg_map*)0x40014000)
-/** Timer 10 register map base pointer */
-#define TIMER10_BASE ((struct timer_gen_reg_map*)0x40014400)
-/** Timer 11 register map base pointer */
-#define TIMER11_BASE ((struct timer_gen_reg_map*)0x40014800)
-/** Timer 12 register map base pointer */
-#define TIMER12_BASE ((struct timer_gen_reg_map*)0x40001800)
-/** Timer 13 register map base pointer */
-#define TIMER13_BASE ((struct timer_gen_reg_map*)0x40001C00)
-/** Timer 14 register map base pointer */
-#define TIMER14_BASE ((struct timer_gen_reg_map*)0x40002000)
-
-/*
- * Register bit definitions
- */
-
-/* TIM2 option register */
-
-/** Timer 2 option register internal trigger 1 remap */
-#define TIMER2_OR_ITR1_RMP (0x3 << 10)
-/** Timer 2 OR internal trigger 1: TIM8_TRGOUT */
-#define TIMER2_OR_ITR1_RMP_TIM8_TRGOUT (0x0 << 10)
-/** Timer 2 OR internal trigger 1: Ethernet PTP trigger output */
-#define TIMER2_OR_ITR1_RMP_PTP_TRGOUT (0x1 << 10)
-/** Timer 2 OR internal trigger 1: USB OTG full speed start of frame */
-#define TIMER2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
-/** Timer 2 OR internal trigger 1: USB OTG high speed start of frame */
-#define TIMER2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
-
-/* TIM5 option register */
-
-/**
- * Timer 5 option register input 4 remap.
- *
- * These bits control whether TIM5_CH4 is connected to a GPIO or a
- * clock. Connecting to a GPIO is the normal mode, useful for e.g. PWM
- * generation or input pulse duration measurement. Connecting to a
- * clock is useful for calibrating that clock.
- */
-#define TIMER5_OR_TI4_RMP (0x3 << 6)
-/**
- * Timer 5 OR input 4: Timer 5 channel 4 connected to GPIO. */
-#define TIMER5_OR_TI4_RMP_GPIO (0x0 << 6)
-/**
- * Timer 5 OR input 4: low speed internal clock (LSI) is connected to
- * TIM5_CH4. */
-#define TIMER5_OR_TI4_RMP_LSI (0x1 << 6)
-/**
- * Timer 5 OR input 4: low speed external clock (LSE) is connected to
- * TIM5_CH4. */
-#define TIMER5_OR_TI4_RMP_LSE (0x2 << 6)
-/**
- * Timer 5 OR input 4: real time clock (RTC) output is connected to
- * TIM5_CH4. */
-#define TIMER5_OR_TI4_RMP_RTC (0x3 << 6)
-
-/*
- * Device pointers
- */
-
-struct timer_dev;
-
-extern struct timer_dev *TIMER1;
-extern struct timer_dev *TIMER2;
-extern struct timer_dev *TIMER3;
-extern struct timer_dev *TIMER4;
-extern struct timer_dev *TIMER5;
-extern struct timer_dev *TIMER6;
-extern struct timer_dev *TIMER7;
-extern struct timer_dev *TIMER8;
-extern struct timer_dev *TIMER9;
-extern struct timer_dev *TIMER10;
-extern struct timer_dev *TIMER11;
-extern struct timer_dev *TIMER12;
-extern struct timer_dev *TIMER13;
-extern struct timer_dev *TIMER14;
-
-/*
- * Routines
- */
-
-gpio_af timer_get_af(struct timer_dev *dev);
-
-#endif
diff --git a/libmaple/stm32f2/include/series/usart.h b/libmaple/stm32f2/include/series/usart.h
deleted file mode 100644
index 8936efa..0000000
--- a/libmaple/stm32f2/include/series/usart.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2012 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f2/include/series/usart.h
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F2 USART support.
- */
-
-#ifndef _LIBMAPLE_STM32F2_USART_H_
-#define _LIBMAPLE_STM32F2_USART_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <libmaple/gpio.h> /* for gpio_af */
-
-/*
- * Register map base pointers.
- */
-
-struct usart_reg_map;
-
-/** USART1 register map base pointer */
-#define USART1_BASE ((struct usart_reg_map*)0x40011000)
-/** USART2 register map base pointer */
-#define USART2_BASE ((struct usart_reg_map*)0x40004400)
-/** USART3 register map base pointer */
-#define USART3_BASE ((struct usart_reg_map*)0x40004800)
-/** UART4 register map base pointer */
-#define UART4_BASE ((struct usart_reg_map*)0x40004C00)
-/** UART5 register map base pointer */
-#define UART5_BASE ((struct usart_reg_map*)0x40005000)
-/** USART6 register map base pointer */
-#define USART6_BASE ((struct usart_reg_map*)0x40011400)
-
-/*
- * F2-only register bit definitions.
- */
-
-/* Control register 1 */
-
-/**
- * @brief Oversampling mode bit.
- * Availability: STM32F2. */
-#define USART_CR1_OVER8_BIT 15
-
-/**
- * @brief Oversampling mode.
- * Availability: STM32F2. */
-#define USART_CR1_OVER8 (1U << USART_CR1_OVER8_BIT)
-
-/* Control register 3 */
-
-/** One sample bit method enable bit. */
-#define USART_CR3_ONEBIT_BIT 11
-
-/** One bit sample method enable. */
-#define USART_CR3_ONEBIT (1 << USART_CR3_ONEBIT_BIT)
-/** Sample method: Three sample bit method. */
-#define USART_CR3_ONEBIT_3SAMPLE (0 << USART_CR3_ONEBIT_BIT)
-/** Sample method: One sample bit method. */
-#define USART_CR3_ONEBIT_1SAMPLE (1 << USART_CR3_ONEBIT_BIT)
-
-/*
- * Devices
- */
-
-struct usart_dev;
-extern struct usart_dev *USART1;
-extern struct usart_dev *USART2;
-extern struct usart_dev *USART3;
-extern struct usart_dev *UART4;
-extern struct usart_dev *UART5;
-extern struct usart_dev *USART6;
-
-/*
- * Routines
- */
-
-gpio_af usart_get_af(struct usart_dev *dev);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif