Resurrect ADC support.

Standard refactoring: add series headers for F1 and F2, along with
series adc.c files. There are some issues relating to adc_extsel_event
to hammer out later, but this will do for now.

We also add some new portability interfaces to libmaple/adc.h in order
for Wirish to use the same code to initialize the ADCs at init() time.

As usual, F1 is untested.

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

1 files changed, 25 insertions, 7 deletions

diff --git a/wirish/stm32f2/boards_setup.cpp b/wirish/stm32f2/boards_setup.cpp
index b3c690c..e1bf1fd 100644
--- a/wirish/stm32f2/boards_setup.cpp
+++ b/wirish/stm32f2/boards_setup.cpp
@@ -28,11 +28,18 @@
  * @file wirish/stm32f2/boards_setup.cpp
  * @author Marti Bolivar <mbolivar@leaflabs.com>
  * @brief STM32F2 chip setup.
+ *
+ * This file controls how init() behaves on the STM32F2. Be very
+ * careful when changing anything here. Many of these values depend
+ * upon each other.
  */
 
-#include <libmaple/rcc.h>
+#include "boards_private.h"
+
 #include <libmaple/gpio.h>
+#include <wirish/wirish_types.h>
 
+// PLL configuration for 25 MHz external oscillator --> 120 MHz SYSCLK.
 #define PLL_Q 5
 #define PLL_P 2
 #define PLL_N 240
@@ -41,7 +48,18 @@ static stm32f2_rcc_pll_data pll_data = {PLL_Q, PLL_P, PLL_N, PLL_M};
 
 namespace wirish {
     namespace priv {
-        rcc_pll_cfg board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
+        // PLL clocked off of HSE, with above configuration data.
+        rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
+        // As f_APB2 = 60 MHz (see board_setup_clock_prescalers),
+        // we need f_ADC = f_PCLK2 / 2 to get the (maximum)
+        // f_ADC = 30 MHz.
+        adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_2;
+        // With clocks as specified here (i.e. f_ADC = 30 MHz), this
+        // ADC sample rate allows for error less than 1/4 LSB with a
+        // 50 KOhm input impedance, assuming an internal sample and
+        // hold capacitance C_ADC at most 8.8 pF. See Equation 1 and
+        // Table 61 in the F2 datasheet for more details.
+        adc_smp_rate w_adc_smp = ADC_SMPR_144;
 
         void board_reset_pll(void) {
             // Set PLLCFGR to its reset value.
@@ -49,8 +67,13 @@ namespace wirish {
         }
 
         void board_setup_clock_prescalers(void) {
+            // With f_SYSCLK = 120 MHz (as determined by board_pll_cfg),
+            //
+            // f_AHB = f_SYSCLK / 1 = 120 MHz
             rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1);
+            // f_APB1 = f_AHB / 4 = 30 MHz
             rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_4);
+            // f_APB2 = f_AHB / 2 = 60 MHz
             rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_2);
         }
 
@@ -58,10 +81,6 @@ namespace wirish {
             gpio_init_all();
         }
 
-        void board_setup_adc(void) {
-            // TODO
-        }
-
         void board_setup_timers(void) {
             // TODO
         }
@@ -72,4 +91,3 @@ namespace wirish {
 
     }
 }
-