diff options
| author | iperry <iperry@749a229e-a60e-11de-b98f-4500b42dc123> | 2009-12-17 02:37:07 +0000 |
|---|---|---|
| committer | iperry <iperry@749a229e-a60e-11de-b98f-4500b42dc123> | 2009-12-17 02:37:07 +0000 |
| commit | 32e57dac2e61e79b029593eb4d34d727bcc10678 (patch) | |
| tree | 98d7ff41993576bb150d13d5f63dc744f6812852 /src/stm32lib/examples/FSMC/NAND | |
| download | librambutan-32e57dac2e61e79b029593eb4d34d727bcc10678.tar.gz librambutan-32e57dac2e61e79b029593eb4d34d727bcc10678.zip | |
Initial commit of library code, moved from leaftest repo
git-svn-id: https://leaflabs.googlecode.com/svn/trunk/library@69 749a229e-a60e-11de-b98f-4500b42dc123
Diffstat (limited to 'src/stm32lib/examples/FSMC/NAND')
| -rwxr-xr-x | src/stm32lib/examples/FSMC/NAND/fsmc_nand.c | 491 | ||||
| -rwxr-xr-x | src/stm32lib/examples/FSMC/NAND/fsmc_nand.h | 99 | ||||
| -rwxr-xr-x | src/stm32lib/examples/FSMC/NAND/main.c | 247 | ||||
| -rwxr-xr-x | src/stm32lib/examples/FSMC/NAND/readme.txt | 56 | ||||
| -rwxr-xr-x | src/stm32lib/examples/FSMC/NAND/stm32f10x_conf.h | 170 | ||||
| -rwxr-xr-x | src/stm32lib/examples/FSMC/NAND/stm32f10x_it.c | 810 | ||||
| -rwxr-xr-x | src/stm32lib/examples/FSMC/NAND/stm32f10x_it.h | 100 |
7 files changed, 1973 insertions, 0 deletions
diff --git a/src/stm32lib/examples/FSMC/NAND/fsmc_nand.c b/src/stm32lib/examples/FSMC/NAND/fsmc_nand.c new file mode 100755 index 0000000..7cc15e7 --- /dev/null +++ b/src/stm32lib/examples/FSMC/NAND/fsmc_nand.c @@ -0,0 +1,491 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : fsmc_nand.c
+* Author : MCD Application Team
+* Version : V2.0.1
+* Date : 06/13/2008
+* Description : This file provides a set of functions needed to drive the
+* NAND512W3A2 memory mounted on STM3210E-EVAL board.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+/* Includes ------------------------------------------------------------------*/
+#include "fsmc_nand.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define FSMC_Bank_NAND FSMC_Bank2_NAND
+#define Bank_NAND_ADDR Bank2_NAND_ADDR
+#define Bank2_NAND_ADDR ((u32)0x70000000)
+
+/* Private macro -------------------------------------------------------------*/
+#define ROW_ADDRESS (Address.Page + (Address.Block + (Address.Zone * NAND_ZONE_SIZE)) * NAND_BLOCK_SIZE)
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name : FSMC_NAND_Init
+* Description : Configures the FSMC and GPIOs to interface with the NAND memory.
+* This function must be called before any write/read operation
+* on the NAND.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void FSMC_NAND_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+ FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
+ FSMC_NAND_PCCARDTimingInitTypeDef p;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
+ RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);
+
+/*-- GPIO Configuration ------------------------------------------------------*/
+/* CLE, ALE, D0->D3, NOE, NWE and NCE2 NAND pin configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_14 | GPIO_Pin_15 |
+ GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 |
+ GPIO_Pin_7;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+/* D4->D7 NAND pin configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
+
+ GPIO_Init(GPIOE, &GPIO_InitStructure);
+
+
+/* NWAIT NAND pin configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+/* INT2 NAND pin configuration */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+ GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+ /*-- FSMC Configuration ------------------------------------------------------*/
+ p.FSMC_SetupTime = 0x1;
+ p.FSMC_WaitSetupTime = 0x3;
+ p.FSMC_HoldSetupTime = 0x2;
+ p.FSMC_HiZSetupTime = 0x1;
+
+ FSMC_NANDInitStructure.FSMC_Bank = FSMC_Bank2_NAND;
+ FSMC_NANDInitStructure.FSMC_Waitfeature = FSMC_Waitfeature_Enable;
+ FSMC_NANDInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+ FSMC_NANDInitStructure.FSMC_ECC = FSMC_ECC_Enable;
+ FSMC_NANDInitStructure.FSMC_ECCPageSize = FSMC_ECCPageSize_512Bytes;
+ FSMC_NANDInitStructure.FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
+ FSMC_NANDInitStructure.FSMC_TCLRSetupTime = 0x00;
+ FSMC_NANDInitStructure.FSMC_TARSetupTime = 0x00;
+ FSMC_NANDInitStructure.FSMC_CommonSpaceTimingStruct = &p;
+ FSMC_NANDInitStructure.FSMC_AttributeSpaceTimingStruct = &p;
+
+ FSMC_NANDInit(&FSMC_NANDInitStructure);
+
+ /* FSMC NAND Bank Cmd Test */
+ FSMC_NANDCmd(FSMC_Bank2_NAND, ENABLE);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NAND_ReadID
+* Description : Reads NAND memory's ID.
+* Input : - NAND_ID: pointer to a NAND_IDTypeDef structure which will hold
+* the Manufacturer and Device ID.
+* Output : None
+* Return : None
+*******************************************************************************/
+void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID)
+{
+ u32 data = 0;
+
+ /* Send Command to the command area */
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = 0x90;
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
+
+ /* Sequence to read ID from NAND flash */
+ data = *(vu32 *)(Bank_NAND_ADDR | DATA_AREA);
+
+ NAND_ID->Maker_ID = ADDR_1st_CYCLE (data);
+ NAND_ID->Device_ID = ADDR_2nd_CYCLE (data);
+ NAND_ID->Third_ID = ADDR_3rd_CYCLE (data);
+ NAND_ID->Fourth_ID = ADDR_4th_CYCLE (data);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NAND_WriteSmallPage
+* Description : This routine is for writing one or several 512 Bytes Page size.
+* Input : - pBuffer: pointer on the Buffer containing data to be written
+* - Address: First page address
+* - NumPageToWrite: Number of page to write
+* Output : None
+* Return : New status of the NAND operation. This parameter can be:
+* - NAND_TIMEOUT_ERROR: when the previous operation generate
+* a Timeout error
+* - NAND_READY: when memory is ready for the next operation
+* And the new status of the increment address operation. It can be:
+* - NAND_VALID_ADDRESS: When the new address is valid address
+* - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+u32 FSMC_NAND_WriteSmallPage(u8 *pBuffer, NAND_ADDRESS Address, u32 NumPageToWrite)
+{
+ u32 index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
+ u32 status = NAND_READY, size = 0x00;
+
+ while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
+ {
+ /* Page write command and address */
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
+
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+
+ /* Calculate the size */
+ size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
+
+ /* Write data */
+ for(; index < size; index++)
+ {
+ *(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
+ }
+
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
+
+ /* Check status for successful operation */
+ status = FSMC_NAND_GetStatus();
+
+ if(status == NAND_READY)
+ {
+ numpagewritten++;
+
+ NumPageToWrite--;
+
+ /* Calculate Next small page Address */
+ addressstatus = FSMC_NAND_AddressIncrement(&Address);
+ }
+ }
+
+ return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NAND_ReadSmallPage
+* Description : This routine is for sequential read from one or several
+* 512 Bytes Page size.
+* Input : - pBuffer: pointer on the Buffer to fill
+* - Address: First page address
+* - NumPageToRead: Number of page to read
+* Output : None
+* Return : New status of the NAND operation. This parameter can be:
+* - NAND_TIMEOUT_ERROR: when the previous operation generate
+* a Timeout error
+* - NAND_READY: when memory is ready for the next operation
+* And the new status of the increment address operation. It can be:
+* - NAND_VALID_ADDRESS: When the new address is valid address
+* - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+u32 FSMC_NAND_ReadSmallPage(u8 *pBuffer, NAND_ADDRESS Address, u32 NumPageToRead)
+{
+ u32 index = 0x00, numpageread = 0x00, addressstatus = NAND_VALID_ADDRESS;
+ u32 status = NAND_READY, size = 0x00;
+
+ while((NumPageToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* Page Read command and page address */
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
+
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1;
+
+ /* Calculate the size */
+ size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpageread);
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ pBuffer[index]= *(vu8 *)(Bank_NAND_ADDR | DATA_AREA);
+ }
+
+ numpageread++;
+
+ NumPageToRead--;
+
+ /* Calculate page address */
+ addressstatus = FSMC_NAND_AddressIncrement(&Address);
+ }
+
+ status = FSMC_NAND_GetStatus();
+
+ return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NAND_WriteSpareArea
+* Description : This routine write the spare area information for the specified
+* pages addresses.
+* Input : - pBuffer: pointer on the Buffer containing data to be written
+* - Address: First page address
+* - NumSpareAreaTowrite: Number of Spare Area to write
+* Output : None
+* Return : New status of the NAND operation. This parameter can be:
+* - NAND_TIMEOUT_ERROR: when the previous operation generate
+* a Timeout error
+* - NAND_READY: when memory is ready for the next operation
+* And the new status of the increment address operation. It can be:
+* - NAND_VALID_ADDRESS: When the new address is valid address
+* - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+u32 FSMC_NAND_WriteSpareArea(u8 *pBuffer, NAND_ADDRESS Address, u32 NumSpareAreaTowrite)
+{
+ u32 index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
+ u32 status = NAND_READY, size = 0x00;
+
+ while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
+ {
+ /* Page write Spare area command and address */
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
+
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+
+ /* Calculate the size */
+ size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
+
+ /* Write the data */
+ for(; index < size; index++)
+ {
+ *(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
+ }
+
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
+
+ /* Check status for successful operation */
+ status = FSMC_NAND_GetStatus();
+
+ if(status == NAND_READY)
+ {
+ numsparesreawritten++;
+
+ NumSpareAreaTowrite--;
+
+ /* Calculate Next page Address */
+ addressstatus = FSMC_NAND_AddressIncrement(&Address);
+ }
+ }
+
+ return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NAND_ReadSpareArea
+* Description : This routine read the spare area information from the specified
+* pages addresses.
+* Input : - pBuffer: pointer on the Buffer to fill
+* - Address: First page address
+* - NumSpareAreaToRead: Number of Spare Area to read
+* Output : None
+* Return : New status of the NAND operation. This parameter can be:
+* - NAND_TIMEOUT_ERROR: when the previous operation generate
+* a Timeout error
+* - NAND_READY: when memory is ready for the next operation
+* And the new status of the increment address operation. It can be:
+* - NAND_VALID_ADDRESS: When the new address is valid address
+* - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+u32 FSMC_NAND_ReadSpareArea(u8 *pBuffer, NAND_ADDRESS Address, u32 NumSpareAreaToRead)
+{
+ u32 numsparearearead = 0x00, index = 0x00, addressstatus = NAND_VALID_ADDRESS;
+ u32 status = NAND_READY, size = 0x00;
+
+ while((NumSpareAreaToRead != 0x0) && (addressstatus == NAND_VALID_ADDRESS))
+ {
+ /* Page Read command and page address */
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
+
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_TRUE1;
+
+ /* Data Read */
+ size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparearearead);
+
+ /* Get Data into Buffer */
+ for ( ;index < size; index++)
+ {
+ pBuffer[index] = *(vu8 *)(Bank_NAND_ADDR | DATA_AREA);
+ }
+
+ numsparearearead++;
+
+ NumSpareAreaToRead--;
+
+ /* Calculate page address */
+ addressstatus = FSMC_NAND_AddressIncrement(&Address);
+ }
+
+ status = FSMC_NAND_GetStatus();
+
+ return (status | addressstatus);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NAND_EraseBlock
+* Description : This routine erase complete block from NAND FLASH
+* Input : - Address: Any address into block to be erased
+* Output : None
+* Return : New status of the NAND operation. This parameter can be:
+* - NAND_TIMEOUT_ERROR: when the previous operation generate
+* a Timeout error
+* - NAND_READY: when memory is ready for the next operation
+*******************************************************************************/
+u32 FSMC_NAND_EraseBlock(NAND_ADDRESS Address)
+{
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE0;
+
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
+ *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
+
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_ERASE1;
+
+ return (FSMC_NAND_GetStatus());
+}
+
+/******************************************************************************
+* Function Name : FSMC_NAND_Reset
+* Description : This routine reset the NAND FLASH
+* Input : None
+* Output : None
+* Return : NAND_READY
+*******************************************************************************/
+u32 FSMC_NAND_Reset(void)
+{
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
+
+ return (NAND_READY);
+}
+
+/******************************************************************************
+* Function Name : FSMC_NAND_GetStatus
+* Description : Get the NAND operation status
+* Input : None
+* Output : None
+* Return : New status of the NAND operation. This parameter can be:
+* - NAND_TIMEOUT_ERROR: when the previous operation generate
+* a Timeout error
+* - NAND_READY: when memory is ready for the next operation
+*******************************************************************************/
+u32 FSMC_NAND_GetStatus(void)
+{
+ u32 timeout = 0x1000000, status = NAND_READY;
+
+ status = FSMC_NAND_ReadStatus();
+
+ /* Wait for a NAND operation to complete or a TIMEOUT to occur */
+ while ((status != NAND_READY) &&( timeout != 0x00))
+ {
+ status = FSMC_NAND_ReadStatus();
+ timeout --;
+ }
+
+ if(timeout == 0x00)
+ {
+ status = NAND_TIMEOUT_ERROR;
+ }
+
+ /* Return the operation status */
+ return (status);
+}
+/******************************************************************************
+* Function Name : FSMC_NAND_ReadStatus
+* Description : Reads the NAND memory status using the Read status command
+* Input : None
+* Output : None
+* Return : The status of the NAND memory. This parameter can be:
+* - NAND_BUSY: when memory is busy
+* - NAND_READY: when memory is ready for the next operation
+* - NAND_ERROR: when the previous operation gererates error
+*******************************************************************************/
+u32 FSMC_NAND_ReadStatus(void)
+{
+ u32 data = 0x00, status = NAND_BUSY;
+
+ /* Read status operation ------------------------------------ */
+ *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_STATUS;
+ data = *(vu8 *)(Bank_NAND_ADDR);
+
+ if((data & NAND_ERROR) == NAND_ERROR)
+ {
+ status = NAND_ERROR;
+ }
+ else if((data & NAND_READY) == NAND_READY)
+ {
+ status = NAND_READY;
+ }
+ else
+ {
+ status = NAND_BUSY;
+ }
+
+ return (status);
+}
+
+/******************************************************************************
+* Function Name : NAND_AddressIncrement
+* Description : Increment the NAND memory address
+* Input : - Address: address to be incremented.
+* Output : None
+* Return : The new status of the increment address operation. It can be:
+* - NAND_VALID_ADDRESS: When the new address is valid address
+* - NAND_INVALID_ADDRESS: When the new address is invalid address
+*******************************************************************************/
+u32 FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address)
+{
+ u32 status = NAND_VALID_ADDRESS;
+
+ Address->Page++;
+
+ if(Address->Page == NAND_BLOCK_SIZE)
+ {
+ Address->Page = 0;
+ Address->Block++;
+
+ if(Address->Block == NAND_ZONE_SIZE)
+ {
+ Address->Block = 0;
+ Address->Zone++;
+
+ if(Address->Zone == NAND_MAX_ZONE)
+ {
+ status = NAND_INVALID_ADDRESS;
+ }
+ }
+ }
+
+ return (status);
+}
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/examples/FSMC/NAND/fsmc_nand.h b/src/stm32lib/examples/FSMC/NAND/fsmc_nand.h new file mode 100755 index 0000000..dd90682 --- /dev/null +++ b/src/stm32lib/examples/FSMC/NAND/fsmc_nand.h @@ -0,0 +1,99 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : fsmc_nand.h
+* Author : MCD Application Team
+* Version : V2.0.1
+* Date : 06/13/2008
+* Description : Header for fsmc_nand.c file.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FSMC_NAND_H
+#define __FSMC_NAND_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+ u8 Maker_ID;
+ u8 Device_ID;
+ u8 Third_ID;
+ u8 Fourth_ID;
+}NAND_IDTypeDef;
+
+typedef struct
+{
+ u16 Zone;
+ u16 Block;
+ u16 Page;
+} NAND_ADDRESS;
+
+/* Exported constants --------------------------------------------------------*/
+/* NAND Area definition for STM3210E-EVAL Board RevD */
+#define CMD_AREA (u32)(1<<16) /* A16 = CLE high */
+#define ADDR_AREA (u32)(1<<17) /* A17 = ALE high */
+
+#define DATA_AREA ((u32)0x00000000)
+
+/* FSMC NAND memory command */
+#define NAND_CMD_AREA_A ((u8)0x00)
+#define NAND_CMD_AREA_B ((u8)0x01)
+#define NAND_CMD_AREA_C ((u8)0x50)
+#define NAND_CMD_AREA_TRUE1 ((u8)0x30)
+
+#define NAND_CMD_WRITE0 ((u8)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((u8)0x10)
+
+#define NAND_CMD_ERASE0 ((u8)0x60)
+#define NAND_CMD_ERASE1 ((u8)0xD0)
+
+#define NAND_CMD_READID ((u8)0x90)
+#define NAND_CMD_STATUS ((u8)0x70)
+#define NAND_CMD_LOCK_STATUS ((u8)0x7A)
+#define NAND_CMD_RESET ((u8)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS ((u32)0x00000100)
+#define NAND_INVALID_ADDRESS ((u32)0x00000200)
+#define NAND_TIMEOUT_ERROR ((u32)0x00000400)
+#define NAND_BUSY ((u32)0x00000000)
+#define NAND_ERROR ((u32)0x00000001)
+#define NAND_READY ((u32)0x00000040)
+
+/* FSMC NAND memory parameters */
+#define NAND_PAGE_SIZE ((u16)0x0200) /* 512 bytes per page w/o Spare Area */
+#define NAND_BLOCK_SIZE ((u16)0x0020) /* 32x512 bytes pages per block */
+#define NAND_ZONE_SIZE ((u16)0x0400) /* 1024 Block per zone */
+#define NAND_SPARE_AREA_SIZE ((u16)0x0010) /* last 16 bytes as spare area */
+#define NAND_MAX_ZONE ((u16)0x0004) /* 4 zones of 1024 block */
+
+/* FSMC NAND memory address computation */
+#define ADDR_1st_CYCLE(ADDR) (u8)((ADDR)& 0xFF) /* 1st addressing cycle */
+#define ADDR_2nd_CYCLE(ADDR) (u8)(((ADDR)& 0xFF00) >> 8) /* 2nd addressing cycle */
+#define ADDR_3rd_CYCLE(ADDR) (u8)(((ADDR)& 0xFF0000) >> 16) /* 3rd addressing cycle */
+#define ADDR_4th_CYCLE(ADDR) (u8)(((ADDR)& 0xFF000000) >> 24) /* 4th addressing cycle */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+void FSMC_NAND_Init(void);
+void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID);
+u32 FSMC_NAND_WriteSmallPage(u8 *pBuffer, NAND_ADDRESS Address, u32 NumPageToWrite);
+u32 FSMC_NAND_ReadSmallPage (u8 *pBuffer, NAND_ADDRESS Address, u32 NumPageToRead);
+u32 FSMC_NAND_WriteSpareArea(u8 *pBuffer, NAND_ADDRESS Address, u32 NumSpareAreaTowrite);
+u32 FSMC_NAND_ReadSpareArea(u8 *pBuffer, NAND_ADDRESS Address, u32 NumSpareAreaToRead);
+u32 FSMC_NAND_EraseBlock(NAND_ADDRESS Address);
+u32 FSMC_NAND_Reset(void);
+u32 FSMC_NAND_GetStatus(void);
+u32 FSMC_NAND_ReadStatus(void);
+u32 FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address);
+
+#endif /* __FSMC_NAND_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/examples/FSMC/NAND/main.c b/src/stm32lib/examples/FSMC/NAND/main.c new file mode 100755 index 0000000..26ac17c --- /dev/null +++ b/src/stm32lib/examples/FSMC/NAND/main.c @@ -0,0 +1,247 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : main.c
+* Author : MCD Application Team
+* Version : V2.0.1
+* Date : 06/13/2008
+* Description : Main program body
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+/* Includes ------------------------------------------------------------------*/
+#include "fsmc_nand.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define BUFFER_SIZE 0x400
+#define NAND_ST_MakerID 0x20
+#define NAND_ST_DeviceID 0x76
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+NAND_IDTypeDef NAND_ID;
+GPIO_InitTypeDef GPIO_InitStructure;
+NAND_ADDRESS WriteReadAddr;
+
+u8 TxBuffer[BUFFER_SIZE], RxBuffer[BUFFER_SIZE];
+
+ErrorStatus HSEStartUpStatus;
+vu32 PageNumber = 2, WriteReadStatus = 0, status= 0;
+u32 j = 0;
+
+/* Private function prototypes -----------------------------------------------*/
+void RCC_Configuration(void);
+void NVIC_Configuration(void);
+void Fill_Buffer(u8 *pBuffer, u16 BufferLenght, u32 Offset);
+
+/* Private functions ---------------------------------------------------------*/
+/*******************************************************************************
+* Function Name : main
+* Description : Main program.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+int main(void)
+{
+
+#ifdef DEBUG
+ debug();
+#endif
+
+ /* System Clocks Configuration */
+ RCC_Configuration();
+
+ /* NVIC Configuration */
+ NVIC_Configuration();
+
+ /* PF.06, PF.07 and PF.08 config to drive LD1, LD2 and LD3 *****************/
+ /* Enable GPIOF clock */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF, ENABLE);
+
+ /* Configure PF.06, PF.07 and PF.08 as Output push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOF, &GPIO_InitStructure);
+
+ /* Enable the FSMC Clock */
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+
+ /* FSMC Initialization */
+ FSMC_NAND_Init();
+
+ /* NAND read ID command */
+ FSMC_NAND_ReadID(&NAND_ID);
+
+ /* Verify the NAND ID */
+ if((NAND_ID.Maker_ID == NAND_ST_MakerID) && (NAND_ID.Device_ID == NAND_ST_DeviceID))
+ {
+
+ /* NAND memory address to write to */
+ WriteReadAddr.Zone = 0x00;
+ WriteReadAddr.Block = 0x00;
+ WriteReadAddr.Page = 0x00;
+
+ /* Erase the NAND first Block */
+ status = FSMC_NAND_EraseBlock(WriteReadAddr);
+
+ /* Write data to FSMC NAND memory */
+ /* Fill the buffer to send */
+ Fill_Buffer(TxBuffer, BUFFER_SIZE , 0x66);
+
+ status = FSMC_NAND_WriteSmallPage(TxBuffer, WriteReadAddr, PageNumber);
+
+ /* Read back the written data */
+ status = FSMC_NAND_ReadSmallPage (RxBuffer, WriteReadAddr, PageNumber);
+
+ /* Verify the written data */
+ for(j = 0; j < BUFFER_SIZE; j++)
+ {
+ if(TxBuffer[j] != RxBuffer[j])
+ {
+ WriteReadStatus++;
+ }
+ }
+
+ if (WriteReadStatus == 0)
+ { /* OK */
+ /* Turn on LD1 */
+ GPIO_SetBits(GPIOF, GPIO_Pin_6);
+ }
+ else
+ { /* KO */
+ /* Turn on LD2 */
+ GPIO_SetBits(GPIOF, GPIO_Pin_7);
+ }
+ }
+ else
+ {
+ /* Turn on LD3 */
+ GPIO_SetBits(GPIOF, GPIO_Pin_8);
+ }
+
+ while(1)
+ {
+ }
+}
+
+/*******************************************************************************
+* Function Name : RCC_Configuration
+* Description : Configures the different system clocks.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_Configuration(void)
+{
+ /* RCC system reset(for debug purpose) */
+ RCC_DeInit();
+
+ /* Enable HSE */
+ RCC_HSEConfig(RCC_HSE_ON);
+
+ /* Wait till HSE is ready */
+ HSEStartUpStatus = RCC_WaitForHSEStartUp();
+
+ if(HSEStartUpStatus == SUCCESS)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
+
+ /* Flash 2 wait state */
+ FLASH_SetLatency(FLASH_Latency_2);
+
+ /* HCLK = SYSCLK */
+ RCC_HCLKConfig(RCC_SYSCLK_Div1);
+
+ /* PCLK2 = HCLK */
+ RCC_PCLK2Config(RCC_HCLK_Div1);
+
+ /* PCLK1 = HCLK/2 */
+ RCC_PCLK1Config(RCC_HCLK_Div2);
+
+ /* PLLCLK = 8MHz * 9 = 72 MHz */
+ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
+
+ /* Enable PLL */
+ RCC_PLLCmd(ENABLE);
+
+ /* Wait till PLL is ready */
+ while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+ /* Wait till PLL is used as system clock source */
+ while(RCC_GetSYSCLKSource() != 0x08)
+ {
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name : NVIC_Configuration
+* Description : Configures Vector Table base location.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+#ifdef VECT_TAB_RAM
+ /* Set the Vector Table base location at 0x20000000 */
+ NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else /* VECT_TAB_FLASH */
+ /* Set the Vector Table base location at 0x08000000 */
+ NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+}
+
+/*******************************************************************************
+* Function name : Fill_Buffer
+* Description : Fill the buffer
+* Input : - pBuffer: pointer on the Buffer to fill
+* - BufferSize: size of the buffer to fill
+* - Offset: first value to fill on the Buffer
+* Output param : None
+*******************************************************************************/
+void Fill_Buffer(u8 *pBuffer, u16 BufferLenght, u32 Offset)
+{
+ u16 IndexTmp = 0;
+
+ /* Put in global buffer same values */
+ for (IndexTmp = 0; IndexTmp < BufferLenght; IndexTmp++ )
+ {
+ pBuffer[IndexTmp] = IndexTmp + Offset;
+ }
+}
+
+#ifdef DEBUG
+/*******************************************************************************
+* Function Name : assert_failed
+* Description : Reports the name of the source file and the source line number
+* where the assert_param error has occurred.
+* Input : - file: pointer to the source file name
+* - line: assert_param error line source number
+* Output : None
+* Return : None
+*******************************************************************************/
+void assert_failed(u8* file, u32 line)
+{
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+ /* Infinite loop */
+ while (1)
+ {
+ }
+}
+#endif
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/examples/FSMC/NAND/readme.txt b/src/stm32lib/examples/FSMC/NAND/readme.txt new file mode 100755 index 0000000..bd78bb4 --- /dev/null +++ b/src/stm32lib/examples/FSMC/NAND/readme.txt @@ -0,0 +1,56 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : readme.txt
+* Author : MCD Application Team
+* Version : V2.0.1
+* Date : 06/13/2008
+* Description : Description of the FSMC NAND Example.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+Example description
+===================
+This example provides a basic example of how to use the FSMC firmware library and
+an associate driver to perform erase/read/write operations on the NAND512W3A2 memory
+mounted on STM3210E-EVAL board.
+
+
+Directory contents
+==================
+stm32f10x_conf.h Library Configuration file
+stm32f10x_it.c Interrupt handlers
+stm32f10x_it.h Header for stm32f10x_it.c
+fsmc_nand.c Driver for NAND memory
+fsmc_nand.h Header for fsmc_nand.c
+main.c Main program
+
+
+Hardware environment
+====================
+This example runs on STMicroelectronics STM3210E-EVAL evaluation board RevD.
+
+Note: make sure that the Jumper 7 (JP7) is in position 1<-->2.
+
+
+How to use it
+=============
+In order to make the program work, you must do the following:
+- Create a project and setup all your toolchain's start-up files
+- Compile the directory content files and required Library files:
+ + stm32f10x_lib.c
+ + stm32f10x_gpio.c
+ + stm32f10x_rcc.c
+ + stm32f10x_nvic.c
+ + stm32f10x_flash.c
+ + stm32f10x_fsmc.c
+
+- Link all compiled files and load your image into target memory
+- Run the example
+
+
+******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE******
diff --git a/src/stm32lib/examples/FSMC/NAND/stm32f10x_conf.h b/src/stm32lib/examples/FSMC/NAND/stm32f10x_conf.h new file mode 100755 index 0000000..48e488f --- /dev/null +++ b/src/stm32lib/examples/FSMC/NAND/stm32f10x_conf.h @@ -0,0 +1,170 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_conf.h
+* Author : MCD Application Team
+* Version : V2.0.1
+* Date : 06/13/2008
+* Description : Library configuration file.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_type.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to compile the library in DEBUG mode, this will expanse
+ the "assert_param" macro in the firmware library code (see "Exported macro"
+ section below) */
+/*#define DEBUG 1*/
+
+/* Comment the line below to disable the specific peripheral inclusion */
+/************************************* ADC ************************************/
+//#define _ADC
+//#define _ADC1
+//#define _ADC2
+//#define _ADC3
+
+/************************************* BKP ************************************/
+//#define _BKP
+
+/************************************* CAN ************************************/
+//#define _CAN
+
+/************************************* CRC ************************************/
+//#define _CRC
+
+/************************************* DAC ************************************/
+//#define _DAC
+
+/************************************* DBGMCU *********************************/
+//#define _DBGMCU
+
+/************************************* DMA ************************************/
+//#define _DMA
+//#define _DMA1_Channel1
+//#define _DMA1_Channel2
+//#define _DMA1_Channel3
+//#define _DMA1_Channel4
+//#define _DMA1_Channel5
+//#define _DMA1_Channel6
+//#define _DMA1_Channel7
+//#define _DMA2_Channel1
+//#define _DMA2_Channel2
+//#define _DMA2_Channel3
+//#define _DMA2_Channel4
+//#define _DMA2_Channel5
+
+/************************************* EXTI ***********************************/
+//#define _EXTI
+
+/************************************* FLASH and Option Bytes *****************/
+#define _FLASH
+/* Uncomment the line below to enable FLASH program/erase/protections functions,
+ otherwise only FLASH configuration (latency, prefetch, half cycle) functions
+ are enabled */
+/* #define _FLASH_PROG */
+
+/************************************* FSMC ***********************************/
+#define _FSMC
+
+/************************************* GPIO ***********************************/
+#define _GPIO
+//#define _GPIOA
+//#define _GPIOB
+//#define _GPIOC
+#define _GPIOD
+#define _GPIOE
+#define _GPIOF
+#define _GPIOG
+#define _AFIO
+
+/************************************* I2C ************************************/
+//#define _I2C
+//#define _I2C1
+//#define _I2C2
+
+/************************************* IWDG ***********************************/
+//#define _IWDG
+
+/************************************* NVIC ***********************************/
+#define _NVIC
+
+/************************************* PWR ************************************/
+//#define _PWR
+
+/************************************* RCC ************************************/
+#define _RCC
+
+/************************************* RTC ************************************/
+//#define _RTC
+
+/************************************* SDIO ***********************************/
+//#define _SDIO
+
+/************************************* SPI ************************************/
+//#define _SPI
+//#define _SPI1
+//#define _SPI2
+//#define _SPI3
+
+/************************************* SysTick ********************************/
+//#define _SysTick
+
+/************************************* TIM ************************************/
+//#define _TIM
+//#define _TIM1
+//#define _TIM2
+//#define _TIM3
+//#define _TIM4
+//#define _TIM5
+//#define _TIM6
+//#define _TIM7
+//#define _TIM8
+
+/************************************* USART **********************************/
+//#define _USART
+//#define _USART1
+//#define _USART2
+//#define _USART3
+//#define _UART4
+//#define _UART5
+
+/************************************* WWDG ***********************************/
+//#define _WWDG
+
+/* In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application */
+#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef DEBUG
+/*******************************************************************************
+* Macro Name : assert_param
+* Description : The assert_param macro is used for function's parameters check.
+* It is used only if the library is compiled in DEBUG mode.
+* Input : - expr: If expr is false, it calls assert_failed function
+* which reports the name of the source file and the source
+* line number of the call that failed.
+* If expr is true, it returns no value.
+* Return : None
+*******************************************************************************/
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(u8* file, u32 line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* DEBUG */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/examples/FSMC/NAND/stm32f10x_it.c b/src/stm32lib/examples/FSMC/NAND/stm32f10x_it.c new file mode 100755 index 0000000..e27c1e7 --- /dev/null +++ b/src/stm32lib/examples/FSMC/NAND/stm32f10x_it.c @@ -0,0 +1,810 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_it.c
+* Author : MCD Application Team
+* Version : V2.0.1
+* Date : 06/13/2008
+* Description : Main Interrupt Service Routines.
+* This file provides template for all exceptions handler
+* and peripherals interrupt service routine.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/*******************************************************************************
+* Function Name : NMIException
+* Description : This function handles NMI exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void NMIException(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : HardFaultException
+* Description : This function handles Hard Fault exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void HardFaultException(void)
+{
+ /* Go to infinite loop when Hard Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/*******************************************************************************
+* Function Name : MemManageException
+* Description : This function handles Memory Manage exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void MemManageException(void)
+{
+ /* Go to infinite loop when Memory Manage exception occurs */
+ while (1)
+ {
+ }
+}
+
+/*******************************************************************************
+* Function Name : BusFaultException
+* Description : This function handles Bus Fault exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void BusFaultException(void)
+{
+ /* Go to infinite loop when Bus Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/*******************************************************************************
+* Function Name : UsageFaultException
+* Description : This function handles Usage Fault exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void UsageFaultException(void)
+{
+ /* Go to infinite loop when Usage Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/*******************************************************************************
+* Function Name : DebugMonitor
+* Description : This function handles Debug Monitor exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DebugMonitor(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : SVCHandler
+* Description : This function handles SVCall exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SVCHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : PendSVC
+* Description : This function handles PendSVC exception.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void PendSVC(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : SysTickHandler
+* Description : This function handles SysTick Handler.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SysTickHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : WWDG_IRQHandler
+* Description : This function handles WWDG interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void WWDG_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : PVD_IRQHandler
+* Description : This function handles PVD interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void PVD_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TAMPER_IRQHandler
+* Description : This function handles Tamper interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TAMPER_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : RTC_IRQHandler
+* Description : This function handles RTC global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTC_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : FLASH_IRQHandler
+* Description : This function handles Flash interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void FLASH_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : RCC_IRQHandler
+* Description : This function handles RCC interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RCC_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : EXTI0_IRQHandler
+* Description : This function handles External interrupt Line 0 request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI0_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : EXTI1_IRQHandler
+* Description : This function handles External interrupt Line 1 request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI1_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : EXTI2_IRQHandler
+* Description : This function handles External interrupt Line 2 request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI2_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : EXTI3_IRQHandler
+* Description : This function handles External interrupt Line 3 request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI3_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : EXTI4_IRQHandler
+* Description : This function handles External interrupt Line 4 request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI4_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA1_Channel1_IRQHandler
+* Description : This function handles DMA1 Channel 1 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA1_Channel1_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA1_Channel2_IRQHandler
+* Description : This function handles DMA1 Channel 2 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA1_Channel2_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA1_Channel3_IRQHandler
+* Description : This function handles DMA1 Channel 3 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA1_Channel3_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA1_Channel4_IRQHandler
+* Description : This function handles DMA1 Channel 4 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA1_Channel4_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA1_Channel5_IRQHandler
+* Description : This function handles DMA1 Channel 5 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA1_Channel5_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA1_Channel6_IRQHandler
+* Description : This function handles DMA1 Channel 6 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA1_Channel6_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA1_Channel7_IRQHandler
+* Description : This function handles DMA1 Channel 7 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA1_Channel7_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : ADC1_2_IRQHandler
+* Description : This function handles ADC1 and ADC2 global interrupts requests.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC1_2_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : USB_HP_CAN_TX_IRQHandler
+* Description : This function handles USB High Priority or CAN TX interrupts
+* requests.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void USB_HP_CAN_TX_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : USB_LP_CAN_RX0_IRQHandler
+* Description : This function handles USB Low Priority or CAN RX0 interrupts
+* requests.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void USB_LP_CAN_RX0_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : CAN_RX1_IRQHandler
+* Description : This function handles CAN RX1 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void CAN_RX1_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : CAN_SCE_IRQHandler
+* Description : This function handles CAN SCE interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void CAN_SCE_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : EXTI9_5_IRQHandler
+* Description : This function handles External lines 9 to 5 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI9_5_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM1_BRK_IRQHandler
+* Description : This function handles TIM1 Break interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_BRK_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM1_UP_IRQHandler
+* Description : This function handles TIM1 overflow and update interrupt
+* request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_UP_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM1_TRG_COM_IRQHandler
+* Description : This function handles TIM1 Trigger and commutation interrupts
+* requests.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_TRG_COM_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM1_CC_IRQHandler
+* Description : This function handles TIM1 capture compare interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM1_CC_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM2_IRQHandler
+* Description : This function handles TIM2 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM2_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM3_IRQHandler
+* Description : This function handles TIM3 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM3_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM4_IRQHandler
+* Description : This function handles TIM4 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM4_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : I2C1_EV_IRQHandler
+* Description : This function handles I2C1 Event interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C1_EV_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : I2C1_ER_IRQHandler
+* Description : This function handles I2C1 Error interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C1_ER_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : I2C2_EV_IRQHandler
+* Description : This function handles I2C2 Event interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C2_EV_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : I2C2_ER_IRQHandler
+* Description : This function handles I2C2 Error interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void I2C2_ER_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : SPI1_IRQHandler
+* Description : This function handles SPI1 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI1_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : SPI2_IRQHandler
+* Description : This function handles SPI2 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI2_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : USART1_IRQHandler
+* Description : This function handles USART1 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART1_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : USART2_IRQHandler
+* Description : This function handles USART2 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART2_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : USART3_IRQHandler
+* Description : This function handles USART3 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void USART3_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : EXTI15_10_IRQHandler
+* Description : This function handles External lines 15 to 10 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void EXTI15_10_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : RTCAlarm_IRQHandler
+* Description : This function handles RTC Alarm interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void RTCAlarm_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : USBWakeUp_IRQHandler
+* Description : This function handles USB WakeUp interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void USBWakeUp_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM8_BRK_IRQHandler
+* Description : This function handles TIM8 Break interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM8_BRK_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM8_UP_IRQHandler
+* Description : This function handles TIM8 overflow and update interrupt
+* request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM8_UP_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM8_TRG_COM_IRQHandler
+* Description : This function handles TIM8 Trigger and commutation interrupts
+* requests.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM8_TRG_COM_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM8_CC_IRQHandler
+* Description : This function handles TIM8 capture compare interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM8_CC_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : ADC3_IRQHandler
+* Description : This function handles ADC3 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void ADC3_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : FSMC_IRQHandler
+* Description : This function handles FSMC global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void FSMC_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : SDIO_IRQHandler
+* Description : This function handles SDIO global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SDIO_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM5_IRQHandler
+* Description : This function handles TIM5 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM5_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : SPI3_IRQHandler
+* Description : This function handles SPI3 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void SPI3_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : UART4_IRQHandler
+* Description : This function handles UART4 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void UART4_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : UART5_IRQHandler
+* Description : This function handles UART5 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void UART5_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM6_IRQHandler
+* Description : This function handles TIM6 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM6_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : TIM7_IRQHandler
+* Description : This function handles TIM7 global interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void TIM7_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA2_Channel1_IRQHandler
+* Description : This function handles DMA2 Channel 1 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA2_Channel1_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA2_Channel2_IRQHandler
+* Description : This function handles DMA2 Channel 2 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA2_Channel2_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA2_Channel3_IRQHandler
+* Description : This function handles DMA2 Channel 3 interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA2_Channel3_IRQHandler(void)
+{
+}
+
+/*******************************************************************************
+* Function Name : DMA2_Channel4_5_IRQHandler
+* Description : This function handles DMA2 Channel 4 and DMA2 Channel 5
+* interrupt request.
+* Input : None
+* Output : None
+* Return : None
+*******************************************************************************/
+void DMA2_Channel4_5_IRQHandler(void)
+{
+}
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
diff --git a/src/stm32lib/examples/FSMC/NAND/stm32f10x_it.h b/src/stm32lib/examples/FSMC/NAND/stm32f10x_it.h new file mode 100755 index 0000000..e74b6cc --- /dev/null +++ b/src/stm32lib/examples/FSMC/NAND/stm32f10x_it.h @@ -0,0 +1,100 @@ +/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
+* File Name : stm32f10x_it.h
+* Author : MCD Application Team
+* Version : V2.0.1
+* Date : 06/13/2008
+* Description : This file contains the headers of the interrupt handlers.
+********************************************************************************
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*******************************************************************************/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_lib.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMIException(void);
+void HardFaultException(void);
+void MemManageException(void);
+void BusFaultException(void);
+void UsageFaultException(void);
+void DebugMonitor(void);
+void SVCHandler(void);
+void PendSVC(void);
+void SysTickHandler(void);
+void WWDG_IRQHandler(void);
+void PVD_IRQHandler(void);
+void TAMPER_IRQHandler(void);
+void RTC_IRQHandler(void);
+void FLASH_IRQHandler(void);
+void RCC_IRQHandler(void);
+void EXTI0_IRQHandler(void);
+void EXTI1_IRQHandler(void);
+void EXTI2_IRQHandler(void);
+void EXTI3_IRQHandler(void);
+void EXTI4_IRQHandler(void);
+void DMA1_Channel1_IRQHandler(void);
+void DMA1_Channel2_IRQHandler(void);
+void DMA1_Channel3_IRQHandler(void);
+void DMA1_Channel4_IRQHandler(void);
+void DMA1_Channel5_IRQHandler(void);
+void DMA1_Channel6_IRQHandler(void);
+void DMA1_Channel7_IRQHandler(void);
+void ADC1_2_IRQHandler(void);
+void USB_HP_CAN_TX_IRQHandler(void);
+void USB_LP_CAN_RX0_IRQHandler(void);
+void CAN_RX1_IRQHandler(void);
+void CAN_SCE_IRQHandler(void);
+void EXTI9_5_IRQHandler(void);
+void TIM1_BRK_IRQHandler(void);
+void TIM1_UP_IRQHandler(void);
+void TIM1_TRG_COM_IRQHandler(void);
+void TIM1_CC_IRQHandler(void);
+void TIM2_IRQHandler(void);
+void TIM3_IRQHandler(void);
+void TIM4_IRQHandler(void);
+void I2C1_EV_IRQHandler(void);
+void I2C1_ER_IRQHandler(void);
+void I2C2_EV_IRQHandler(void);
+void I2C2_ER_IRQHandler(void);
+void SPI1_IRQHandler(void);
+void SPI2_IRQHandler(void);
+void USART1_IRQHandler(void);
+void USART2_IRQHandler(void);
+void USART3_IRQHandler(void);
+void EXTI15_10_IRQHandler(void);
+void RTCAlarm_IRQHandler(void);
+void USBWakeUp_IRQHandler(void);
+void TIM8_BRK_IRQHandler(void);
+void TIM8_UP_IRQHandler(void);
+void TIM8_TRG_COM_IRQHandler(void);
+void TIM8_CC_IRQHandler(void);
+void ADC3_IRQHandler(void);
+void FSMC_IRQHandler(void);
+void SDIO_IRQHandler(void);
+void TIM5_IRQHandler(void);
+void SPI3_IRQHandler(void);
+void UART4_IRQHandler(void);
+void UART5_IRQHandler(void);
+void TIM6_IRQHandler(void);
+void TIM7_IRQHandler(void);
+void DMA2_Channel1_IRQHandler(void);
+void DMA2_Channel2_IRQHandler(void);
+void DMA2_Channel3_IRQHandler(void);
+void DMA2_Channel4_5_IRQHandler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
|