Fix compiler errors after reverting broken commit.

4 files changed, 16 insertions, 16 deletions

diff --git a/libmaple/adc.c b/libmaple/adc.c
index 9626a40..3d38596 100644
--- a/libmaple/adc.c
+++ b/libmaple/adc.c
@@ -126,8 +126,8 @@ void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate) {
  * @param dev adc device
  */
 static void adc_calibrate(const adc_dev *dev) {
-    __io uint32 *rstcal_bit = bb_peripv(&(dev->regs->CR2), 3);
-    __io uint32 *cal_bit = bb_peripv(&(dev->regs->CR2), 2);
+    __io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
+    __io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
 
     *rstcal_bit = 1;
     while (*rstcal_bit)
diff --git a/libmaple/adc.h b/libmaple/adc.h
index 4811dbc..53ef032 100644
--- a/libmaple/adc.h
+++ b/libmaple/adc.h
@@ -175,7 +175,7 @@ static inline uint32 adc_read(const adc_dev *dev, uint8 channel) {
  * @param enable If 1, conversion on external events is enabled, 0 to disable
  */
 static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) {
-    *bb_peripv(&dev->regs->CR2, 20) = !!enable;
+    *bb_perip(&dev->regs->CR2, 20) = !!enable;
 }
 
 /**
@@ -183,7 +183,7 @@ static inline void adc_set_exttrig(const adc_dev *dev, uint8 enable) {
  * @param dev ADC device to enable
  */
 static inline void adc_enable(const adc_dev *dev) {
-    *bb_peripv(&dev->regs->CR2, 0) = 1;
+    *bb_perip(&dev->regs->CR2, 0) = 1;
 }
 
 /**
@@ -191,7 +191,7 @@ static inline void adc_enable(const adc_dev *dev) {
  * @param dev ADC device to disable
  */
 static inline void adc_disable(const adc_dev *dev) {
-    *bb_peripv(&dev->regs->CR2, 0) = 0;
+    *bb_perip(&dev->regs->CR2, 0) = 0;
 }
 
 /**
diff --git a/libmaple/bkp.c b/libmaple/bkp.c
index b152069..aaccb1f 100644
--- a/libmaple/bkp.c
+++ b/libmaple/bkp.c
@@ -57,14 +57,14 @@ void bkp_init(void) {
  * @see bkp_init()
  */
 void bkp_enable_writes(void) {
-    *bb_peripv(&PWR_BASE->CR, PWR_CR_DBP) = 1;
+    *bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 1;
 }
 
 /**
  * Disable write access to the backup registers.
  */
 void bkp_disable_writes(void) {
-    *bb_peripv(&PWR_BASE->CR, PWR_CR_DBP) = 0;
+    *bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 0;
 }
 
 /**
diff --git a/libmaple/exti.c b/libmaple/exti.c
index 8177e1e..7f56712 100644
--- a/libmaple/exti.c
+++ b/libmaple/exti.c
@@ -98,14 +98,14 @@ void exti_attach_interrupt(afio_exti_num num,
     /* Set trigger mode */
     switch (mode) {
     case EXTI_RISING:
-        *bb_peripv(&EXTI_BASE->RTSR, num) = 1;
+        *bb_perip(&EXTI_BASE->RTSR, num) = 1;
         break;
     case EXTI_FALLING:
-        *bb_peripv(&EXTI_BASE->FTSR, num) = 1;
+        *bb_perip(&EXTI_BASE->FTSR, num) = 1;
         break;
     case EXTI_RISING_FALLING:
-        *bb_peripv(&EXTI_BASE->RTSR, num) = 1;
-        *bb_peripv(&EXTI_BASE->FTSR, num) = 1;
+        *bb_perip(&EXTI_BASE->RTSR, num) = 1;
+        *bb_perip(&EXTI_BASE->FTSR, num) = 1;
         break;
     }
 
@@ -113,7 +113,7 @@ void exti_attach_interrupt(afio_exti_num num,
     afio_exti_select(num, port);
 
     /* Unmask external interrupt request */
-    *bb_peripv(&EXTI_BASE->IMR, num) = 1;
+    *bb_perip(&EXTI_BASE->IMR, num) = 1;
 
     /* Enable the interrupt line */
     enable_irq(num);
@@ -126,11 +126,11 @@ void exti_attach_interrupt(afio_exti_num num,
  */
 void exti_detach_interrupt(afio_exti_num num) {
     /* First, mask the interrupt request */
-    *bb_peripv(&EXTI_BASE->IMR, num) = 0;
+    *bb_perip(&EXTI_BASE->IMR, num) = 0;
 
     /* Then, clear the trigger selection registers */
-    *bb_peripv(&EXTI_BASE->FTSR, num) = 0;
-    *bb_peripv(&EXTI_BASE->RTSR, num) = 0;
+    *bb_perip(&EXTI_BASE->FTSR, num) = 0;
+    *bb_perip(&EXTI_BASE->RTSR, num) = 0;
 
     /* Next, disable the IRQ, unless it's multiplexed and there are
      * other active external interrupts on the same IRQ line */
@@ -210,7 +210,7 @@ void __irq_exti15_10(void) {
  */
 
 static inline void clear_pending(uint32 exti_num) {
-    *bb_peripv(&EXTI_BASE->PR, exti_num) = 1;
+    *bb_perip(&EXTI_BASE->PR, exti_num) = 1;
     /* If the pending bit is cleared as the last instruction in an ISR,
      * it won't actually be cleared in time and the ISR will fire again.
      * Insert a 2-cycle buffer to allow it to take effect. */