Initial timer refactor.

Basic PWM works.  Had some problems in testing that might be due to
USART bugs.

HardwareTimer has been removed from the build for now; I will
re-implement it in terms of the new libmaple API, but consider it
deprecated.  Let's come up with something better.

Servo is implemented in terms of HardwareTimer, so it also has been
temporarily removed from the build.

pwmWrite() likely got a little bit less inefficient due to
indirection, but the PIN_MAPs shrank by a pointer per PinMapping.

10 files changed, 1522 insertions, 1013 deletions

diff --git a/libmaple/bitband.h b/libmaple/bitband.h
index 3e02702..870abe9 100644
--- a/libmaple/bitband.h
+++ b/libmaple/bitband.h
@@ -30,6 +30,9 @@
  * @brief Bit-banding utility functions
  */
 
+#ifndef _BITBAND_H_
+#define _BITBAND_H_
+
 #define BB_SRAM_REF      0x20000000
 #define BB_SRAM_BASE     0x22000000
 #define BB_PERI_REF      0x40000000
@@ -103,3 +106,5 @@ static inline __io uint32* __bb_addr(__io void *address,
                                      uint32 bb_ref) {
     return (__io uint32*)(bb_base + ((uint32)address - bb_ref) * 32 + bit * 4);
 }
+
+#endif  /* _BITBAND_H_ */
diff --git a/libmaple/delay.h b/libmaple/delay.h
index 10839c9..e4d85c5 100644
--- a/libmaple/delay.h
+++ b/libmaple/delay.h
@@ -1,5 +1,5 @@
 /**
- *  @brief 
+ *  @brief Delay implementation
  */
 
 #ifndef _DELAY_H_
diff --git a/libmaple/nvic.h b/libmaple/nvic.h
index fe9990f..cbcd49c 100644
--- a/libmaple/nvic.h
+++ b/libmaple/nvic.h
@@ -53,9 +53,6 @@ extern "C"{
 /* System control registers  */
 #define SCB_VTOR            0xE000ED08  // Vector table offset register
 
-#define NVIC_VectTab_RAM             ((u32)0x20000000)
-#define NVIC_VectTab_FLASH           ((u32)0x08000000)
-
 #define NVIC_BASE           0xE000E100
 #define NVIC                ((nvic_reg_map*)NVIC_BASE)
 
@@ -75,52 +72,58 @@ typedef struct nvic_reg_map {
   __io uint32 STIR;                    // Software Trigger Interrupt Registers
 } nvic_reg_map;
 
-enum {
-    NVIC_NMI          = -14,
-    NVIC_MEM_MANAGE   = -12,
-    NVIC_BUS_FAULT    = -11,
-    NVIC_USAGE_FAULT  = -10,
-    NVIC_SVC          = -5,
-    NVIC_DEBUG_MON    = -4,
-    NVIC_PEND_SVC     = -2,
-    NVIC_SYSTICK      = -1,
-    NVIC_TIMER1       = 27,
-    NVIC_TIMER2       = 28,
-    NVIC_TIMER3       = 29,
-    NVIC_TIMER4       = 30,
-    NVIC_TIMER5       = 50,   // high density only (Maple Native, Maple Audio)
-    NVIC_TIMER6       = 54,   // high density only
-    NVIC_TIMER7       = 55,   // high density only
-    NVIC_TIMER8       = 46,   // high density only
-
-    NVIC_USART1       = 37,
-    NVIC_USART2       = 38,
-    NVIC_USART3       = 39,
-    NVIC_UART4        = 52,   // high density only
-    NVIC_UART5        = 53,   // high density only
-
-    NVIC_EXTI0        = 6,
-    NVIC_EXTI1        = 7,
-    NVIC_EXTI2        = 8,
-    NVIC_EXTI3        = 9,
-    NVIC_EXTI4        = 10,
-    NVIC_EXTI9_5      = 23,
-    NVIC_EXTI15_10    = 40,
-
-    NVIC_DMA_CH1      = 11,
-    NVIC_DMA_CH2      = 12,
-    NVIC_DMA_CH3      = 13,
-    NVIC_DMA_CH4      = 14,
-    NVIC_DMA_CH5      = 15,
-    NVIC_DMA_CH6      = 16,
-    NVIC_DMA_CH7      = 17,
-
-    NVIC_I2C1_EV      = 31,
-    NVIC_I2C1_ER      = 32,
-    NVIC_I2C2_EV      = 33,
-    NVIC_I2C2_ER      = 34
-};
-
+typedef enum nvic_irq_num {
+    NVIC_NMI            = -14,
+    NVIC_MEM_MANAGE     = -12,
+    NVIC_BUS_FAULT      = -11,
+    NVIC_USAGE_FAULT    = -10,
+    NVIC_SVC            = -5,
+    NVIC_DEBUG_MON      = -4,
+    NVIC_PEND_SVC       = -2,
+    NVIC_SYSTICK        = -1,
+
+    NVIC_TIMER1_BRK     = 24,
+    NVIC_TIMER1_UP      = 25,
+    NVIC_TIMER1_TRG_COM = 26,
+    NVIC_TIMER1_CC      = 27,
+    NVIC_TIMER2         = 28,
+    NVIC_TIMER3         = 29,
+    NVIC_TIMER4         = 30,
+    NVIC_TIMER5         = 50,
+    NVIC_TIMER6         = 54,
+    NVIC_TIMER7         = 55,
+    NVIC_TIMER8_BRK     = 43,
+    NVIC_TIMER8_UP      = 44,
+    NVIC_TIMER8_TRG_COM = 45,
+    NVIC_TIMER8_CC      = 46,
+
+    NVIC_USART1         = 37,
+    NVIC_USART2         = 38,
+    NVIC_USART3         = 39,
+    NVIC_UART4          = 52,
+    NVIC_UART5          = 53,
+
+    NVIC_EXTI0          = 6,
+    NVIC_EXTI1          = 7,
+    NVIC_EXTI2          = 8,
+    NVIC_EXTI3          = 9,
+    NVIC_EXTI4          = 10,
+    NVIC_EXTI9_5        = 23,
+    NVIC_EXTI15_10      = 40,
+
+    NVIC_DMA_CH1        = 11,
+    NVIC_DMA_CH2        = 12,
+    NVIC_DMA_CH3        = 13,
+    NVIC_DMA_CH4        = 14,
+    NVIC_DMA_CH5        = 15,
+    NVIC_DMA_CH6        = 16,
+    NVIC_DMA_CH7        = 17,
+
+    NVIC_I2C1_EV        = 31,
+    NVIC_I2C1_ER        = 32,
+    NVIC_I2C2_EV        = 33,
+    NVIC_I2C2_ER        = 34
+} nvic_irq_num;
 
 #define nvic_globalirq_enable()   asm volatile("cpsie i")
 #define nvic_globalirq_disable()  asm volatile("cpsid i")
diff --git a/libmaple/rules.mk b/libmaple/rules.mk
index 48b5ed4..a9d7e50 100644
--- a/libmaple/rules.mk
+++ b/libmaple/rules.mk
@@ -28,7 +28,7 @@ cSRCS_$(d) := adc.c                    \
               spi.c                    \
               syscalls.c               \
               systick.c                \
-              timers.c                 \
+              timer.c                  \
               usart.c                  \
               util.c                   \
               usb/descriptors.c        \
diff --git a/libmaple/spi.h b/libmaple/spi.h
index db8aa9c..5ebf52d 100644
--- a/libmaple/spi.h
+++ b/libmaple/spi.h
@@ -31,6 +31,9 @@
 #ifndef _SPI_H_
 #define _SPI_H_
 
+#include "libmaple_types.h"
+#include "util.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/libmaple/timer.c b/libmaple/timer.c
new file mode 100644
index 0000000..ad0ec6f
--- /dev/null
+++ b/libmaple/timer.c
@@ -0,0 +1,449 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   timer.c
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  New-style timer interface
+ */
+
+#include "timer.h"
+
+#if defined(STM32_MEDIUM_DENSITY)
+#define NR_TIMERS 4
+#elif defined(STM32_HIGH_DENSITY)
+#define NR_TIMERS 8
+#endif
+
+/* Just like the corresponding DIER bits:
+ * [0] = Update handler;
+ * [1,2,3,4] = capture/compare 1,2,3,4 handlers, respectively;
+ * [5] = COM;
+ * [6] = TRG;
+ * [7] = BRK. */
+#define NR_ADV_HANDLERS                 8
+/* Update, capture/compare 1,2,3,4; <junk>; trigger. */
+#define NR_GEN_HANDLERS                 6
+/* Update only. */
+#define NR_BAS_HANDLERS                 1
+
+static timer_dev timer1 = {
+    .regs         = {.adv = TIMER1_BASE},
+    .clk_id       = RCC_TIMER1,
+    .type         = TIMER_ADVANCED,
+    .handlers     = { [NR_ADV_HANDLERS - 1] = 0 },
+};
+timer_dev *TIMER1 = &timer1;
+
+static timer_dev timer2 = {
+    .regs         = {.gen = TIMER2_BASE},
+    .clk_id       = RCC_TIMER2,
+    .type         = TIMER_GENERAL,
+    .handlers     = { [NR_GEN_HANDLERS - 1] = 0 },
+};
+timer_dev *TIMER2 = &timer2;
+
+static timer_dev timer3 = {
+    .regs         = {.gen = TIMER3_BASE},
+    .clk_id       = RCC_TIMER3,
+    .type         = TIMER_GENERAL,
+    .handlers     = { [NR_GEN_HANDLERS - 1] = 0 },
+};
+timer_dev *TIMER3 = &timer3;
+
+static timer_dev timer4 = {
+    .regs         = {.gen = TIMER4_BASE},
+    .clk_id       = RCC_TIMER4,
+    .type         = TIMER_GENERAL,
+    .handlers     = { [NR_GEN_HANDLERS - 1] = 0 },
+};
+timer_dev *TIMER4 = &timer4;
+
+#ifdef STM32_HIGH_DENSITY
+static timer_dev timer5 = {
+    .regs         = {.gen = TIMER5_BASE},
+    .clk_id       = RCC_TIMER5,
+    .type         = TIMER_GENERAL,
+    .handlers     = { [NR_GEN_HANDLERS - 1] = 0 },
+};
+timer_dev *TIMER5 = &timer5;
+
+static timer_dev timer6 = {
+    .regs         = {.bas = TIMER6_BASE},
+    .clk_id       = RCC_TIMER6,
+    .type         = TIMER_BASIC,
+    .handlers     = { [NR_BAS_HANDLERS - 1] = 0 },
+};
+timer_dev *TIMER6 = &timer6;
+
+static timer_dev timer7 = {
+    .regs         = {.bas = TIMER7_BASE},
+    .clk_id       = RCC_TIMER7,
+    .type         = TIMER_BASIC,
+    .handlers     = { [NR_BAS_HANDLERS - 1] = 0 },
+};
+timer_dev *TIMER7 = &timer7;
+
+static timer_dev timer8 = {
+    .regs         = {.adv = TIMER8_BASE},
+    .clk_id       = RCC_TIMER8,
+    .type         = TIMER_ADVANCED,
+    .handlers     = { [NR_ADV_HANDLERS - 1] = 0 },
+};
+timer_dev *TIMER8 = &timer8;
+#endif
+
+/*
+ * Convenience routines
+ */
+
+static void disable_channel(timer_dev *dev, uint8 channel);
+static void pwm_mode(timer_dev *dev, uint8 channel);
+static void output_compare_mode(timer_dev *dev, uint8 channel);
+
+static inline void enable_irq(timer_dev *dev, uint8 interrupt);
+
+/**
+ * Initialize a timer, and reset its register map.
+ * @param dev Timer to initialize
+ */
+void timer_init(timer_dev *dev) {
+    rcc_clk_enable(dev->clk_id);
+    rcc_reset_dev(dev->clk_id);
+}
+
+/**
+ * @brief Disable a timer.
+ *
+ * The timer will stop counting, all DMA requests and interrupts will
+ * be disabled, and no state changes will be output.
+ *
+ * @param dev Timer to disable.
+ */
+void timer_disable(timer_dev *dev) {
+    (dev->regs).bas->CR1 = 0;
+    (dev->regs).bas->DIER = 0;
+    switch (dev->type) {
+    case TIMER_ADVANCED:        /* fall-through */
+    case TIMER_GENERAL:
+        (dev->regs).gen->CCER = 0;
+        break;
+    case TIMER_BASIC:
+        break;
+    }
+}
+
+/**
+ * Sets the mode of an individual timer channel.
+ *
+ * Note that not all timers can be configured in every mode.  For
+ * example, basic timers cannot be configured to output compare mode.
+ * Be sure to use a timer which is appropriate for the mode you want.
+ *
+ * @param dev Timer whose channel mode to set
+ * @param channel Relevant channel
+ * @param mode New timer mode for channel
+ */
+void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode) {
+    ASSERT(channel > 0 && channel <= 4);
+
+    /* TODO decide about the basic timers */
+    ASSERT(dev->type != TIMER_BASIC);
+    if (dev->type == TIMER_BASIC)
+        return;
+
+    switch (mode) {
+    case TIMER_DISABLED:
+        disable_channel(dev, channel);
+        break;
+    case TIMER_PWM:
+        pwm_mode(dev, channel);
+        break;
+    case TIMER_OUTPUT_COMPARE:
+        output_compare_mode(dev, channel);
+        break;
+    }
+}
+
+/**
+ * @brief Call a given function on all timers.
+ * @param fn Function to call on each timer.
+ */
+void timer_foreach(void (*fn)(timer_dev*)) {
+    fn(TIMER1);
+    fn(TIMER2);
+    fn(TIMER3);
+    fn(TIMER4);
+#ifdef STM32_HIGH_DENSITY
+    fn(TIMER5);
+    fn(TIMER6);
+    fn(TIMER7);
+    fn(TIMER8);
+#endif
+}
+
+/**
+ * @brief Attach a timer interrupt.
+ * @param dev Timer device
+ * @param interrupt Interrupt number to attach to; this may be any
+ *                  timer_interrupt_id or timer_channel value appropriate
+ *                  for the timer.
+ * @param handler Handler to attach to the given interrupt.
+ * @see timer_interrupt_id
+ * @see timer_channel
+ */
+void timer_attach_interrupt(timer_dev *dev,
+                            uint8 interrupt,
+                            voidFuncPtr handler) {
+    dev->handlers[interrupt] = handler;
+    timer_enable_interrupt(dev, interrupt);
+    enable_irq(dev, interrupt);
+}
+
+/**
+ * @brief Detach a timer interrupt.
+ * @param dev Timer device
+ * @param interrupt Interrupt number to detach; this may be any
+ *                  timer_interrupt_id or timer_channel value appropriate
+ *                  for the timer.
+ * @see timer_interrupt_id
+ * @see timer_channel
+ */
+void timer_detach_interrupt(timer_dev *dev, uint8 interrupt) {
+    timer_disable_interrupt(dev, interrupt);
+    dev->handlers[interrupt] = NULL;
+}
+
+/*
+ * IRQ handlers
+ */
+
+static inline void dispatch_adv_brk(timer_dev *dev);
+static inline void dispatch_adv_up(timer_dev *dev);
+static inline void dispatch_adv_trg_com(timer_dev *dev);
+static inline void dispatch_adv_cc(timer_dev *dev);
+static inline void dispatch_general(timer_dev *dev);
+static inline void dispatch_basic(timer_dev *dev);
+
+void __irq_tim1_brk(void) {
+    dispatch_adv_brk(TIMER1);
+}
+
+void __irq_tim1_up(void) {
+    dispatch_adv_up(TIMER1);
+}
+
+void __irq_tim1_trg_com(void) {
+    dispatch_adv_trg_com(TIMER1);
+}
+
+void __irq_tim1_cc(void) {
+    dispatch_adv_cc(TIMER1);
+}
+
+void __irq_tim2(void) {
+    dispatch_general(TIMER2);
+}
+
+void __irq_tim3(void) {
+    dispatch_general(TIMER3);
+}
+
+void __irq_tim4(void) {
+    dispatch_general(TIMER4);
+}
+
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+
+void __irq_tim5(void) {
+    dispatch_general(TIMER5);
+}
+
+void __irq_tim6(void) {
+    dispatch_basic(TIMER6);
+}
+
+void __irq_tim7(void) {
+    dispatch_basic(TIMER7);
+}
+
+void __irq_tim8_brk(void) {
+    dispatch_adv_brk(TIMER8);
+}
+
+void __irq_tim8_up(void) {
+    dispatch_adv_up(TIMER8);
+}
+
+void __irq_tim8_trg_com(void) {
+    dispatch_adv_trg_com(TIMER8);
+}
+
+void __irq_tim8_cc(void) {
+    dispatch_adv_cc(TIMER8);
+}
+#endif
+
+static inline void dispatch_irq(timer_dev *dev, uint8 iid, uint8 sr_bit);
+static inline void dispatch_cc_irqs(timer_dev *dev);
+
+static inline void dispatch_adv_brk(timer_dev *dev) {
+    dispatch_irq(dev, TIMER_BREAK_INTERRUPT, TIMER_SR_BIF_BIT);
+}
+
+static inline void dispatch_adv_up(timer_dev *dev) {
+    dispatch_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF_BIT);
+}
+
+static inline void dispatch_adv_trg_com(timer_dev *dev) {
+    dispatch_irq(dev, TIMER_TRG_INTERRUPT, TIMER_SR_TIF_BIT);
+    dispatch_irq(dev, TIMER_COM_INTERRUPT, TIMER_SR_COMIF_BIT);
+}
+
+static inline void dispatch_adv_cc(timer_dev *dev) {
+    dispatch_cc_irqs(dev);
+}
+
+static inline void dispatch_general(timer_dev *dev) {
+    dispatch_irq(dev, TIMER_TRG_INTERRUPT, TIMER_SR_TIF_BIT);
+    dispatch_cc_irqs(dev);
+    dispatch_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF_BIT);
+}
+
+static inline void dispatch_basic(timer_dev *dev) {
+    dispatch_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF_BIT);
+}
+
+static inline void dispatch_irq(timer_dev *dev, uint8 iid, uint8 sr_bit) {
+    __io uint32 *sr = &(dev->regs).bas->SR;
+    if (bb_peri_get_bit(sr, sr_bit)) {
+        if (dev->handlers[iid])
+            (dev->handlers[iid])();
+        bb_peri_set_bit(sr, sr_bit, 0);
+    }
+}
+
+static inline void dispatch_cc_irqs(timer_dev *dev) {
+    uint32 sr = (dev->regs).gen->SR;
+    uint32 sr_clear = 0;
+    uint32 b;
+
+    ASSERT(sr & (TIMER_SR_CC1IF | TIMER_SR_CC2IF |
+                 TIMER_SR_CC3IF | TIMER_SR_CC4IF));
+
+    for (b = TIMER_SR_CC1IF_BIT; b <= TIMER_SR_CC4IF_BIT; b++) {
+        uint32 mask = BIT(b);
+        if (sr & mask) {
+            if (dev->handlers[b])
+                (dev->handlers[b])();
+            sr_clear |= mask;
+        }
+    }
+
+    (dev->regs).gen->SR &= ~sr_clear;
+}
+
+/*
+ * Utilities
+ */
+
+static void disable_channel(timer_dev *dev, uint8 channel) {
+    timer_detach_interrupt(dev, channel);
+    timer_cc_disable(dev, channel);
+}
+
+static void pwm_mode(timer_dev *dev, uint8 channel) {
+    timer_disable_interrupt(dev, channel);
+    timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1, TIMER_OC_PE);
+    timer_cc_enable(dev, channel);
+}
+
+static void output_compare_mode(timer_dev *dev, uint8 channel) {
+    timer_oc_set_mode(dev, channel, TIMER_OC_MODE_ACTIVE_ON_MATCH, 0);
+    timer_cc_enable(dev, channel);
+}
+
+static void enable_advanced_irq(timer_dev *dev, timer_interrupt_id id);
+static void enable_nonmuxed_irq(timer_dev *dev);
+
+static inline void enable_irq(timer_dev *dev, timer_interrupt_id iid) {
+    if (dev->type == TIMER_ADVANCED) {
+        enable_advanced_irq(dev, iid);
+    } else {
+        enable_nonmuxed_irq(dev);
+    }
+}
+
+static void enable_advanced_irq(timer_dev *dev, timer_interrupt_id id) {
+    uint8 is_timer1 = dev->clk_id == RCC_TIMER1;
+
+    switch (id) {
+    case TIMER_UPDATE_INTERRUPT:
+        nvic_irq_enable(is_timer1 ? NVIC_TIMER1_UP : NVIC_TIMER8_UP);
+        break;
+    case TIMER_CC1_INTERRUPT:
+    case TIMER_CC2_INTERRUPT:
+    case TIMER_CC3_INTERRUPT:
+    case TIMER_CC4_INTERRUPT:
+        nvic_irq_enable(is_timer1 ? NVIC_TIMER1_CC : NVIC_TIMER8_CC);
+        break;
+    case TIMER_COM_INTERRUPT:
+    case TIMER_TRG_INTERRUPT:
+        nvic_irq_enable(is_timer1 ? NVIC_TIMER1_TRG_COM : NVIC_TIMER8_TRG_COM);
+        break;
+    case TIMER_BREAK_INTERRUPT:
+        nvic_irq_enable(is_timer1 ? NVIC_TIMER1_BRK : NVIC_TIMER8_BRK);
+        break;
+    }
+}
+
+static void enable_nonmuxed_irq(timer_dev *dev) {
+    switch (dev->clk_id) {
+    case RCC_TIMER2:
+        nvic_irq_enable(NVIC_TIMER2);
+        break;
+    case RCC_TIMER3:
+        nvic_irq_enable(NVIC_TIMER3);
+        break;
+    case RCC_TIMER4:
+        nvic_irq_enable(NVIC_TIMER4);
+        break;
+#ifdef STM32_HIGH_DENSITY
+    case RCC_TIMER5:
+        nvic_irq_enable(NVIC_TIMER5);
+        break;
+    case RCC_TIMER6:
+        nvic_irq_enable(NVIC_TIMER6);
+        break;
+    case RCC_TIMER7:
+        nvic_irq_enable(NVIC_TIMER7);
+        break;
+#endif
+    default:
+        ASSERT(0);
+        break;
+    }
+}
diff --git a/libmaple/timer.h b/libmaple/timer.h
new file mode 100644
index 0000000..025bcb0
--- /dev/null
+++ b/libmaple/timer.h
@@ -0,0 +1,1010 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   timer.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  New-style timer interface.
+ *
+ * Replaces old timers.h implementation.
+ */
+
+#ifndef _TIMERS_H_
+#define _TIMERS_H_
+
+#include "libmaple.h"
+#include "rcc.h"
+#include "nvic.h"
+#include "bitband.h"
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*
+ * Register maps and devices
+ */
+
+/** Advanced control timer register map type */
+typedef struct timer_adv_reg_map {
+    __io uint32 CR1;            /**< Control register 1 */
+    __io uint32 CR2;            /**< Control register 2 */
+    __io uint32 SMCR;           /**< Slave mode control register */
+    __io uint32 DIER;           /**< DMA/Interrupt enable register */
+    __io uint32 SR;             /**< Status register */
+    __io uint32 EGR;            /**< Event generation register  */
+    __io uint32 CCMR1;          /**< Capture/compare mode register 1 */
+    __io uint32 CCMR2;          /**< Capture/compare mode register 2 */
+    __io uint32 CCER;           /**< Capture/compare enable register */
+    __io uint32 CNT;            /**< Counter */
+    __io uint32 PSC;            /**< Prescaler */
+    __io uint32 ARR;            /**< Auto-reload register */
+    __io uint32 RCR;            /**< Repetition counter register */
+    __io uint32 CCR1;           /**< Capture/compare register 1 */
+    __io uint32 CCR2;           /**< Capture/compare register 2 */
+    __io uint32 CCR3;           /**< Capture/compare register 3 */
+    __io uint32 CCR4;           /**< Capture/compare register 4 */
+    __io uint32 BDTR;           /**< Break and dead-time register */
+    __io uint32 DCR;            /**< DMA control register */
+    __io uint32 DMAR;           /**< DMA address for full transfer */
+} timer_adv_reg_map;
+
+/** General purpose timer register map type */
+typedef struct timer_gen_reg_map {
+    __io uint32 CR1;            /**< Control register 1 */
+    __io uint32 CR2;            /**< Control register 2 */
+    __io uint32 SMCR;           /**< Slave mode control register */
+    __io uint32 DIER;           /**< DMA/Interrupt enable register */
+    __io uint32 SR;             /**< Status register */
+    __io uint32 EGR;            /**< Event generation register  */
+    __io uint32 CCMR1;          /**< Capture/compare mode register 1 */
+    __io uint32 CCMR2;          /**< Capture/compare mode register 2 */
+    __io uint32 CCER;           /**< Capture/compare enable register */
+    __io uint32 CNT;            /**< Counter */
+    __io uint32 PSC;            /**< Prescaler */
+    __io uint32 ARR;            /**< Auto-reload register */
+    const uint32 RESERVED1;     /**< Reserved */
+    __io uint32 CCR1;           /**< Capture/compare register 1 */
+    __io uint32 CCR2;           /**< Capture/compare register 2 */
+    __io uint32 CCR3;           /**< Capture/compare register 3 */
+    __io uint32 CCR4;           /**< Capture/compare register 4 */
+    const uint32 RESERVED2;     /**< Reserved */
+    __io uint32 DCR;            /**< DMA control register */
+    __io uint32 DMAR;           /**< DMA address for full transfer */
+} timer_gen_reg_map;
+
+/** Basic timer register map type */
+typedef struct timer_bas_reg_map {
+    __io uint32 CR1;            /**< Control register 1 */
+    __io uint32 CR2;            /**< Control register 2 */
+    const uint32 RESERVED1;     /**< Reserved */
+    __io uint32 DIER;           /**< DMA/Interrupt enable register */
+    __io uint32 SR;             /**< Status register */
+    __io uint32 EGR;            /**< Event generation register  */
+    const uint32 RESERVED2;     /**< Reserved */
+    const uint32 RESERVED3;     /**< Reserved */
+    const uint32 RESERVED4;     /**< Reserved */
+    __io uint32 CNT;            /**< Counter */
+    __io uint32 PSC;            /**< Prescaler */
+    __io uint32 ARR;            /**< Auto-reload register */
+} timer_bas_reg_map;
+
+/** Timer 1 register map base pointer */
+#define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40012C00)
+/** Timer 2 register map base pointer */
+#define TIMER2_BASE        ((struct timer_gen_reg_map*)0x40000000)
+/** Timer 3 register map base pointer */
+#define TIMER3_BASE        ((struct timer_gen_reg_map*)0x40000400)
+/** Timer 4 register map base pointer */
+#define TIMER4_BASE        ((struct timer_gen_reg_map*)0x40000800)
+#ifdef STM32_HIGH_DENSITY
+/** Timer 5 register map base pointer */
+#define TIMER5_BASE        ((struct timer_gen_reg_map*)0x40000C00)
+/** Timer 6 register map base pointer */
+#define TIMER6_BASE        ((struct timer_bas_reg_map*)0x40001000)
+/** Timer 7 register map base pointer */
+#define TIMER7_BASE        ((struct timer_bas_reg_map*)0x40001400)
+/** Timer 8 register map base pointer */
+#define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40013400)
+#endif
+
+/*
+ * Timer devices
+ */
+
+typedef union {
+    timer_adv_reg_map *adv;
+    timer_gen_reg_map *gen;
+    timer_bas_reg_map *bas;
+} timer_reg_map_union;
+
+typedef enum {
+    TIMER_ADVANCED,
+    TIMER_GENERAL,
+    TIMER_BASIC
+} timer_type;
+
+/** Timer device type */
+typedef struct timer_dev {
+    timer_reg_map_union regs;
+    rcc_clk_id clk_id;
+    timer_type type;
+    voidFuncPtr handlers[];
+} timer_dev;
+
+/** Timer 1 device (advanced) */
+extern timer_dev *TIMER1;
+/** Timer 2 device (general-purpose) */
+extern timer_dev *TIMER2;
+/** Timer 3 device (general-purpose) */
+extern timer_dev *TIMER3;
+/** Timer 4 device (general-purpose) */
+extern timer_dev *TIMER4;
+#ifdef STM32_HIGH_DENSITY
+/** Timer 5 device (general-purpose) */
+extern timer_dev *TIMER5;
+/** Timer 6 device (basic) */
+extern timer_dev *TIMER6;
+/** Timer 7 device (basic) */
+extern timer_dev *TIMER7;
+/** Timer 8 device (basic) */
+extern timer_dev *TIMER8;
+#endif
+
+/*
+ * Register bit definitions
+ */
+
+/* Control register 1 (CR1) */
+
+#define TIMER_CR1_ARPE_BIT              7
+#define TIMER_CR1_DIR_BIT               4
+#define TIMER_CR1_OPM_BIT               3
+#define TIMER_CR1_URS_BIT               2
+#define TIMER_CR1_UDIS_BIT              1
+#define TIMER_CR1_CEN_BIT               0
+
+#define TIMER_CR1_CKD                   (0x3 << 8)
+#define TIMER_CR1_CKD_1TCKINT           (0x0 << 8)
+#define TIMER_CR1_CKD_2TCKINT           (0x1 << 8)
+#define TIMER_CR1_CKD_4TICKINT          (0x2 << 8)
+#define TIMER_CR1_ARPE                  BIT(TIMER_CR1_ARPE_BIT)
+#define TIMER_CR1_CKD_CMS               (0x3 << 5)
+#define TIMER_CR1_CKD_CMS_EDGE          (0x0 << 5)
+#define TIMER_CR1_CKD_CMS_CENTER1       (0x1 << 5)
+#define TIMER_CR1_CKD_CMS_CENTER2       (0x2 << 5)
+#define TIMER_CR1_CKD_CMS_CENTER3       (0x3 << 5)
+#define TIMER_CR1_DIR                   BIT(TIMER_CR1_DIR_BIT)
+#define TIMER_CR1_OPM                   BIT(TIMER_CR1_OPM_BIT)
+#define TIMER_CR1_URS                   BIT(TIMER_CR1_URS_BIT)
+#define TIMER_CR1_UDIS                  BIT(TIMER_CR1_UDIS_BIT)
+#define TIMER_CR1_CEN                   BIT(TIMER_CR1_CEN_BIT)
+
+/* Control register 2 (CR2) */
+
+#define TIMER_CR2_OIS4_BIT              14
+#define TIMER_CR2_OIS3N_BIT             13
+#define TIMER_CR2_OIS3_BIT              12
+#define TIMER_CR2_OIS2N_BIT             11
+#define TIMER_CR2_OIS2_BIT              10
+#define TIMER_CR2_OIS1N_BIT             9
+#define TIMER_CR2_OIS1_BIT              8
+#define TIMER_CR2_TI1S_BIT              7 /* tills? yikes */
+#define TIMER_CR2_CCDS_BIT              3
+#define TIMER_CR2_CCUS_BIT              2
+#define TIMER_CR2_CCPC_BIT              0
+
+#define TIMER_CR2_OIS4                  BIT(TIMER_CR2_OIS4_BIT)
+#define TIMER_CR2_OIS3N                 BIT(TIMER_CR2_OIS3N_BIT)
+#define TIMER_CR2_OIS3                  BIT(TIMER_CR2_OIS3_BIT)
+#define TIMER_CR2_OIS2N                 BIT(TIMER_CR2_OIS2N_BIT)
+#define TIMER_CR2_OIS2                  BIT(TIMER_CR2_OIS2_BIT)
+#define TIMER_CR2_OIS1N                 BIT(TIMER_CR2_OIS1N_BIT)
+#define TIMER_CR2_OIS1                  BIT(TIMER_CR2_OIS1_BIT)
+#define TIMER_CR2_TI1S                  BIT(TIMER_CR2_TI1S_BIT)
+#define TIMER_CR2_MMS                   (0x7 << 4)
+#define TIMER_CR2_MMS_RESET             (0x0 << 4)
+#define TIMER_CR2_MMS_ENABLE            (0x1 << 4)
+#define TIMER_CR2_MMS_UPDATE            (0x2 << 4)
+#define TIMER_CR2_MMS_COMPARE_PULSE     (0x3 << 4)
+#define TIMER_CR2_MMS_COMPARE_OC1REF    (0x4 << 4)
+#define TIMER_CR2_MMS_COMPARE_OC2REF    (0x5 << 4)
+#define TIMER_CR2_MMS_COMPARE_OC3REF    (0x6 << 4)
+#define TIMER_CR2_MMS_COMPARE_OC4REF    (0x7 << 4)
+#define TIMER_CR2_CCDS                  BIT(TIMER_CR2_CCDS_BIT)
+#define TIMER_CR2_CCUS                  BIT(TIMER_CR2_CCUS_BIT)
+#define TIMER_CR2_CCPC                  BIT(TIMER_CR2_CCPC_BIT)
+
+/* Slave mode control register (SMCR) */
+
+#define TIMER_SMCR_ETP_BIT              15
+#define TIMER_SMCR_ECE_BIT              14
+#define TIMER_SMCR_MSM_BIT              7
+
+#define TIMER_SMCR_ETP                  BIT(TIMER_SMCR_ETP_BIT)
+#define TIMER_SMCR_ECE                  BIT(TIMER_SMCR_ECE_BIT)
+#define TIMER_SMCR_ETPS                 (0x3 << 12)
+#define TIMER_SMCR_ETPS_OFF             (0x0 << 12)
+#define TIMER_SMCR_ETPS_DIV2            (0x1 << 12)
+#define TIMER_SMCR_ETPS_DIV4            (0x2 << 12)
+#define TIMER_SMCR_ETPS_DIV8            (0x3 << 12)
+#define TIMER_SMCR_ETF                  (0xF << 12)
+#define TIMER_SMCR_MSM                  BIT(TIMER_SMCR_MSM_BIT)
+#define TIMER_SMCR_TS                   (0x3 << 4)
+#define TIMER_SMCR_TS_ITR0              (0x0 << 4)
+#define TIMER_SMCR_TS_ITR1              (0x1 << 4)
+#define TIMER_SMCR_TS_ITR2              (0x2 << 4)
+#define TIMER_SMCR_TS_ITR3              (0x3 << 4)
+#define TIMER_SMCR_TS_TI1F_ED           (0x4 << 4)
+#define TIMER_SMCR_TS_TI1FP1            (0x5 << 4)
+#define TIMER_SMCR_TS_TI2FP2            (0x6 << 4)
+#define TIMER_SMCR_TS_ETRF              (0x7 << 4)
+#define TIMER_SMCR_SMS                  0x3
+#define TIMER_SMCR_SMS_DISABLED         0x0
+#define TIMER_SMCR_SMS_ENCODER1         0x1
+#define TIMER_SMCR_SMS_ENCODER2         0x2
+#define TIMER_SMCR_SMS_ENCODER3         0x3
+#define TIMER_SMCR_SMS_RESET            0x4
+#define TIMER_SMCR_SMS_GATED            0x5
+#define TIMER_SMCR_SMS_TRIGGER          0x6
+#define TIMER_SMCR_SMS_EXTERNAL         0x7
+
+/* DMA/Interrupt enable register (DIER) */
+
+#define TIMER_DIER_TDE_BIT              14
+#define TIMER_DIER_CC4DE_BIT            12
+#define TIMER_DIER_CC3DE_BIT            11
+#define TIMER_DIER_CC2DE_BIT            10
+#define TIMER_DIER_CC1DE_BIT            9
+#define TIMER_DIER_UDE_BIT              8
+#define TIMER_DIER_TIE_BIT              6
+#define TIMER_DIER_CC4IE_BIT            4
+#define TIMER_DIER_CC3IE_BIT            3
+#define TIMER_DIER_CC2IE_BIT            2
+#define TIMER_DIER_CC1IE_BIT            1
+#define TIMER_DIER_UIE_BIT              0
+
+#define TIMER_DIER_TDE                  BIT(TIMER_DIER_TDE_BIT)
+#define TIMER_DIER_CC4DE                BIT(TIMER_DIER_CC4DE_BIT)
+#define TIMER_DIER_CC3DE                BIT(TIMER_DIER_CC3DE_BIT)
+#define TIMER_DIER_CC2DE                BIT(TIMER_DIER_CC2DE_BIT)
+#define TIMER_DIER_CC1DE                BIT(TIMER_DIER_CC1DE_BIT)
+#define TIMER_DIER_UDE                  BIT(TIMER_DIER_UDE_BIT)
+#define TIMER_DIER_TIE                  BIT(TIMER_DIER_TIE_BIT)
+#define TIMER_DIER_CC4IE                BIT(TIMER_DIER_CC4IE_BIT)
+#define TIMER_DIER_CC3IE                BIT(TIMER_DIER_CC3IE_BIT)
+#define TIMER_DIER_CC2IE                BIT(TIMER_DIER_CC2IE_BIT)
+#define TIMER_DIER_CC1IE                BIT(TIMER_DIER_CC1IE_BIT)
+#define TIMER_DIER_UIE                  BIT(TIMER_DIER_UIE_BIT)
+
+/* Status register (SR) */
+
+#define TIMER_SR_CC4OF_BIT              12
+#define TIMER_SR_CC3OF_BIT              11
+#define TIMER_SR_CC2OF_BIT              10
+#define TIMER_SR_CC1OF_BIT              9
+#define TIMER_SR_BIF_BIT                7
+#define TIMER_SR_TIF_BIT                6
+#define TIMER_SR_COMIF_BIT              5
+#define TIMER_SR_CC4IF_BIT              4
+#define TIMER_SR_CC3IF_BIT              3
+#define TIMER_SR_CC2IF_BIT              2
+#define TIMER_SR_CC1IF_BIT              1
+#define TIMER_SR_UIF_BIT                0
+
+#define TIMER_SR_CC4OF                  BIT(TIMER_SR_CC4OF_BIT)
+#define TIMER_SR_CC3OF                  BIT(TIMER_SR_CC3OF_BIT)
+#define TIMER_SR_CC2OF                  BIT(TIMER_SR_CC2OF_BIT)
+#define TIMER_SR_CC1OF                  BIT(TIMER_SR_CC1OF_BIT)
+#define TIMER_SR_BIF                    BIT(TIMER_SR_BIF_BIT)
+#define TIMER_SR_TIF                    BIT(TIMER_SR_TIF_BIT)
+#define TIMER_SR_COMIF                  BIT(TIMER_SR_COMIF_BIT)
+#define TIMER_SR_CC4IF                  BIT(TIMER_SR_CC4IF_BIT)
+#define TIMER_SR_CC3IF                  BIT(TIMER_SR_CC3IF_BIT)
+#define TIMER_SR_CC2IF                  BIT(TIMER_SR_CC2IF_BIT)
+#define TIMER_SR_CC1IF                  BIT(TIMER_SR_CC1IF_BIT)
+#define TIMER_SR_UIF                    BIT(TIMER_SR_UIF_BIT)
+
+/* Event generation register (EGR) */
+
+#define TIMER_EGR_TG_BIT                6
+#define TIMER_EGR_CC4G_BIT              4
+#define TIMER_EGR_CC3G_BIT              3
+#define TIMER_EGR_CC2G_BIT              2
+#define TIMER_EGR_CC1G_BIT              1
+#define TIMER_EGR_UG_BIT                0
+
+#define TIMER_EGR_TG                    BIT(TIMER_EGR_TG_BIT)
+#define TIMER_EGR_CC4G                  BIT(TIMER_EGR_CC4G_BIT)
+#define TIMER_EGR_CC3G                  BIT(TIMER_EGR_CC3G_BIT)
+#define TIMER_EGR_CC2G                  BIT(TIMER_EGR_CC2G_BIT)
+#define TIMER_EGR_CC1G                  BIT(TIMER_EGR_CC1G_BIT)
+#define TIMER_EGR_UG                    BIT(TIMER_EGR_UG_BIT)
+
+/* Capture/compare mode registers, common values */
+
+#define TIMER_CCMR_CCS_OUTPUT           0x0
+#define TIMER_CCMR_CCS_INPUT_TI1        0x1
+#define TIMER_CCMR_CCS_INPUT_TI2        0x2
+#define TIMER_CCMR_CCS_INPUT_TRC        0x3
+
+/* Capture/compare mode register 1 (CCMR1) */
+
+#define TIMER_CCMR1_OC2CE_BIT           15
+#define TIMER_CCMR1_OC2PE_BIT           11
+#define TIMER_CCMR1_OC2FE_BIT           10
+#define TIMER_CCMR1_OC1CE_BIT           7
+#define TIMER_CCMR1_OC1PE_BIT           3
+#define TIMER_CCMR1_OC1FE_BIT           2
+
+#define TIMER_CCMR1_OC2CE               BIT(TIMER_CCMR1_OC2CE_BIT)
+#define TIMER_CCMR1_OC2M                (0x3 << 12)
+#define TIMER_CCMR1_IC2F                (0xF << 12)
+#define TIMER_CCMR1_OC2PE               BIT(TIMER_CCMR1_OC2PE_BIT)
+#define TIMER_CCMR1_OC2FE               BIT(TIMER_CCMR1_OC2FE_BIT)
+#define TIMER_CCMR1_IC2PSC              (0x3 << 10)
+#define TIMER_CCMR1_CC2S                (0x3 << 8)
+#define TIMER_CCMR1_CC2S_OUTPUT         (TIMER_CCMR_CCS_OUTPUT << 8)
+#define TIMER_CCMR1_CC2S_INPUT_TI1      (TIMER_CCMR_CCS_INPUT_TI1 << 8)
+#define TIMER_CCMR1_CC2S_INPUT_TI2      (TIMER_CCMR_CCS_INPUT_TI2 << 8)
+#define TIMER_CCMR1_CC2S_INPUT_TRC      (TIMER_CCMR_CCS_INPUT_TRC << 8)
+#define TIMER_CCMR1_OC1CE               BIT(TIMER_CCMR1_OC1CE_BIT)
+#define TIMER_CCMR1_OC1M                (0x3 << 4)
+#define TIMER_CCMR1_IC1F                (0xF << 4)
+#define TIMER_CCMR1_OC1PE               BIT(TIMER_CCMR1_OC1PE_BIT)
+#define TIMER_CCMR1_OC1FE               BIT(TIMER_CCMR1_OC1FE_BIT)
+#define TIMER_CCMR1_IC1PSC              (0x3 << 2)
+#define TIMER_CCMR1_CC1S                0x3
+#define TIMER_CCMR1_CC1S_OUTPUT         TIMER_CCMR_CCS_OUTPUT
+#define TIMER_CCMR1_CC1S_INPUT_TI1      TIMER_CCMR_CCS_INPUT_TI1
+#define TIMER_CCMR1_CC1S_INPUT_TI2      TIMER_CCMR_CCS_INPUT_TI2
+#define TIMER_CCMR1_CC1S_INPUT_TRC      TIMER_CCMR_CCS_INPUT_TRC
+
+/* Capture/compare mode register 2 (CCMR2) */
+
+#define TIMER_CCMR2_OC4CE_BIT           15
+#define TIMER_CCMR2_OC4PE_BIT           11
+#define TIMER_CCMR2_OC4FE_BIT           10
+#define TIMER_CCMR2_OC3CE_BIT           7
+#define TIMER_CCMR2_OC3PE_BIT           3
+#define TIMER_CCMR2_OC3FE_BIT           2
+
+#define TIMER_CCMR2_OC4CE               BIT(TIMER_CCMR2_OC4CE_BIT)
+#define TIMER_CCMR2_OC4M                (0x3 << 12)
+#define TIMER_CCMR2_IC2F                (0xF << 12)
+#define TIMER_CCMR2_OC4PE               BIT(TIMER_CCMR2_OC4PE_BIT)
+#define TIMER_CCMR2_OC4FE               BIT(TIMER_CCMR2_OC4FE_BIT)
+#define TIMER_CCMR2_IC2PSC              (0x3 << 10)
+#define TIMER_CCMR2_CC4S                (0x3 << 8)
+#define TIMER_CCMR1_CC4S_OUTPUT         (TIMER_CCMR_CCS_OUTPUT << 8)
+#define TIMER_CCMR1_CC4S_INPUT_TI1      (TIMER_CCMR_CCS_INPUT_TI1 << 8)
+#define TIMER_CCMR1_CC4S_INPUT_TI2      (TIMER_CCMR_CCS_INPUT_TI2 << 8)
+#define TIMER_CCMR1_CC4S_INPUT_TRC      (TIMER_CCMR_CCS_INPUT_TRC << 8)
+#define TIMER_CCMR2_OC3CE               BIT(TIMER_CCMR2_OC3CE_BIT)
+#define TIMER_CCMR2_OC3M                (0x3 << 4)
+#define TIMER_CCMR2_IC1F                (0xF << 4)
+#define TIMER_CCMR2_OC3PE               BIT(TIMER_CCMR2_OC3PE_BIT)
+#define TIMER_CCMR2_OC3FE               BIT(TIMER_CCMR2_OC3FE_BIT)
+#define TIMER_CCMR2_IC1PSC              (0x3 << 2)
+#define TIMER_CCMR2_CC3S                0x3
+#define TIMER_CCMR1_CC3S_OUTPUT         TIMER_CCMR_CCS_OUTPUT
+#define TIMER_CCMR1_CC3S_INPUT_TI1      TIMER_CCMR_CCS_INPUT_TI1
+#define TIMER_CCMR1_CC3S_INPUT_TI2      TIMER_CCMR_CCS_INPUT_TI2
+#define TIMER_CCMR1_CC3S_INPUT_TRC      TIMER_CCMR_CCS_INPUT_TRC
+
+/* Capture/compare enable register (CCER) */
+
+#define TIMER_CCER_CC4P_BIT             13
+#define TIMER_CCER_CC4E_BIT             12
+#define TIMER_CCER_CC3P_BIT             9
+#define TIMER_CCER_CC3E_BIT             8
+#define TIMER_CCER_CC2P_BIT             5
+#define TIMER_CCER_CC2E_BIT             4
+#define TIMER_CCER_CC1P_BIT             1
+#define TIMER_CCER_CC1E_BIT             0
+
+#define TIMER_CCER_CC4P                 BIT(TIMER_CCER_CC4P_BIT)
+#define TIMER_CCER_CC4E                 BIT(TIMER_CCER_CC4E_BIT)
+#define TIMER_CCER_CC3P                 BIT(TIMER_CCER_CC3P_BIT)
+#define TIMER_CCER_CC3E                 BIT(TIMER_CCER_CC3E_BIT)
+#define TIMER_CCER_CC2P                 BIT(TIMER_CCER_CC2P_BIT)
+#define TIMER_CCER_CC2E                 BIT(TIMER_CCER_CC2E_BIT)
+#define TIMER_CCER_CC1P                 BIT(TIMER_CCER_CC1P_BIT)
+#define TIMER_CCER_CC1E                 BIT(TIMER_CCER_CC1E_BIT)
+
+/* Break and dead-time register (BDTR) */
+
+#define TIMER_BDTR_MOE_BIT              15
+#define TIMER_BDTR_AOE_BIT              14
+#define TIMER_BDTR_BKP_BIT              13
+#define TIMER_BDTR_BKE_BIT              12
+#define TIMER_BDTR_OSSR_BIT             11
+#define TIMER_BDTR_OSSI_BIT             10
+
+#define TIMER_BDTR_MOE                  BIT(TIMER_BDTR_MOE_BIT)
+#define TIMER_BDTR_AOE                  BIT(TIMER_BDTR_AOE_BIT)
+#define TIMER_BDTR_BKP                  BIT(TIMER_BDTR_BKP_BIT)
+#define TIMER_BDTR_BKE                  BIT(TIMER_BDTR_BKE_BIT)
+#define TIMER_BDTR_OSSR                 BIT(TIMER_BDTR_OSSR_BIT)
+#define TIMER_BDTR_OSSI                 BIT(TIMER_BDTR_OSSI_BIT)
+#define TIMER_BDTR_LOCK                 (0x3 << 8)
+#define TIMER_BDTR_LOCK_OFF             (0x0 << 8)
+#define TIMER_BDTR_LOCK_LEVEL1          (0x1 << 8)
+#define TIMER_BDTR_LOCK_LEVEL2          (0x2 << 8)
+#define TIMER_BDTR_LOCK_LEVEL3          (0x3 << 8)
+#define TIMER_BDTR_DTG                  0xFF
+
+/* DMA control register (DCR) */
+
+#define TIMER_DCR_DBL                   (0x1F << 8)
+#define TIMER_DCR_DBL_1BYTE             (0x0 << 8)
+#define TIMER_DCR_DBL_2BYTE             (0x1 << 8)
+#define TIMER_DCR_DBL_3BYTE             (0x2 << 8)
+#define TIMER_DCR_DBL_4BYTE             (0x3 << 8)
+#define TIMER_DCR_DBL_5BYTE             (0x4 << 8)
+#define TIMER_DCR_DBL_6BYTE             (0x5 << 8)
+#define TIMER_DCR_DBL_7BYTE             (0x6 << 8)
+#define TIMER_DCR_DBL_8BYTE             (0x7 << 8)
+#define TIMER_DCR_DBL_9BYTE             (0x8 << 8)
+#define TIMER_DCR_DBL_10BYTE            (0x9 << 8)
+#define TIMER_DCR_DBL_11BYTE            (0xA << 8)
+#define TIMER_DCR_DBL_12BYTE            (0xB << 8)
+#define TIMER_DCR_DBL_13BYTE            (0xC << 8)
+#define TIMER_DCR_DBL_14BYTE            (0xD << 8)
+#define TIMER_DCR_DBL_15BYTE            (0xE << 8)
+#define TIMER_DCR_DBL_16BYTE            (0xF << 8)
+#define TIMER_DCR_DBL_17BYTE            (0x10 << 8)
+#define TIMER_DCR_DBL_18BYTE            (0x11 << 8)
+#define TIMER_DCR_DBA                   0x1F
+#define TIMER_DCR_DBA_CR1               0x0
+#define TIMER_DCR_DBA_CR2               0x1
+#define TIMER_DCR_DBA_SMCR              0x2
+#define TIMER_DCR_DBA_DIER              0x3
+#define TIMER_DCR_DBA_SR                0x4
+#define TIMER_DCR_DBA_EGR               0x5
+#define TIMER_DCR_DBA_CCMR1             0x6
+#define TIMER_DCR_DBA_CCMR2             0x7
+#define TIMER_DCR_DBA_CCER              0x8
+#define TIMER_DCR_DBA_CNT               0x9
+#define TIMER_DCR_DBA_PSC               0xA
+#define TIMER_DCR_DBA_ARR               0xB
+#define TIMER_DCR_DBA_RCR               0xC
+#define TIMER_DCR_DBA_CCR1              0xD
+#define TIMER_DCR_DBA_CCR2              0xE
+#define TIMER_DCR_DBA_CCR3              0xF
+#define TIMER_DCR_DBA_CCR4              0x10
+#define TIMER_DCR_DBA_BDTR              0x11
+#define TIMER_DCR_DBA_DCR               0x12
+#define TIMER_DCR_DBA_DMAR              0x13
+
+/*
+ * Convenience routines
+ */
+
+/**
+ * Used to configure the behavior of a timer channel.  Note that not
+ * all timers can be configured in every mode.
+ */
+/* TODO TIMER_PWM_CENTER_ALIGNED, TIMER_INPUT_CAPTURE, TIMER_ONE_PULSE */
+typedef enum timer_mode {
+    TIMER_DISABLED, /**< In this mode, the timer stops counting,
+                         channel interrupts are detached, and no state
+                         changes are output. */
+    TIMER_PWM, /**< PWM output mode. This is the default mode for pins
+                    after initialization. */
+    /* TIMER_PWM_CENTER_ALIGNED, /\**< Center-aligned PWM output mode. *\/ */
+    TIMER_OUTPUT_COMPARE, /**< In this mode, the timer counts from 0
+                               to its reload value repeatedly; every
+                               time the counter value reaches one of
+                               the channel compare values, the
+                               corresponding interrupt is fired. */
+    /* TIMER_INPUT_CAPTURE, /\**< In this mode, the timer can measure the */
+    /*                           pulse lengths of input signals. *\/ */
+    /* TIMER_ONE_PULSE /\**< In this mode, the timer can generate a single */
+    /*                      pulse on a GPIO pin for a specified amount of */
+    /*                      time. *\/ */
+} timer_mode;
+
+/** Timer channel numbers */
+typedef enum timer_channel {
+    TIMER_CH1 = 1, /**< Channel 1 */
+    TIMER_CH2 = 2, /**< Channel 2 */
+    TIMER_CH3 = 3, /**< Channel 3 */
+    TIMER_CH4 = 4  /**< Channel 4 */
+} timer_channel;
+
+/*
+ * Note: Don't require timer_channel arguments! We want to be able to say
+ *
+ * for (int channel = 1; channel <= 4; channel++) {
+ *    ...
+ * }
+ *
+ * without the compiler yelling at us.
+ */
+
+void timer_init(timer_dev *dev);
+void timer_disable(timer_dev *dev);
+void timer_set_mode(timer_dev *dev, uint8 channel, timer_mode mode);
+void timer_foreach(void (*fn)(timer_dev*));
+
+/**
+ * @brief Timer interrupt number.
+ *
+ * Not all timers support all of these values; see the descriptions
+ * for each value.
+ */
+typedef enum timer_interrupt_id {
+    TIMER_UPDATE_INTERRUPT, /**< Update interrupt, available on all timers. */
+    TIMER_CC1_INTERRUPT, /**< Capture/compare 1 interrupt, available
+                              on general and advanced timers only. */
+    TIMER_CC2_INTERRUPT, /**< Capture/compare 2 interrupt, general and
+                              advanced timers only. */
+    TIMER_CC3_INTERRUPT, /**< Capture/compare 3 interrupt, general and
+                              advanced timers only. */
+    TIMER_CC4_INTERRUPT, /**< Capture/compare 4 interrupt, general and
+                              advanced timers only. */
+    TIMER_COM_INTERRUPT, /**< COM interrupt, advanced timers only */
+    TIMER_TRG_INTERRUPT, /**< Trigger interrupt, general and advanced
+                              timers only */
+    TIMER_BREAK_INTERRUPT /**< Break interrupt, advanced timers only. */
+} timer_interrupt_id;
+
+void timer_attach_interrupt(timer_dev *dev,
+                            uint8 interrupt,
+                            voidFuncPtr handler);
+void timer_detach_interrupt(timer_dev *dev, uint8 interrupt);
+
+/**
+ * Initialize all timer devices on the chip.
+ */
+static inline void timer_init_all(void) {
+    timer_foreach(timer_init);
+}
+
+/**
+ * Disables all timers on the device.
+ */
+static inline void timer_disable_all(void) {
+    timer_foreach(timer_disable);
+}
+
+/**
+ * @brief Stop a timer's counter from changing.
+ *
+ * Does not affect the timer's mode or other settings.
+ *
+ * @param dev Device whose counter to pause.
+ */
+static inline void timer_pause(timer_dev *dev) {
+    *bb_perip(&(dev->regs).bas->CR1, TIMER_CR1_CEN_BIT) = 0;
+}
+
+/**
+ * @brief Start a timer's counter.
+ *
+ * Does not affect the timer's mode or other settings.
+ *
+ * @param dev Device whose counter to resume
+ */
+static inline void timer_resume(timer_dev *dev) {
+    *bb_perip(&(dev->regs).bas->CR1, TIMER_CR1_CEN_BIT) = 1;
+}
+
+/**
+ * @brief Returns the timer's counter value.
+ *
+ * This value is likely to be inaccurate if the counter is running
+ * with a low prescaler.
+ *
+ * @param dev Timer whose counter to return
+ */
+static inline uint16 timer_get_count(timer_dev *dev) {
+    return (uint16)(dev->regs).bas->CNT;
+}
+
+/**
+ * @brief Sets the counter value for the given timer.
+ * @param timer_num Timer whose counter to set
+ * @param value     New counter value
+ */
+static inline void timer_set_count(timer_dev *dev, uint16 value) {
+    (dev->regs).bas->CNT = value;
+}
+
+/**
+ * @brief Returns the given timer's prescaler.
+ *
+ * Note that if the timer's prescaler is set (e.g. via
+ * timer_set_prescaler() or accessing a TIMx_PSC register), the value
+ * returned by this function will reflect the new setting, but the
+ * timer's counter will only reflect the new prescaler at the next
+ * update event.
+ *
+ * @param dev Timer whose prescaler to return
+ * @see timer_generate_update()
+ */
+static inline uint16 timer_get_prescaler(timer_dev *dev) {
+    return (uint16)(dev->regs).bas->PSC;
+}
+
+/**
+ * @brief Set a timer's prescale value.
+ *
+ * The new value will not take effect until the next update event.
+ *
+ * @param dev Timer whose prescaler to set
+ * @param psc New prescaler value
+ * @see timer_generate_update()
+ */
+static inline void timer_set_prescaler(timer_dev *dev, uint16 psc) {
+    (dev->regs).bas->PSC = psc;
+}
+
+/**
+ * @brief Returns a timer's reload value.
+ * @param dev Timer whose reload value to return
+ */
+static inline uint16 timer_get_reload(timer_dev *dev) {
+    return (uint16)(dev->regs).bas->ARR;
+}
+
+/**
+ * @brief Set a timer's reload value.
+ * @param dev Timer whose reload value to set
+ * @param arr New reload value to use.  Takes effect at next update event.
+ * @see timer_generate_update()
+ */
+static inline void timer_set_reload(timer_dev *dev, uint16 arr) {
+    (dev->regs).bas->ARR = arr;
+}
+
+/**
+ * @brief Get the compare value for the given timer channel.
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @param channel Channel whose compare value to get.
+ */
+static inline uint16 timer_get_compare(timer_dev *dev, uint8 channel) {
+    __io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
+    return *ccr;
+}
+
+/**
+ * @brief Set the compare value for the given timer channel.
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @param channel Channel whose compare value to set.
+ * @param value   New compare value.
+ */
+static inline void timer_set_compare(timer_dev *dev,
+                                     uint8 channel,
+                                     uint16 value) {
+    __io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
+    *ccr = value;
+}
+
+/**
+ * @brief Generate an update event for the given timer.
+ *
+ * Normally, this will cause the prescaler and auto-reload values in
+ * the PSC and ARR registers to take immediate effect.  However, this
+ * function will do nothing if the UDIS bit is set in the timer's CR1
+ * register (UDIS is cleared by default).
+ *
+ * @param dev Timer device to generate an update for.
+ */
+static inline void timer_generate_update(timer_dev *dev) {
+    *bb_perip(&(dev->regs).bas->EGR, TIMER_EGR_UG_BIT) = 1;
+}
+
+/**
+ * @brief Enable a timer's trigger DMA request
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL
+ */
+static inline void timer_trigger_dma_enable_request(timer_dev *dev) {
+    *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 1;
+}
+
+/**
+ * @brief Disable a timer's trigger DMA request
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL
+ */
+static inline void timer_trigger_dma_disable_request(timer_dev *dev) {
+    *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 0;
+}
+
+/**
+ * @brief Enable a timer channel's DMA request.
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL
+ * @param channel Channel whose DMA request to enable.
+ */
+static inline void timer_dma_enable_request(timer_dev *dev, uint8 channel) {
+    *bb_perip(&(dev->regs).gen->DIER, channel + 8) = 1;
+}
+
+/**
+ * @brief Disable a timer channel's DMA request.
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @param channel Channel whose DMA request to disable.
+ */
+static inline void timer_dma_disable_request(timer_dev *dev, uint8 channel) {
+    *bb_perip(&(dev->regs).gen->DIER, channel + 8) = 0;
+}
+
+/**
+ * @brief Enable a timer interrupt.
+ * @param dev Timer device.
+ * @param interrupt Interrupt number to enable; this may be any
+ *                  timer_interrupt_id value appropriate for the timer.
+ * @see timer_interrupt_id
+ * @see timer_channel
+ */
+static inline void timer_enable_interrupt(timer_dev *dev, uint8 interrupt) {
+    *bb_perip(&(dev->regs).adv->DIER, interrupt) = 1;
+}
+
+/**
+ * @brief Disable a timer interrupt.
+ * @param dev Timer device.
+ * @param interrupt Interrupt number to disable; this may be any
+ *                  timer_interrupt_id value appropriate for the timer.
+ * @see timer_interrupt_id
+ * @see timer_channel
+ */
+static inline void timer_disable_interrupt(timer_dev *dev, uint8 interrupt) {
+    *bb_perip(&(dev->regs).adv->DIER, interrupt) = 0;
+}
+
+/**
+ * @brief Enable a timer channel's capture/compare signal.
+ *
+ * If the channel is configured as output, the corresponding output
+ * compare signal will be output on the corresponding output pin.  If
+ * the channel is configured as input, enables capture of the counter
+ * value into the input capture/compare register.
+ *
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @param channel Channel to enable, from 1 to 4.
+ */
+static inline void timer_cc_enable(timer_dev *dev, uint8 channel) {
+    *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1)) = 1;
+}
+
+/**
+ * @brief Disable a timer channel's output compare or input capture signal.
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @param channel Channel to disable, from 1 to 4.
+ * @see timer_cc_enable()
+ */
+static inline void timer_cc_disable(timer_dev *dev, uint8 channel) {
+    *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1)) = 0;
+}
+
+/**
+ * @brief Get a channel's capture/compare output polarity
+ * @brief dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @brief channel Channel whose capture/compare output polarity to get.
+ * @return Polarity, either 0 or 1.
+ * @see timer_cc_set_polarity()
+ */
+static inline uint8 timer_cc_get_polarity(timer_dev *dev, uint8 channel) {
+    return *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1) + 1);
+}
+
+/**
+ * @brief Set a timer channel's capture/compare output polarity.
+ *
+ * If the timer channel is configured as output: polarity == 0 means
+ * the output channel will be active high; polarity == 1 means active
+ * low.
+ *
+ * If the timer channel is configured as input: polarity == 0 means
+ * capture is done on the rising edge of ICn; when used as an external
+ * trigger, ICn is non-inverted.  polarity == 1 means capture is done
+ * on the falling edge of ICn; when used as an external trigger, ICn
+ * is inverted.
+ *
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @param channel Channel whose capture/compare output polarity to set.
+ * @param pol New polarity, 0 or 1.
+ */
+static inline void timer_cc_set_polarity(timer_dev *dev,
+                                         uint8 channel,
+                                         uint8 pol) {
+    *bb_perip(&(dev->regs).gen->CCER, 4 * (channel - 1) + 1) = pol;
+}
+
+/**
+ * @brief Get a timer's DMA burst length.
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @return Number of bytes to be transferred per DMA request, from 1 to 18.
+ */
+static inline uint8 timer_get_dma_burst_length(timer_dev *dev) {
+    uint32 dbl = ((dev->regs).gen->DCR & TIMER_DCR_DBL) >> 8;
+    return dbl + 1;             /* 0 means 1 byte, etc. */
+}
+
+/**
+ * @brief Set a timer's DMA burst length.
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @param length DMA burst length; i.e., number of bytes to transfer
+ *               per DMA request, from 1 to 18.
+ */
+static inline void timer_set_dma_burst_length(timer_dev *dev, uint8 length) {
+    uint32 tmp = (dev->regs).gen->DCR;
+    tmp &= ~TIMER_DCR_DBL;
+    tmp |= (length << 8) - 1;
+    (dev->regs).gen->DCR = tmp;
+}
+
+/**
+ * @brief Timer DMA base address.
+ *
+ * Defines the base address for DMA transfers.
+ */
+typedef enum timer_dma_base_address {
+    TIMER_DMA_BASE_CR1 = TIMER_DCR_DBA_CR1, /**< Base is control register 1 */
+    TIMER_DMA_BASE_CR2 = TIMER_DCR_DBA_CR2, /**< Base is control register 2 */
+    TIMER_DMA_BASE_SMCR = TIMER_DCR_DBA_SMCR, /**< Base is slave mode
+                                                   control register */
+    TIMER_DMA_BASE_DIER = TIMER_DCR_DBA_DIER, /**< Base is DMA interrupt enable
+                                                   register */
+    TIMER_DMA_BASE_SR = TIMER_DCR_DBA_SR, /**< Base is status register */
+    TIMER_DMA_BASE_EGR = TIMER_DCR_DBA_EGR, /**< Base is event generation
+                                                 register */
+    TIMER_DMA_BASE_CCMR1 = TIMER_DCR_DBA_CCMR1, /**< Base is capture/compare
+                                                     mode register 1 */
+    TIMER_DMA_BASE_CCMR2 = TIMER_DCR_DBA_CCMR2, /**< Base is capture/compare
+                                                     mode register 2 */
+    TIMER_DMA_BASE_CCER = TIMER_DCR_DBA_CCER,   /**< Base is capture/compare
+                                                     enable register */
+    TIMER_DMA_BASE_CNT = TIMER_DCR_DBA_CNT,     /**< Base is counter */
+    TIMER_DMA_BASE_PSC = TIMER_DCR_DBA_PSC,     /**< Base is prescaler */
+    TIMER_DMA_BASE_ARR = TIMER_DCR_DBA_ARR,     /**< Base is auto-reload
+                                                     register */
+    TIMER_DMA_BASE_RCR = TIMER_DCR_DBA_RCR,     /**< Base is repetition
+                                                     counter register */
+    TIMER_DMA_BASE_CCR1 = TIMER_DCR_DBA_CCR1,   /**< Base is capture/compare
+                                                     register 1 */
+    TIMER_DMA_BASE_CCR2 = TIMER_DCR_DBA_CCR2,   /**< Base is capture/compare
+                                                     register 2 */
+    TIMER_DMA_BASE_CCR3 = TIMER_DCR_DBA_CCR3,   /**< Base is capture/compare
+                                                     register 3 */
+    TIMER_DMA_BASE_CCR4 = TIMER_DCR_DBA_CCR4,   /**< Base is capture/compare
+                                                     register 4 */
+    TIMER_DMA_BASE_BDTR = TIMER_DCR_DBA_BDTR,   /**< Base is break and
+                                                     dead-time register */
+    TIMER_DMA_BASE_DCR = TIMER_DCR_DBA_DCR,     /**< Base is DMA control
+                                                     register */
+    TIMER_DMA_BASE_DMAR = TIMER_DCR_DBA_DMAR    /**< Base is DMA address for
+                                                     full transfer */
+} timer_dma_base_address;
+
+/**
+ * @brief Get the timer's DMA base address.
+ *
+ * Some restrictions apply; see ST RM0008.
+ *
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @return DMA base address
+ */
+static inline timer_dma_base_address
+timer_get_dma_base_address(timer_dev *dev) {
+    uint32 dcr = (dev->regs).gen->DCR;
+    return (timer_dma_base_address)(dcr & TIMER_DCR_DBA);
+}
+
+/**
+ * @brief Set the timer's DMA base address.
+ *
+ * Some restrictions apply; see ST RM0008.
+ *
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @param dma_base DMA base address.
+ */
+static inline void
+timer_set_dma_base_address(timer_dev *dev, timer_dma_base_address dma_base) {
+    uint32 tmp = (dev->regs).gen->DCR;
+    tmp &= ~TIMER_DCR_DBA;
+    tmp |= dma_base;
+    (dev->regs).gen->DCR = tmp;
+}
+
+/**
+ * Timer output compare modes.
+ */
+typedef enum timer_oc_mode {
+    TIMER_OC_MODE_FROZEN = 0 << 4, /**< Frozen: comparison between output
+                                      compare register and counter has no
+                                      effect on the outputs. */
+    TIMER_OC_MODE_ACTIVE_ON_MATCH = 1 << 4, /**< OCxREF signal is forced
+                                               high when the count matches
+                                               the channel capture/compare
+                                               register. */
+    TIMER_OC_MODE_INACTIVE_ON_MATCH = 2 << 4, /**< OCxREF signal is forced
+                                                 low when the counter matches
+                                                 the channel capture/compare
+                                                 register. */
+    TIMER_OC_MODE_TOGGLE = 3 << 4, /**< OCxREF toggles when counter
+                                      matches the cannel capture/compare
+                                      register. */
+    TIMER_OC_MODE_FORCE_INACTIVE = 4 << 4, /**< OCxREF is forced low. */
+    TIMER_OC_MODE_FORCE_ACTIVE = 5 << 4, /**< OCxREF is forced high. */
+    TIMER_OC_MODE_PWM_1 = 6 << 4, /**< PWM mode 1.  In upcounting, channel is
+                                     active as long as count is less than
+                                     channel capture/compare register, else
+                                     inactive.  In downcounting, channel is
+                                     inactive as long as count exceeds
+                                     capture/compare register, else
+                                     active. */
+    TIMER_OC_MODE_PWM_2 = 7 << 4  /**< PWM mode 2. In upcounting, channel is
+                                     inactive as long as count is less than
+                                     capture/compare register, else active.
+                                     In downcounting, channel is active as
+                                     long as count exceeds capture/compare
+                                     register, else inactive. */
+} timer_oc_mode;
+
+/**
+ * Timer output compare mode flags.
+ * @see timer_oc_set_mode()
+ */
+typedef enum timer_oc_mode_flags {
+    TIMER_OC_CE = BIT(7),       /**< Output compare clear enable. */
+    TIMER_OC_PE = BIT(3),       /**< Output compare preload enable. */
+    TIMER_OC_FE = BIT(2)        /**< Output compare fast enable. */
+} timer_oc_mode_flags;
+
+/**
+ * @brief Configure a channel's output compare mode.
+ *
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL.
+ * @param channel Channel to configure in output compare mode.
+ * @param flags OR of timer_oc_mode_flags.
+ * @see timer_oc_mode
+ * @see timer_oc_mode_flags
+ */
+static inline void timer_oc_set_mode(timer_dev *dev,
+                                     uint8 channel,
+                                     timer_oc_mode mode,
+                                     uint8 flags) {
+    uint8 bit0 = channel & 1;
+    uint8 bit1 = (channel >> 1) & 1;
+    /* channel == 1,2 -> CCMR1; channel == 3,4 -> CCMR2 */
+    __io uint32 *ccmr = &(dev->regs).gen->CCMR1 + bit1;
+    /* channel == 1,3 -> shift = 0, channel == 2,4 -> shift = 8 */
+    uint8 shift = 8 * (1 - bit0);
+
+    uint32 tmp = *ccmr;
+    tmp &= ~(0xFF << shift);
+    tmp |= (mode | flags | TIMER_CCMR_CCS_OUTPUT) << shift;
+    *ccmr = tmp;
+}
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif
diff --git a/libmaple/timers.c b/libmaple/timers.c
deleted file mode 100644
index c561d39..0000000
--- a/libmaple/timers.c
+++ /dev/null
@@ -1,526 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *****************************************************************************/
-
-/**
- * @brief General timer routines
- */
-
-/* TODO: actually support timer5 and timer8 */
-
-#include "libmaple.h"
-#include "rcc.h"
-#include "nvic.h"
-#include "timers.h"
-
-/* Timer descriptor table */
-struct timer_dev timer_dev_table[] = {
-    [TIMER1] = {
-        .base = (timer_port*)TIMER1_BASE,
-        .rcc_dev_num = RCC_TIMER1,
-        .nvic_dev_num = NVIC_TIMER1
-    },
-    [TIMER2] = {
-        .base = (timer_port*)TIMER2_BASE,
-        .rcc_dev_num = RCC_TIMER2,
-        .nvic_dev_num = NVIC_TIMER2
-    },
-    [TIMER3] = {
-        .base = (timer_port*)TIMER3_BASE,
-        .rcc_dev_num = RCC_TIMER3,
-        .nvic_dev_num = NVIC_TIMER3
-    },
-    [TIMER4] = {
-        .base = (timer_port*)TIMER4_BASE,
-        .rcc_dev_num = RCC_TIMER4,
-        .nvic_dev_num = NVIC_TIMER4
-    },
-#ifdef STM32_HIGH_DENSITY
-    /* High density devices only (eg, Maple Native) */
-    [TIMER5] = {
-        .base = (timer_port*)TIMER5_BASE,
-        .rcc_dev_num = RCC_TIMER5,
-        .nvic_dev_num = NVIC_TIMER5
-    },
-    [TIMER8] = {
-        .base = (timer_port*)TIMER8_BASE,
-        .rcc_dev_num = RCC_TIMER8,
-        .nvic_dev_num = NVIC_TIMER8
-    },
-#endif
-};
-
-/* This function should probably be rewriten to take (timer_num, mode)
- * and have prescaler set elsewhere. The mode can be passed through to
- * set_mode at the end */
-void timer_init(timer_dev_num timer_num, uint16 prescale) {
-    /* TODO: doesn't catch 6+7 */
-
-    timer_port *timer = timer_dev_table[timer_num].base;
-    uint8 is_advanced = 0;
-
-    if (timer_num == TIMER1) {
-        is_advanced = 1;
-    }
-#ifdef STM32_HIGH_DENSITY
-    if (timer_num == TIMER8) {
-        is_advanced = 1;
-    }
-#endif
-
-    rcc_clk_enable(timer_dev_table[timer_num].rcc_dev_num);
-
-    timer->CR1 = ARPE;        // No clock division
-                              // Do not buffer auto-reload preload
-                              // Edge aligned
-                              // Upcounter
-                              // Do not stop counter at update event
-                              // Update events enabled (etc, see bits [1:2])
-                              // Counter disabled for now
-
-    timer->PSC = prescale;    // Prescaling by prescale (duh)
-    timer->ARR = 0xFFFF;      // Max reload cont
-
-    /* initialize all the channels to 50% duty cycle,
-     * TODO: none of them actually get output unless the gpio pin
-     * is set, this will probably consume a bit more power but
-     * we'll worry about that later. */
-    timer->CCR1   = 0x8FFF;     // PWM start value
-    timer->CCMR1 |= 0x68;       // PWM mode 1, enable preload register.
-
-    timer->CCR2   = 0x8FFF;     // PWM start value
-    timer->CCMR1 |= (0x68 << 8);// PWM mode 1, enable preload register.
-
-    timer->CCR3   = 0x8FFF;     // PWM start value
-    timer->CCMR2 |= 0x68;       // PWM mode 1, enable preload register.
-
-    timer->CCR4   = 0x8FFF;     // PWM start value
-    timer->CCMR2 |= (0x68 << 8);// PWM mode 1, enable preload register.
-
-    /* Advanced timer?  */
-    if (is_advanced) {
-        timer->BDTR = 0x8000;     // moe enable
-    }
-
-    timer->SR = 0;            // clear it
-    timer->DIER = 0;          // disable update interrupt
-    timer->EGR  = 1;          // Initialize update event and shadow registers
-    timer->CR1  |= 1;         // Enable timer
-}
-
-/* Stops the counter; the mode and settings are not modified */
-void timer_pause(timer_dev_num timer_num) {
-    timer_port *timer = timer_dev_table[timer_num].base;
-
-    timer->CR1 &= ~(0x0001);    // CEN
-}
-
-/* Starts the counter; the mode and settings are not modified */
-void timer_resume(timer_dev_num timer_num) {
-    timer_port *timer = timer_dev_table[timer_num].base;
-
-    timer->CR1 |= 0x0001;       // CEN
-}
-
-/* Returns the current timer counter value. Probably very inaccurate
- * if the counter is running with a low prescaler. */
-uint16 timer_get_count(timer_dev_num timer_num) {
-    timer_port *timer = timer_dev_table[timer_num].base;
-
-    return timer->CNT;
-}
-
-/* This function sets the counter value via register for the specified
- * timer.  Can't think of specific usecases except for resetting to
- * zero but it's easy to implement and allows for "creative"
- * programming */
-void timer_set_count(timer_dev_num timer_num, uint16 value) {
-    timer_port *timer = timer_dev_table[timer_num].base;
-
-    timer->CNT = value;
-}
-
-/* Get the prescaler buffer value (remember, the actual prescaler
- * doesn't get set until an update event). */
-uint16 timer_get_prescaler(timer_dev_num timer_num) {
-    timer_port *timer = timer_dev_table[timer_num].base;
-    return timer->PSC;
-}
-
-/* Sets the prescaler */
-void timer_set_prescaler(timer_dev_num timer_num, uint16 prescale) {
-    timer_port *timer = timer_dev_table[timer_num].base;
-
-    timer->PSC = prescale;
-}
-
-/* Get the reload value for the entire timer. */
-uint16 timer_get_reload(timer_dev_num timer_num) {
-    timer_port *timer = timer_dev_table[timer_num].base;
-    return timer->ARR;
-}
-
-/* This sets the "reload" or "overflow" value for the entire timer. We
- * should probably settle on either "reload" or "overflow" to prevent
- * confusion? */
-void timer_set_reload(timer_dev_num timer_num, uint16 max_reload) {
-    timer_port *timer = timer_dev_table[timer_num].base;
-
-    timer->ARR = max_reload;
-}
-
-/* This quickly disables all 4 timers, presumably as part of a system shutdown
- * or similar to prevent interrupts and PWM output without 16 seperate function
- * calls to timer_set_mode */
-void timer_disable_all(void) {
-    timer_port *timer;
-#ifdef STM32_HIGH_DENSITY
-    timer_port *timers[6] = { (timer_port*)TIMER1_BASE,
-                              (timer_port*)TIMER2_BASE,
-                              (timer_port*)TIMER3_BASE,
-                              (timer_port*)TIMER4_BASE,
-                              (timer_port*)TIMER5_BASE,
-                              (timer_port*)TIMER8_BASE,
-    };
-    uint8 i;
-    for (i = 0; i < 6; i++) {
-        timer = timers[i];
-        timer->CR1 = 0;
-        timer->CCER = 0;
-    }
-#else
-    timer_port *timers[4] = { (timer_port*)TIMER1_BASE,
-                              (timer_port*)TIMER2_BASE,
-                              (timer_port*)TIMER3_BASE,
-                              (timer_port*)TIMER4_BASE,
-    };
-    uint8 i;
-    for (i = 0; i < 4; i++) {
-        timer = timers[i];
-        timer->CR1 = 0;
-        timer->CCER = 0;
-    }
-#endif
-}
-
-/* Sets the mode of individual timer channels, including a DISABLE mode */
-void timer_set_mode(timer_dev_num timer_num, uint8 channel, TimerMode mode) {
-    timer_port *timer = timer_dev_table[timer_num].base;
-    ASSERT(channel >= 1);
-
-    switch(mode) {
-    case TIMER_DISABLED:
-        /* Disable the channel
-         * Disable any interrupt
-         * Clear interrupt SR? (TODO) */
-        timer->DIER &= ~(1 << channel); // 1-indexed compare nums
-        timer_detach_interrupt(timer_num, channel);
-        timer->CCER &= ~(1 << (4*(channel - 1))); // 0-indexed
-        break;
-    case TIMER_PWM:
-        /* Set CCMR mode
-         * Keep existing reload value
-         * Disable any interrupt
-         * Clear interrupt SR? (TODO)
-         * Enable channel */
-        timer->DIER &= ~(1 << channel); // 1-indexed compare nums
-        switch (channel) {
-        case 1:
-            timer->CCMR1 &= ~(0xFF);
-            timer->CCMR1 |= 0x68;       // PWM mode 1, enable preload register.
-            break;
-        case 2:
-            timer->CCMR1 &= ~(0xFF00);
-            timer->CCMR1 |= (0x68 << 8);// PWM mode 1, enable preload register.
-            break;
-        case 3:
-            timer->CCMR2 &= ~(0xFF);
-            timer->CCMR2 |= 0x68;       // PWM mode 1, enable preload register.
-            break;
-        case 4:
-            timer->CCMR2 &= ~(0xFF00);
-            timer->CCMR2 |= (0x68 << 8);// PWM mode 1, enable preload register.
-            break;
-        default:
-            ASSERT(0);
-        }
-        timer->CCER |= (1 << (4*(channel - 1))); // Enable
-        break;
-    case TIMER_OUTPUTCOMPARE:
-        /* Set CCMR mode
-         * Keep existing reload value
-         * Don't modify interrupt (needs to be attached to enable)
-         * Clear interrupt SR? (TODO)
-         * Enable channel */
-        switch (channel) {
-        case 1:
-            timer->CCMR1 &= ~(0xFF);
-            timer->CCMR1 |= 0x0010; // PWM mode 1, enable preload register.
-            break;
-        case 2:
-            timer->CCMR1 &= ~(0xFF00);
-            timer->CCMR1 |= 0x1000; // PWM mode 1, enable preload register.
-            break;
-        case 3:
-            timer->CCMR2 &= ~(0xFF);
-            timer->CCMR2 |= 0x0010; // PWM mode 1, enable preload register.
-            break;
-        case 4:
-            timer->CCMR2 &= ~(0xFF00);
-            timer->CCMR2 |= 0x1000; // PWM mode 1, enable preload register.
-            break;
-        default:
-            ASSERT(0);
-        }
-        timer->CCER |= (1 << (4*(channel - 1))); // Enable
-        break;
-    default:
-        ASSERT(0);
-    }
-}
-
-uint16 timer_get_compare_value(timer_dev_num timer_num, uint8 channel_num) {
-    /* faster: just read TIMERx_CHy_CCR (see timers.h) */
-    ASSERT(channel_num > 0 && channel_num <= 4);
-    timer_port *timer = timer_dev_table[timer_num].base;
-    switch(channel_num) {
-    case 1:
-        return timer->CCR1;
-    case 2:
-        return timer->CCR2;
-    case 3:
-        return timer->CCR3;
-    case 4:
-        return timer->CCR4;
-    default:                    /* in case ASSERT is disabled */
-        return 0;
-    }
-}
-
-/* This sets the compare value (aka the trigger) for a given timer
- * channel */
-void timer_set_compare_value(timer_dev_num timer_num,
-                             uint8 channel_num,
-                             uint16 value) {
-    ASSERT(channel_num > 0 && channel_num <= 4);
-
-    /* The faster version of this function is the inline
-       timer_pwm_write_ccr */
-    timer_port *timer = timer_dev_table[timer_num].base;
-
-    switch(channel_num) {
-    case 1:
-        timer->CCR1 = value;
-        break;
-    case 2:
-        timer->CCR2 = value;
-        break;
-    case 3:
-        timer->CCR3 = value;
-        break;
-    case 4:
-        timer->CCR4 = value;
-        break;
-    }
-}
-
-/* Stores a pointer to the passed usercode interrupt function and configures
- * the actual ISR so that it will actually be called */
-void timer_attach_interrupt(timer_dev_num timer_num,
-                            uint8 compare_num,
-                            voidFuncPtr handler) {
-    ASSERT(compare_num > 0 && compare_num <= 4);
-
-    timer_port *timer = timer_dev_table[timer_num].base;
-
-    timer_dev_table[timer_num].handlers[compare_num-1] = handler;
-    timer->DIER |= (1 << compare_num); // 1-indexed compare nums
-    nvic_irq_enable(timer_dev_table[timer_num].nvic_dev_num);
-}
-
-void timer_detach_interrupt(timer_dev_num timer_num, uint8 compare_num) {
-    ASSERT(compare_num > 0 && compare_num <= 4);
-
-    timer_port *timer = timer_dev_table[timer_num].base;
-
-    timer_dev_table[timer_num].handlers[compare_num-1] = 0;
-    timer->DIER &= ~(1 << compare_num); // 1-indexed compare nums
-}
-
-void timer_generate_update(timer_dev_num timer_num) {
-    /* cause update event by setting UG bit in EGR.  updates prescaler
-       ratio etc. */
-    timer_port *timer = timer_dev_table[timer_num].base;
-    timer->EGR |= 0x1;
-}
-
-/* The following are the actual interrupt handlers; 1 for each timer which must
- * determine which actual compare value (aka channel) was triggered.
- *
- * These ISRs get called when the timer interrupt is enabled, the
- * timer is running, and the timer count equals any of the CCR
- * registers /or/ has overflowed.
- *
- * This is a rather long implementation... */
-void __irq_tim1_cc(void) {
-    timer_port *timer = (timer_port*)TIMER1_BASE;
-    uint16 sr_buffer;
-    sr_buffer = timer->SR;
-
-    /* Simply switch/case-ing here doesn't work because multiple
-     * CC flags may be high. */
-    if(sr_buffer & 0x10){ // CC4 flag
-        timer->SR &= ~(0x10);
-        if(timer_dev_table[TIMER1].handlers[3]) {
-            timer_dev_table[TIMER1].handlers[3]();
-        }
-    }
-    if(sr_buffer & 0x8){ // CC3 flag
-        timer->SR &= ~(0x8);
-        if(timer_dev_table[TIMER1].handlers[2]) {
-            timer_dev_table[TIMER1].handlers[2]();
-        }
-    }
-    if(sr_buffer & 0x4){ // CC2 flag
-        timer->SR &= ~(0x4);
-        if(timer_dev_table[TIMER1].handlers[1]) {
-            timer_dev_table[TIMER1].handlers[1]();
-        }
-    }
-    if(sr_buffer & 0x2){ // CC1 flag
-        timer->SR &= ~(0x2);
-        if(timer_dev_table[TIMER1].handlers[0]) {
-            timer_dev_table[TIMER1].handlers[0]();
-        }
-    }
-    if(sr_buffer & 0x1){ // Update flag
-        timer->SR &= ~(0x1);
-        //timer->EGR  = 1;
-    }
-}
-void __irq_tim2(void) {
-    /* This is a rather long implementation... */
-    timer_port *timer = (timer_port*)TIMER2_BASE;
-    uint16 sr_buffer;
-    sr_buffer = timer->SR;
-
-    if(sr_buffer & 0x10){ // CC4 flag
-        timer->SR &= ~(0x10);
-        if(timer_dev_table[TIMER2].handlers[3]) {
-            timer_dev_table[TIMER2].handlers[3]();
-        }
-    }
-    if(sr_buffer & 0x8){ // CC3 flag
-        timer->SR &= ~(0x8);
-        if(timer_dev_table[TIMER2].handlers[2]) {
-            timer_dev_table[TIMER2].handlers[2]();
-        }
-    }
-    if(sr_buffer & 0x4){ // CC2 flag
-        timer->SR &= ~(0x4);
-        if(timer_dev_table[TIMER2].handlers[1]) {
-            timer_dev_table[TIMER2].handlers[1]();
-        }
-    }
-    if(sr_buffer & 0x2){ // CC1 flag
-        timer->SR &= ~(0x2);
-        if(timer_dev_table[TIMER2].handlers[0]) {
-            timer_dev_table[TIMER2].handlers[0]();
-        }
-    }
-    if(sr_buffer & 0x1){ // Update flag
-        timer->SR &= ~(0x1);
-        //timer->EGR  = 1;
-    }
-}
-void __irq_tim3(void) {
-    /* This is a rather long implementation... */
-    timer_port *timer = (timer_port*)TIMER3_BASE;
-    uint16 sr_buffer;
-    sr_buffer = timer->SR;
-
-    if(sr_buffer & 0x10){ // CC4 flag
-        timer->SR &= ~(0x10);
-        if(timer_dev_table[TIMER3].handlers[3]) {
-            timer_dev_table[TIMER3].handlers[3]();
-        }
-    }
-    if(sr_buffer & 0x8){ // CC3 flag
-        timer->SR &= ~(0x8);
-        if(timer_dev_table[TIMER3].handlers[2]) {
-            timer_dev_table[TIMER3].handlers[2]();
-        }
-    }
-    if(sr_buffer & 0x4){ // CC2 flag
-        timer->SR &= ~(0x4);
-        if(timer_dev_table[TIMER3].handlers[1]) {
-            timer_dev_table[TIMER3].handlers[1]();
-        }
-    }
-    if(sr_buffer & 0x2){ // CC1 flag
-        timer->SR &= ~(0x2);
-        if(timer_dev_table[TIMER3].handlers[0]) {
-            timer_dev_table[TIMER3].handlers[0]();
-        }
-    }
-    if(sr_buffer & 0x1){ // Update flag
-        timer->SR &= ~(0x1);
-        //timer->EGR  = 1;
-    }
-}
-
-void __irq_tim4(void) {
-    /* This is a rather long implementation... */
-    timer_port*timer = (timer_port*)TIMER4_BASE;
-    uint16 sr_buffer;
-    sr_buffer = timer->SR;
-
-    if(sr_buffer & 0x10){ // CC4 flag
-        timer->SR &= ~(0x10);
-        if(timer_dev_table[TIMER4].handlers[3]) {
-            timer_dev_table[TIMER4].handlers[3]();
-        }
-    }
-    if(sr_buffer & 0x8){ // CC3 flag
-        timer->SR &= ~(0x8);
-        if(timer_dev_table[TIMER4].handlers[2]) {
-            timer_dev_table[TIMER4].handlers[2]();
-        }
-    }
-    if(sr_buffer & 0x4){ // CC2 flag
-        timer->SR &= ~(0x4);
-        if(timer_dev_table[TIMER4].handlers[1]) {
-            timer_dev_table[TIMER4].handlers[1]();
-        }
-    }
-    if(sr_buffer & 0x2){ // CC1 flag
-        timer->SR &= ~(0x2);
-        if(timer_dev_table[TIMER4].handlers[0]) {
-            timer_dev_table[TIMER4].handlers[0]();
-        }
-    }
-    if(sr_buffer & 0x1){ // Update flag
-        timer->SR &= ~(0x1);
-        //timer->EGR  = 1;
-    }
-}
diff --git a/libmaple/timers.h b/libmaple/timers.h
deleted file mode 100644
index 1f6afcd..0000000
--- a/libmaple/timers.h
+++ /dev/null
@@ -1,435 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file timers.h
- *
- * @brief Timer prototypes and various definitions
- */
-
-/* Note to self:
- * The timer clock frequencies are automatically fixed by hardware.
- * There are two cases:
- *     1.  if the APB prescaler is 1, the timer clock frequencies are
- *         set to the same frequency as that of the APB domain to which
- *         the timers are connected.
- *     2.  otherwise, they are set to twice (x2) the frequency of the
- *         APB domain to which the timers are connected.
- * See stm32 manual, 77/995
- *
- * hence, 72 mhz timers
- */
-
-/* Maple Timer channels:
- * Timer        Maple Pin               STM32 Pin     Type
- * TIM1_CH1     D6                      PA8           Advanced
- * TIM1_CH2     D7                      PA9           Advanced
- * TIM1_CH3     D8                      PA10          Advanced
- *
- * TIM2_CH1     D2                      PA0
- * TIM2_CH2     D3                      PA1
- * TIM2_CH3     D1                      PA2
- * TIM2_CH4     D0                      PA3
- *
- * TIM3_CH1     D12                     PA6
- * TIM3_CH2     D11                     PA7
- * TIM3_CH3     EXT7                    PB0
- * TIM3_CH4     EXT8                    PB1
- *
- * TIM4_CH1     EXT5                    PB6
- * TIM4_CH1     EXT9                    PB7
- * TIM4_CH1     EXT15                   PB8
- * TIM4_CH1     EXT4                    PB9
- *
- * Not supported:
- * TIM1_CH4    USBDM, not available     PA11          Advanced
- * TIM1_CH1_N  EXT12                    PB13
- * TIM1_CH2_N  EXT13                    PB14
- * TIM1_CH3_N  EXT14                    PB15
- * */
-
-/* I don't like the Arduino API for dealing with pin modes.
- * How about...
- *
- * pinMode(digitalPin, PWM);
- * pwmWrite(digitalPin) */
-
-#ifndef _TIMERS_H_
-#define _TIMERS_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-typedef volatile uint16* TimerCCR;
-
-#define TIMER1_BASE        0x40012C00
-#define TIMER2_BASE        0x40000000
-#define TIMER3_BASE        0x40000400
-#define TIMER4_BASE        0x40000800
-#define TIMER5_BASE        0x40000C00   // High-density devices only
-#define TIMER6_BASE        0x40001000   // High-density devices only
-#define TIMER7_BASE        0x40001400   // High-density devices only
-#define TIMER8_BASE        0x40013400   // High-density devices only
-
-#define ARPE               BIT(7)       // Auto-reload preload enable
-#define NOT_A_TIMER        0
-
-#define TIMER_CCR(NUM,CHAN)  (TIMER ## NUM ## _CH ## CHAN ## _CRR)
-
-/* Timers 1-4 are present on the entire STM32 line. */
-
-#define TIMER1_CH1_CCR     ((TimerCCR)(TIMER1_BASE + 0x34))
-#define TIMER1_CH2_CCR     ((TimerCCR)(TIMER1_BASE + 0x38))
-#define TIMER1_CH3_CCR     ((TimerCCR)(TIMER1_BASE + 0x3C))
-#define TIMER1_CH4_CCR     ((TimerCCR)(TIMER1_BASE + 0x40))
-
-#define TIMER2_CH1_CCR     ((TimerCCR)(TIMER2_BASE + 0x34))
-#define TIMER2_CH2_CCR     ((TimerCCR)(TIMER2_BASE + 0x38))
-#define TIMER2_CH3_CCR     ((TimerCCR)(TIMER2_BASE + 0x3C))
-#define TIMER2_CH4_CCR     ((TimerCCR)(TIMER2_BASE + 0x40))
-
-#define TIMER3_CH1_CCR     ((TimerCCR)(TIMER3_BASE + 0x34))
-#define TIMER3_CH2_CCR     ((TimerCCR)(TIMER3_BASE + 0x38))
-#define TIMER3_CH3_CCR     ((TimerCCR)(TIMER3_BASE + 0x3C))
-#define TIMER3_CH4_CCR     ((TimerCCR)(TIMER3_BASE + 0x40))
-
-#define TIMER4_CH1_CCR     ((TimerCCR)(TIMER4_BASE + 0x34))
-#define TIMER4_CH2_CCR     ((TimerCCR)(TIMER4_BASE + 0x38))
-#define TIMER4_CH3_CCR     ((TimerCCR)(TIMER4_BASE + 0x3C))
-#define TIMER4_CH4_CCR     ((TimerCCR)(TIMER4_BASE + 0x40))
-
-/* Timers 5 and 8 are in high-density devices only (such as Maple
-   Native).  Timers 6 and 7 in these devices have no output compare
-   pins. */
-
-#define TIMER5_CH1_CCR     ((TimerCCR)(TIMER5_BASE + 0x34))
-#define TIMER5_CH2_CCR     ((TimerCCR)(TIMER5_BASE + 0x38))
-#define TIMER5_CH3_CCR     ((TimerCCR)(TIMER5_BASE + 0x3C))
-#define TIMER5_CH4_CCR     ((TimerCCR)(TIMER5_BASE + 0x40))
-
-#define TIMER8_CH1_CCR     ((TimerCCR)(TIMER8_BASE + 0x34))
-#define TIMER8_CH2_CCR     ((TimerCCR)(TIMER8_BASE + 0x38))
-#define TIMER8_CH3_CCR     ((TimerCCR)(TIMER8_BASE + 0x3C))
-#define TIMER8_CH4_CCR     ((TimerCCR)(TIMER8_BASE + 0x40))
-
-/**
- * Used to configure the behavior of a timer.
- */
-typedef enum TimerMode {
-    TIMER_DISABLED, /**< In this mode, the timer stops counting,
-                       interrupts are not called, and no state changes
-                       are output. */
-    TIMER_PWM, /**< This is the default mode for pins after
-                  initialization. */
-    TIMER_OUTPUTCOMPARE, /**< In this mode, the timer counts from 0 to
-                            its reload value repeatedly; every time
-                            the counter value reaches one of the
-                            channel compare values, the corresponding
-                            interrupt is fired. */
-} TimerMode;
-
-typedef struct {
-    /* Fields up to ARR common to general purpose (2,3,4,5), advanced
-       control (1,8) and basic (6, 7) timers: */
-    volatile uint16 CR1;
-    uint16  RESERVED0;
-    volatile uint16 CR2;
-    uint16  RESERVED1;
-    volatile uint16 SMCR;
-    uint16  RESERVED2;
-    volatile uint16 DIER;
-    uint16  RESERVED3;
-    volatile uint16 SR;
-    uint16  RESERVED4;
-    volatile uint16 EGR;
-    uint16  RESERVED5;
-    volatile uint16 CCMR1;
-    uint16  RESERVED6;
-    volatile uint16 CCMR2;
-    uint16  RESERVED7;
-    volatile uint16 CCER;
-    uint16  RESERVED8;
-    volatile uint16 CNT;
-    uint16  RESERVED9;
-    volatile uint16 PSC;
-    uint16  RESERVED10;
-    volatile uint16 ARR;
-    uint16  RESERVED11;
-    /* Basic timers have none of the following: */
-    volatile uint16 RCR;        /* Advanced control timers only */
-    uint16  RESERVED12;         /* Advanced control timers only */
-    volatile uint16 CCR1;
-    uint16  RESERVED13;
-    volatile uint16 CCR2;
-    uint16  RESERVED14;
-    volatile uint16 CCR3;
-    uint16  RESERVED15;
-    volatile uint16 CCR4;
-    uint16  RESERVED16;
-    volatile uint16 BDTR;       /* Advanced control timers only */
-    uint16  RESERVED17;         /* Advanced control timers only */
-    volatile uint16 DCR;
-    uint16  RESERVED18;
-    volatile uint16 DMAR;
-    uint16  RESERVED19;
-} timer_port;
-
-/**
- * Timer device numbers.  See STM32 reference manual, chapters 13-15.
- */
-/* several locations depend on TIMER1=0, etc.; don't change the
-   enumerator values to start at 1. */
-typedef enum {
-    TIMER1,      /*< Advanced control timer TIM1 */
-    TIMER2,      /*< General purpose timer TIM2 */
-    TIMER3,      /*< General purpose timer TIM3 */
-    TIMER4,      /*< General purpose timer TIM4 */
-#ifdef STM32_HIGH_DENSITY
-    TIMER5,      /*< General purpose timer TIM5; high density only */
-    /* FIXME maple native: put timers 6 and 7 back in and make the
-       corresponding changes to timers.c */
-    /* TIMER6,      /\*< Basic timer TIM6; high density only *\/ */
-    /* TIMER7,      /\*< Basic timer TIM7; high density only *\/ */
-    TIMER8,      /*< Advanced control timer TIM8; high density only */
-#endif
-    TIMER_INVALID /* FIXME: this is starting to seem like a bad idea */
-} timer_dev_num;
-
-/* timer descriptor */
-struct timer_dev {
-    timer_port *base;
-    const uint8 rcc_dev_num;
-    const uint8 nvic_dev_num;
-    volatile voidFuncPtr handlers[4];
-};
-
-extern struct timer_dev timer_dev_table[];
-
-/**
- * Initializes timer with prescale as the clock divisor.
- *
- * @param timer_num Timer number.
- *
- * @param prescale value in the range 1--65535 to use as a prescaler
- * for timer counter increment frequency.
- *
- * @see timer_dev_num
- * @see timer_set_prescaler()
- * @see timer_set_mode()
- */
-void timer_init(timer_dev_num timer_num, uint16 prescale);
-
-/**
- * Quickly disable all timers.  Calling this function is faster than,
- * e.g., calling timer_set_mode() for all available timers/channels.
- */
-void timer_disable_all(void);
-
-/**
- * Returns the timer's counter value.  Due to function call overhead,
- * this value is likely to be inaccurate if the counter is running
- * with a low prescaler.
- *
- * @param timer_num the timer whose counter to return.
- *
- * @pre Timer has been initialized.
- */
-uint16 timer_get_count(timer_dev_num timer_num);
-
-/**
- * Sets the counter value for the given timer.
- *
- * @param timer_num the timer whose counter to set.
- *
- * @param value the new counter value.
- *
- * @pre Timer has been initialized.
- */
-void timer_set_count(timer_dev_num timer_num, uint16 value);
-
-/**
- * Stops the timer's counter from incrementing.  Does not modify the
- * timer's mode or settings.
- *
- * @param timer_num the timer to pause.
- *
- * @see timer_resume()
- *
- * @pre Timer has been initialized.
- */
-void timer_pause(timer_dev_num timer_num);
-
-/**
- * Starts the counter for the given timer.  Does not modify the
- * timer's mode or settings.  The timer will begin counting on the
- * first rising clock cycle after it has been re-enabled using this
- * function.
- *
- * @param timer_num the timer to resume.
- *
- * @see timer_pause()
- *
- * @pre Timer has been initialized.
- */
-void timer_resume(timer_dev_num timer_num);
-
-/**
- * Returns the prescaler for the given timer.
- *
- * @param timer_num the timer whose prescaler to return.
- *
- * @see timer_set_prescaler()
- *
- * @pre Timer has been initialized.
- */
-uint16 timer_get_prescaler(timer_dev_num timer_num);
-
-/**
- * Sets the prescaler for the given timer.  This value goes into the
- * PSC register, so it's 0-based (i.e., a prescale of 0 counts 1 tick
- * per clock cycle).  This prescale does not take effect until the
- * next update event.
- *
- * @param timer_num the timer whose prescaler to set.
- *
- * @param prescale the new prescaler.
- *
- * @pre Timer has been initialized.
- */
-void timer_set_prescaler(timer_dev_num timer_num, uint16 prescale);
-
-/**
- * Gets the reload value for the timer.
- *
- * @see timer_set_reload()
- *
- * @pre Timer has been initialized.
- */
-uint16 timer_get_reload(timer_dev_num timer_num);
-
-/**
- * Sets the reload value for the timer.
- *
- * After this function returns, the timer's counter will reset to 0
- * after it has reached the value max_reload.
- *
- * @pre Timer has been initialized.
- */
-void timer_set_reload(timer_dev_num timer_num, uint16 max_reload);
-
-/* TODO: timer_get_mode */
-
-/**
- * Set the mode of an individual timer channel.
- *
- * @see timer_disable_all()
- * @see TimerMode
- * @see timer_dev_num
- * @pre Timer has been initialized.
- */
-void timer_set_mode(timer_dev_num timer_num, uint8 channel, TimerMode mode);
-
-/**
- * Get the compare value for the given timer channel.
- * @see timer_set_compare_value()
- * @see timer_dev_num
- * @pre Timer has been initialized.
- */
-uint16 timer_get_compare_value(timer_dev_num timer_num, uint8 channel);
-
-/**
- * Sets the compare value for a given timer channel.  Useful for
- * scheduling when interrupt handlers will be called.
- *
- * @see timer_attach_interrupt()
- * @see timer_detach_interrupt()
- * @see timer_set_reload()
- * @see timer_dev_num
- * @pre Timer has been initialized.
- */
-void timer_set_compare_value(timer_dev_num timer_num, uint8 channel,
-                             uint16 value);
-
-/**
- * Detach the interrupt handler for the given timer channel, if any.
- * After this function returns, any handler attached to the given
- * channel will no longer be called.
- *
- * @see timer_attach_interrupt()
- * @pre Timer has been initialized.
- * @see timer_dev_num
- */
-void timer_detach_interrupt(timer_dev_num timer_num, uint8 channel);
-
-/**
- * Attach an interrupt handler for the given timer and channel.  The
- * given ISR, handler, will be called whenever the timer's counter
- * reaches the compare value for the given timer and channel.
- *
- * @see timer_set_compare_value()
- * @see timer_detach_interrupt()
- * @see timer_set_mode()
- * @see timer_dev_num
- * @see voidFuncPtr
- * @pre Timer has been initialized.
- * @pre The channel's mode must be set to TIMER_OUTPUTCOMPARE, or the
- *      interrupt handler will not get called.
- */
-void timer_attach_interrupt(timer_dev_num timer_num, uint8 channel,
-                            voidFuncPtr handler);
-
-/**
- * Programmatically generate an update event on the given timer.  This
- * updates the prescaler, reloads the compare value (in upcounting
- * mode, etc.).
- *
- * @pre Timer has been initialized.
- */
-void timer_generate_update(timer_dev_num timer_num);
-
-/**
- * Turn on PWM with duty_cycle.
- *
- * @param ccr TIMERx_CHn_CCR, where x ranges over timers, and n ranges
- * from 1 to 4.
- *
- * @param duty_cycle: A number between 0 and
- * timer_get_compare_value(TIMERx, y), where x and y are as above.
- *
- * @pre Pin has been set to alternate function output.
- *
- * @pre Timer has been initialized.
- */
-static inline void timer_pwm_write_ccr(TimerCCR ccr, uint16 duty_cycle) {
-    *ccr = duty_cycle;
-}
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-
-#endif
-
diff --git a/libmaple/util.c b/libmaple/util.c
index 09fbecd..6b4f216 100644
--- a/libmaple/util.c
+++ b/libmaple/util.c
@@ -32,7 +32,7 @@
 #include "gpio.h"
 #include "nvic.h"
 #include "adc.h"
-#include "timers.h"
+#include "timer.h"
 
 /* Failed asserts send out a message on this USART. */
 #ifndef ERROR_USART_NUM