series/rcc.h: Lose BIT().

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

1 files changed, 228 insertions, 228 deletions

diff --git a/libmaple/stm32f2/include/series/rcc.h b/libmaple/stm32f2/include/series/rcc.h
index e5a6e3e..1d9de85 100644
--- a/libmaple/stm32f2/include/series/rcc.h
+++ b/libmaple/stm32f2/include/series/rcc.h
@@ -36,7 +36,7 @@
 extern "C"{
 #endif
 
-#include <libmaple/libmaple.h>
+#include <libmaple/libmaple_types.h>
 
 /*
  * Register map
@@ -105,25 +105,25 @@ typedef struct rcc_reg_map {
 #define RCC_CR_HSIRDY_BIT               1
 #define RCC_CR_HSION_BIT                0
 
-#define RCC_CR_PLLI2SRDY                BIT(RCC_CR_PLLI2SRDY_BIT)
-#define RCC_CR_PLLI2SON                 BIT(RCC_CR_PLLI2SON_BIT)
-#define RCC_CR_PLLRDY                   BIT(RCC_CR_PLLRDY_BIT)
-#define RCC_CR_PLLON                    BIT(RCC_CR_PLLON_BIT)
-#define RCC_CR_CSSON                    BIT(RCC_CR_CSSON_BIT)
-#define RCC_CR_HSEBYP                   BIT(RCC_CR_HSEBYP_BIT)
-#define RCC_CR_HSERDY                   BIT(RCC_CR_HSERDY_BIT)
-#define RCC_CR_HSEON                    BIT(RCC_CR_HSEON_BIT)
+#define RCC_CR_PLLI2SRDY                (1U << RCC_CR_PLLI2SRDY_BIT)
+#define RCC_CR_PLLI2SON                 (1U << RCC_CR_PLLI2SON_BIT)
+#define RCC_CR_PLLRDY                   (1U << RCC_CR_PLLRDY_BIT)
+#define RCC_CR_PLLON                    (1U << RCC_CR_PLLON_BIT)
+#define RCC_CR_CSSON                    (1U << RCC_CR_CSSON_BIT)
+#define RCC_CR_HSEBYP                   (1U << RCC_CR_HSEBYP_BIT)
+#define RCC_CR_HSERDY                   (1U << RCC_CR_HSERDY_BIT)
+#define RCC_CR_HSEON                    (1U << RCC_CR_HSEON_BIT)
 #define RCC_CR_HSICAL                   (0xFF << 8)
 #define RCC_CR_HSITRIM                  (0x1F << 3)
-#define RCC_CR_HSIRDY                   BIT(RCC_CR_HSIRDY_BIT)
-#define RCC_CR_HSION                    BIT(RCC_CR_HSION_BIT)
+#define RCC_CR_HSIRDY                   (1U << RCC_CR_HSIRDY_BIT)
+#define RCC_CR_HSION                    (1U << RCC_CR_HSION_BIT)
 
 /* PLL configuration register */
 
 #define RCC_PLLCFGR_PLLSRC_BIT          22
 
 #define RCC_PLLCFGR_PLLQ                (0xF << 24)
-#define RCC_PLLCFGR_PLLSRC              BIT(RCC_PLLCFGR_PLLSRC_BIT)
+#define RCC_PLLCFGR_PLLSRC              (1U << RCC_PLLCFGR_PLLSRC_BIT)
 #define RCC_PLLCFGR_PLLSRC_HSI          (0x0 << RCC_PLLCFGR_PLLSRC_BIT)
 #define RCC_PLLCFGR_PLLSRC_HSE          (0x1 << RCC_PLLCFGR_PLLSRC_BIT)
 #define RCC_PLLCFGR_PLLP                (0x3 << 16)
@@ -154,7 +154,7 @@ typedef struct rcc_reg_map {
 #define RCC_CFGR_MCO1PRE_DIV_4          (0x6 << 24)
 #define RCC_CFGR_MCO1PRE_DIV_5          (0x7 << 24)
 
-#define RCC_CFGR_I2SSRC                 BIT(RCC_CFGR_I2SSRC_BIT)
+#define RCC_CFGR_I2SSRC                 (1U << RCC_CFGR_I2SSRC_BIT)
 #define RCC_CFGR_I2SSRC_PLLI2S          (0 << RCC_CFGR_I2SSRC_BIT)
 #define RCC_CFGR_I2SSRC_I2S_CKIN        (1 << RCC_CFGR_I2SSRC_BIT)
 
@@ -228,30 +228,30 @@ typedef struct rcc_reg_map {
 #define RCC_CIR_LSERDYF_BIT             1
 #define RCC_CIR_LSIRDYF_BIT             0
 
-#define RCC_CIR_CSSC                    BIT(RCC_CIR_CSSC_BIT)
+#define RCC_CIR_CSSC                    (1U << RCC_CIR_CSSC_BIT)
 
-#define RCC_CIR_PLLI2SRDYC              BIT(RCC_CIR_PLLI2SRDYC_BIT)
-#define RCC_CIR_PLLRDYC                 BIT(RCC_CIR_PLLRDYC_BIT)
-#define RCC_CIR_HSERDYC                 BIT(RCC_CIR_HSERDYC_BIT)
-#define RCC_CIR_HSIRDYC                 BIT(RCC_CIR_HSIRDYC_BIT)
-#define RCC_CIR_LSERDYC                 BIT(RCC_CIR_LSERDYC_BIT)
-#define RCC_CIR_LSIRDYC                 BIT(RCC_CIR_LSIRDYC_BIT)
+#define RCC_CIR_PLLI2SRDYC              (1U << RCC_CIR_PLLI2SRDYC_BIT)
+#define RCC_CIR_PLLRDYC                 (1U << RCC_CIR_PLLRDYC_BIT)
+#define RCC_CIR_HSERDYC                 (1U << RCC_CIR_HSERDYC_BIT)
+#define RCC_CIR_HSIRDYC                 (1U << RCC_CIR_HSIRDYC_BIT)
+#define RCC_CIR_LSERDYC                 (1U << RCC_CIR_LSERDYC_BIT)
+#define RCC_CIR_LSIRDYC                 (1U << RCC_CIR_LSIRDYC_BIT)
 
-#define RCC_CIR_PLLI2SRDYIE             BIT(RCC_CIR_PLLI2SRDYIE_BIT)
-#define RCC_CIR_PLLRDYIE                BIT(RCC_CIR_PLLRDYIE_BIT)
-#define RCC_CIR_HSERDYIE                BIT(RCC_CIR_HSERDYIE_BIT)
-#define RCC_CIR_HSIRDYIE                BIT(RCC_CIR_HSIRDYIE_BIT)
-#define RCC_CIR_LSERDYIE                BIT(RCC_CIR_LSERDYIE_BIT)
-#define RCC_CIR_LSIRDYIE                BIT(RCC_CIR_LSIRDYIE_BIT)
+#define RCC_CIR_PLLI2SRDYIE             (1U << RCC_CIR_PLLI2SRDYIE_BIT)
+#define RCC_CIR_PLLRDYIE                (1U << RCC_CIR_PLLRDYIE_BIT)
+#define RCC_CIR_HSERDYIE                (1U << RCC_CIR_HSERDYIE_BIT)
+#define RCC_CIR_HSIRDYIE                (1U << RCC_CIR_HSIRDYIE_BIT)
+#define RCC_CIR_LSERDYIE                (1U << RCC_CIR_LSERDYIE_BIT)
+#define RCC_CIR_LSIRDYIE                (1U << RCC_CIR_LSIRDYIE_BIT)
 
-#define RCC_CIR_CSSF                    BIT(RCC_CIR_CSSF_BIT)
+#define RCC_CIR_CSSF                    (1U << RCC_CIR_CSSF_BIT)
 
-#define RCC_CIR_PLLI2SRDYF              BIT(RCC_CIR_PLLI2SRDYF_BIT)
-#define RCC_CIR_PLLRDYF                 BIT(RCC_CIR_PLLRDYF_BIT)
-#define RCC_CIR_HSERDYF                 BIT(RCC_CIR_HSERDYF_BIT)
-#define RCC_CIR_HSIRDYF                 BIT(RCC_CIR_HSIRDYF_BIT)
-#define RCC_CIR_LSERDYF                 BIT(RCC_CIR_LSERDYF_BIT)
-#define RCC_CIR_LSIRDYF                 BIT(RCC_CIR_LSIRDYF_BIT)
+#define RCC_CIR_PLLI2SRDYF              (1U << RCC_CIR_PLLI2SRDYF_BIT)
+#define RCC_CIR_PLLRDYF                 (1U << RCC_CIR_PLLRDYF_BIT)
+#define RCC_CIR_HSERDYF                 (1U << RCC_CIR_HSERDYF_BIT)
+#define RCC_CIR_HSIRDYF                 (1U << RCC_CIR_HSIRDYF_BIT)
+#define RCC_CIR_LSERDYF                 (1U << RCC_CIR_LSERDYF_BIT)
+#define RCC_CIR_LSIRDYF                 (1U << RCC_CIR_LSIRDYF_BIT)
 
 /* AHB1 peripheral reset register */
 
@@ -270,20 +270,20 @@ typedef struct rcc_reg_map {
 #define RCC_AHB1RSTR_GPIOBRST_BIT       1
 #define RCC_AHB1RSTR_GPIOARST_BIT       0
 
-#define RCC_AHB1RSTR_OTGHSRST           BIT(RCC_AHB1RSTR_OTGHSRST_BIT)
-#define RCC_AHB1RSTR_ETHMACRST          BIT(RCC_AHB1RSTR_ETHMACRST_BIT)
-#define RCC_AHB1RSTR_DMA2RST            BIT(RCC_AHB1RSTR_DMA2RST_BIT)
-#define RCC_AHB1RSTR_DMA1RST            BIT(RCC_AHB1RSTR_DMA1RST_BIT)
-#define RCC_AHB1RSTR_CRCRST             BIT(RCC_AHB1RSTR_CRCRST_BIT)
-#define RCC_AHB1RSTR_GPIOIRST           BIT(RCC_AHB1RSTR_GPIOIRST_BIT)
-#define RCC_AHB1RSTR_GPIOHRST           BIT(RCC_AHB1RSTR_GPIOHRST_BIT)
-#define RCC_AHB1RSTR_GPIOGRST           BIT(RCC_AHB1RSTR_GPIOGRST_BIT)
-#define RCC_AHB1RSTR_GPIOFRST           BIT(RCC_AHB1RSTR_GPIOFRST_BIT)
-#define RCC_AHB1RSTR_GPIOERST           BIT(RCC_AHB1RSTR_GPIOERST_BIT)
-#define RCC_AHB1RSTR_GPIODRST           BIT(RCC_AHB1RSTR_GPIODRST_BIT)
-#define RCC_AHB1RSTR_GPIOCRST           BIT(RCC_AHB1RSTR_GPIOCRST_BIT)
-#define RCC_AHB1RSTR_GPIOBRST           BIT(RCC_AHB1RSTR_GPIOBRST_BIT)
-#define RCC_AHB1RSTR_GPIOARST           BIT(RCC_AHB1RSTR_GPIOARST_BIT)
+#define RCC_AHB1RSTR_OTGHSRST           (1U << RCC_AHB1RSTR_OTGHSRST_BIT)
+#define RCC_AHB1RSTR_ETHMACRST          (1U << RCC_AHB1RSTR_ETHMACRST_BIT)
+#define RCC_AHB1RSTR_DMA2RST            (1U << RCC_AHB1RSTR_DMA2RST_BIT)
+#define RCC_AHB1RSTR_DMA1RST            (1U << RCC_AHB1RSTR_DMA1RST_BIT)
+#define RCC_AHB1RSTR_CRCRST             (1U << RCC_AHB1RSTR_CRCRST_BIT)
+#define RCC_AHB1RSTR_GPIOIRST           (1U << RCC_AHB1RSTR_GPIOIRST_BIT)
+#define RCC_AHB1RSTR_GPIOHRST           (1U << RCC_AHB1RSTR_GPIOHRST_BIT)
+#define RCC_AHB1RSTR_GPIOGRST           (1U << RCC_AHB1RSTR_GPIOGRST_BIT)
+#define RCC_AHB1RSTR_GPIOFRST           (1U << RCC_AHB1RSTR_GPIOFRST_BIT)
+#define RCC_AHB1RSTR_GPIOERST           (1U << RCC_AHB1RSTR_GPIOERST_BIT)
+#define RCC_AHB1RSTR_GPIODRST           (1U << RCC_AHB1RSTR_GPIODRST_BIT)
+#define RCC_AHB1RSTR_GPIOCRST           (1U << RCC_AHB1RSTR_GPIOCRST_BIT)
+#define RCC_AHB1RSTR_GPIOBRST           (1U << RCC_AHB1RSTR_GPIOBRST_BIT)
+#define RCC_AHB1RSTR_GPIOARST           (1U << RCC_AHB1RSTR_GPIOARST_BIT)
 
 /* AHB2 peripheral reset register */
 
@@ -293,17 +293,17 @@ typedef struct rcc_reg_map {
 #define RCC_AHB2RSTR_CRYPRST_BIT        4
 #define RCC_AHB2RSTR_DCMIRST_BIT        0
 
-#define RCC_AHB2RSTR_OTGFSRST           BIT(RCC_AHB2RSTR_OTGFSRST_BIT)
-#define RCC_AHB2RSTR_RNGRST             BIT(RCC_AHB2RSTR_RNGRST_BIT)
-#define RCC_AHB2RSTR_HASHRST            BIT(RCC_AHB2RSTR_HASHRST_BIT)
-#define RCC_AHB2RSTR_CRYPRST            BIT(RCC_AHB2RSTR_CRYPRST_BIT)
-#define RCC_AHB2RSTR_DCMIRST            BIT(RCC_AHB2RSTR_DCMIRST_BIT)
+#define RCC_AHB2RSTR_OTGFSRST           (1U << RCC_AHB2RSTR_OTGFSRST_BIT)
+#define RCC_AHB2RSTR_RNGRST             (1U << RCC_AHB2RSTR_RNGRST_BIT)
+#define RCC_AHB2RSTR_HASHRST            (1U << RCC_AHB2RSTR_HASHRST_BIT)
+#define RCC_AHB2RSTR_CRYPRST            (1U << RCC_AHB2RSTR_CRYPRST_BIT)
+#define RCC_AHB2RSTR_DCMIRST            (1U << RCC_AHB2RSTR_DCMIRST_BIT)
 
 /* AHB3 peripheral reset register */
 
 #define RCC_AHB3RSTR_FSMCRST_BIT        0
 
-#define RCC_AHB3RSTR_FSMCRST            BIT(RCC_AHB3RSTR_FSMCRST_BIT)
+#define RCC_AHB3RSTR_FSMCRST            (1U << RCC_AHB3RSTR_FSMCRST_BIT)
 
 /* APB1 peripheral reset register */
 
@@ -331,29 +331,29 @@ typedef struct rcc_reg_map {
 #define RCC_APB1RSTR_TIM3RST_BIT        1
 #define RCC_APB1RSTR_TIM2RST_BIT        0
 
-#define RCC_APB1RSTR_DACRST             BIT(RCC_APB1RSTR_DACRST_BIT)
-#define RCC_APB1RSTR_PWRRST             BIT(RCC_APB1RSTR_PWRRST_BIT)
-#define RCC_APB1RSTR_CAN2RST            BIT(RCC_APB1RSTR_CAN2RST_BIT)
-#define RCC_APB1RSTR_CAN1RST            BIT(RCC_APB1RSTR_CAN1RST_BIT)
-#define RCC_APB1RSTR_I2C3RST            BIT(RCC_APB1RSTR_I2C3RST_BIT)
-#define RCC_APB1RSTR_I2C2RST            BIT(RCC_APB1RSTR_I2C2RST_BIT)
-#define RCC_APB1RSTR_I2C1RST            BIT(RCC_APB1RSTR_I2C1RST_BIT)
-#define RCC_APB1RSTR_UART5RST           BIT(RCC_APB1RSTR_UART5RST_BIT)
-#define RCC_APB1RSTR_UART4RST           BIT(RCC_APB1RSTR_UART4RST_BIT)
-#define RCC_APB1RSTR_UART3RST           BIT(RCC_APB1RSTR_UART3RST_BIT)
-#define RCC_APB1RSTR_UART2RST           BIT(RCC_APB1RSTR_UART2RST_BIT)
-#define RCC_APB1RSTR_SPI3RST            BIT(RCC_APB1RSTR_SPI3RST_BIT)
-#define RCC_APB1RSTR_SPI2RST            BIT(RCC_APB1RSTR_SPI2RST_BIT)
-#define RCC_APB1RSTR_WWDGRST            BIT(RCC_APB1RSTR_WWDGRST_BIT)
-#define RCC_APB1RSTR_TIM14RST           BIT(RCC_APB1RSTR_TIM14RST_BIT)
-#define RCC_APB1RSTR_TIM13RST           BIT(RCC_APB1RSTR_TIM13RST_BIT)
-#define RCC_APB1RSTR_TIM12RST           BIT(RCC_APB1RSTR_TIM12RST_BIT)
-#define RCC_APB1RSTR_TIM7RST            BIT(RCC_APB1RSTR_TIM7RST_BIT)
-#define RCC_APB1RSTR_TIM6RST            BIT(RCC_APB1RSTR_TIM6RST_BIT)
-#define RCC_APB1RSTR_TIM5RST            BIT(RCC_APB1RSTR_TIM5RST_BIT)
-#define RCC_APB1RSTR_TIM4RST            BIT(RCC_APB1RSTR_TIM4RST_BIT)
-#define RCC_APB1RSTR_TIM3RST            BIT(RCC_APB1RSTR_TIM3RST_BIT)
-#define RCC_APB1RSTR_TIM2RST            BIT(RCC_APB1RSTR_TIM2RST_BIT)
+#define RCC_APB1RSTR_DACRST             (1U << RCC_APB1RSTR_DACRST_BIT)
+#define RCC_APB1RSTR_PWRRST             (1U << RCC_APB1RSTR_PWRRST_BIT)
+#define RCC_APB1RSTR_CAN2RST            (1U << RCC_APB1RSTR_CAN2RST_BIT)
+#define RCC_APB1RSTR_CAN1RST            (1U << RCC_APB1RSTR_CAN1RST_BIT)
+#define RCC_APB1RSTR_I2C3RST            (1U << RCC_APB1RSTR_I2C3RST_BIT)
+#define RCC_APB1RSTR_I2C2RST            (1U << RCC_APB1RSTR_I2C2RST_BIT)
+#define RCC_APB1RSTR_I2C1RST            (1U << RCC_APB1RSTR_I2C1RST_BIT)
+#define RCC_APB1RSTR_UART5RST           (1U << RCC_APB1RSTR_UART5RST_BIT)
+#define RCC_APB1RSTR_UART4RST           (1U << RCC_APB1RSTR_UART4RST_BIT)
+#define RCC_APB1RSTR_UART3RST           (1U << RCC_APB1RSTR_UART3RST_BIT)
+#define RCC_APB1RSTR_UART2RST           (1U << RCC_APB1RSTR_UART2RST_BIT)
+#define RCC_APB1RSTR_SPI3RST            (1U << RCC_APB1RSTR_SPI3RST_BIT)
+#define RCC_APB1RSTR_SPI2RST            (1U << RCC_APB1RSTR_SPI2RST_BIT)
+#define RCC_APB1RSTR_WWDGRST            (1U << RCC_APB1RSTR_WWDGRST_BIT)
+#define RCC_APB1RSTR_TIM14RST           (1U << RCC_APB1RSTR_TIM14RST_BIT)
+#define RCC_APB1RSTR_TIM13RST           (1U << RCC_APB1RSTR_TIM13RST_BIT)
+#define RCC_APB1RSTR_TIM12RST           (1U << RCC_APB1RSTR_TIM12RST_BIT)
+#define RCC_APB1RSTR_TIM7RST            (1U << RCC_APB1RSTR_TIM7RST_BIT)
+#define RCC_APB1RSTR_TIM6RST            (1U << RCC_APB1RSTR_TIM6RST_BIT)
+#define RCC_APB1RSTR_TIM5RST            (1U << RCC_APB1RSTR_TIM5RST_BIT)
+#define RCC_APB1RSTR_TIM4RST            (1U << RCC_APB1RSTR_TIM4RST_BIT)
+#define RCC_APB1RSTR_TIM3RST            (1U << RCC_APB1RSTR_TIM3RST_BIT)
+#define RCC_APB1RSTR_TIM2RST            (1U << RCC_APB1RSTR_TIM2RST_BIT)
 
 /* APB2 peripheral reset register */
 
@@ -369,17 +369,17 @@ typedef struct rcc_reg_map {
 #define RCC_APB2RSTR_TIM8RST_BIT        1
 #define RCC_APB2RSTR_TIM1RST_BIT        0
 
-#define RCC_APB2RSTR_TIM11RST           BIT(RCC_APB2RSTR_TIM11RST_BIT)
-#define RCC_APB2RSTR_TIM10RST           BIT(RCC_APB2RSTR_TIM10RST_BIT)
-#define RCC_APB2RSTR_TIM9RST            BIT(RCC_APB2RSTR_TIM9RST_BIT)
-#define RCC_APB2RSTR_SYSCFGRST          BIT(RCC_APB2RSTR_SYSCFGRST_BIT)
-#define RCC_APB2RSTR_SPI1RST            BIT(RCC_APB2RSTR_SPI1RST_BIT)
-#define RCC_APB2RSTR_SDIORST            BIT(RCC_APB2RSTR_SDIORST_BIT)
-#define RCC_APB2RSTR_ADCRST             BIT(RCC_APB2RSTR_ADCRST_BIT)
-#define RCC_APB2RSTR_USART6RST          BIT(RCC_APB2RSTR_USART6RST_BIT)
-#define RCC_APB2RSTR_USART1RST          BIT(RCC_APB2RSTR_USART1RST_BIT)
-#define RCC_APB2RSTR_TIM8RST            BIT(RCC_APB2RSTR_TIM8RST_BIT)
-#define RCC_APB2RSTR_TIM1RST            BIT(RCC_APB2RSTR_TIM1RST_BIT)
+#define RCC_APB2RSTR_TIM11RST           (1U << RCC_APB2RSTR_TIM11RST_BIT)
+#define RCC_APB2RSTR_TIM10RST           (1U << RCC_APB2RSTR_TIM10RST_BIT)
+#define RCC_APB2RSTR_TIM9RST            (1U << RCC_APB2RSTR_TIM9RST_BIT)
+#define RCC_APB2RSTR_SYSCFGRST          (1U << RCC_APB2RSTR_SYSCFGRST_BIT)
+#define RCC_APB2RSTR_SPI1RST            (1U << RCC_APB2RSTR_SPI1RST_BIT)
+#define RCC_APB2RSTR_SDIORST            (1U << RCC_APB2RSTR_SDIORST_BIT)
+#define RCC_APB2RSTR_ADCRST             (1U << RCC_APB2RSTR_ADCRST_BIT)
+#define RCC_APB2RSTR_USART6RST          (1U << RCC_APB2RSTR_USART6RST_BIT)
+#define RCC_APB2RSTR_USART1RST          (1U << RCC_APB2RSTR_USART1RST_BIT)
+#define RCC_APB2RSTR_TIM8RST            (1U << RCC_APB2RSTR_TIM8RST_BIT)
+#define RCC_APB2RSTR_TIM1RST            (1U << RCC_APB2RSTR_TIM1RST_BIT)
 
 /* AHB1 peripheral clock enable register */
 
@@ -403,25 +403,25 @@ typedef struct rcc_reg_map {
 #define RCC_AHB1ENR_GPIOBEN_BIT         1
 #define RCC_AHB1ENR_GPIOAEN_BIT         0
 
-#define RCC_AHB1ENR_OTGHSULPIEN         BIT(RCC_AHB1ENR_OTGHSULPIEN_BIT)
-#define RCC_AHB1ENR_OTGHSEN             BIT(RCC_AHB1ENR_OTGHSEN_BIT)
-#define RCC_AHB1ENR_ETHMACPTPEN         BIT(RCC_AHB1ENR_ETHMACPTPEN_BIT)
-#define RCC_AHB1ENR_ETHMACRXEN          BIT(RCC_AHB1ENR_ETHMACRXEN_BIT)
-#define RCC_AHB1ENR_ETHMACTXEN          BIT(RCC_AHB1ENR_ETHMACTXEN_BIT)
-#define RCC_AHB1ENR_ETHMACEN            BIT(RCC_AHB1ENR_ETHMACEN_BIT)
-#define RCC_AHB1ENR_DMA2EN              BIT(RCC_AHB1ENR_DMA2EN_BIT)
-#define RCC_AHB1ENR_DMA1EN              BIT(RCC_AHB1ENR_DMA1EN_BIT)
-#define RCC_AHB1ENR_BKPSRAMEN           BIT(RCC_AHB1ENR_BKPSRAMEN_BIT)
-#define RCC_AHB1ENR_CRCEN               BIT(RCC_AHB1ENR_CRCEN_BIT)
-#define RCC_AHB1ENR_GPIOIEN             BIT(RCC_AHB1ENR_GPIOIEN_BIT)
-#define RCC_AHB1ENR_GPIOHEN             BIT(RCC_AHB1ENR_GPIOHEN_BIT)
-#define RCC_AHB1ENR_GPIOGEN             BIT(RCC_AHB1ENR_GPIOGEN_BIT)
-#define RCC_AHB1ENR_GPIOFEN             BIT(RCC_AHB1ENR_GPIOFEN_BIT)
-#define RCC_AHB1ENR_GPIOEEN             BIT(RCC_AHB1ENR_GPIOEEN_BIT)
-#define RCC_AHB1ENR_GPIODEN             BIT(RCC_AHB1ENR_GPIODEN_BIT)
-#define RCC_AHB1ENR_GPIOCEN             BIT(RCC_AHB1ENR_GPIOCEN_BIT)
-#define RCC_AHB1ENR_GPIOBEN             BIT(RCC_AHB1ENR_GPIOBEN_BIT)
-#define RCC_AHB1ENR_GPIOAEN             BIT(RCC_AHB1ENR_GPIOAEN_BIT)
+#define RCC_AHB1ENR_OTGHSULPIEN         (1U << RCC_AHB1ENR_OTGHSULPIEN_BIT)
+#define RCC_AHB1ENR_OTGHSEN             (1U << RCC_AHB1ENR_OTGHSEN_BIT)
+#define RCC_AHB1ENR_ETHMACPTPEN         (1U << RCC_AHB1ENR_ETHMACPTPEN_BIT)
+#define RCC_AHB1ENR_ETHMACRXEN          (1U << RCC_AHB1ENR_ETHMACRXEN_BIT)
+#define RCC_AHB1ENR_ETHMACTXEN          (1U << RCC_AHB1ENR_ETHMACTXEN_BIT)
+#define RCC_AHB1ENR_ETHMACEN            (1U << RCC_AHB1ENR_ETHMACEN_BIT)
+#define RCC_AHB1ENR_DMA2EN              (1U << RCC_AHB1ENR_DMA2EN_BIT)
+#define RCC_AHB1ENR_DMA1EN              (1U << RCC_AHB1ENR_DMA1EN_BIT)
+#define RCC_AHB1ENR_BKPSRAMEN           (1U << RCC_AHB1ENR_BKPSRAMEN_BIT)
+#define RCC_AHB1ENR_CRCEN               (1U << RCC_AHB1ENR_CRCEN_BIT)
+#define RCC_AHB1ENR_GPIOIEN             (1U << RCC_AHB1ENR_GPIOIEN_BIT)
+#define RCC_AHB1ENR_GPIOHEN             (1U << RCC_AHB1ENR_GPIOHEN_BIT)
+#define RCC_AHB1ENR_GPIOGEN             (1U << RCC_AHB1ENR_GPIOGEN_BIT)
+#define RCC_AHB1ENR_GPIOFEN             (1U << RCC_AHB1ENR_GPIOFEN_BIT)
+#define RCC_AHB1ENR_GPIOEEN             (1U << RCC_AHB1ENR_GPIOEEN_BIT)
+#define RCC_AHB1ENR_GPIODEN             (1U << RCC_AHB1ENR_GPIODEN_BIT)
+#define RCC_AHB1ENR_GPIOCEN             (1U << RCC_AHB1ENR_GPIOCEN_BIT)
+#define RCC_AHB1ENR_GPIOBEN             (1U << RCC_AHB1ENR_GPIOBEN_BIT)
+#define RCC_AHB1ENR_GPIOAEN             (1U << RCC_AHB1ENR_GPIOAEN_BIT)
 
 /* AHB2 peripheral clock enable register */
 
@@ -431,17 +431,17 @@ typedef struct rcc_reg_map {
 #define RCC_AHB2ENR_CRYPEN_BIT          4
 #define RCC_AHB2ENR_DCMIEN_BIT          0
 
-#define RCC_AHB2ENR_OTGFSEN             BIT(RCC_AHB2ENR_OTGFSEN_BIT)
-#define RCC_AHB2ENR_RNGEN               BIT(RCC_AHB2ENR_RNGEN_BIT)
-#define RCC_AHB2ENR_HASHEN              BIT(RCC_AHB2ENR_HASHEN_BIT)
-#define RCC_AHB2ENR_CRYPEN              BIT(RCC_AHB2ENR_CRYPEN_BIT)
-#define RCC_AHB2ENR_DCMIEN              BIT(RCC_AHB2ENR_DCMIEN_BIT)
+#define RCC_AHB2ENR_OTGFSEN             (1U << RCC_AHB2ENR_OTGFSEN_BIT)
+#define RCC_AHB2ENR_RNGEN               (1U << RCC_AHB2ENR_RNGEN_BIT)
+#define RCC_AHB2ENR_HASHEN              (1U << RCC_AHB2ENR_HASHEN_BIT)
+#define RCC_AHB2ENR_CRYPEN              (1U << RCC_AHB2ENR_CRYPEN_BIT)
+#define RCC_AHB2ENR_DCMIEN              (1U << RCC_AHB2ENR_DCMIEN_BIT)
 
 /* AHB3 peripheral clock enable register */
 
 #define RCC_AHB3ENR_FSMCEN_BIT          0
 
-#define RCC_AHB3ENR_FSMCEN              BIT(RCC_AHB3ENR_FSMCEN_BIT)
+#define RCC_AHB3ENR_FSMCEN              (1U << RCC_AHB3ENR_FSMCEN_BIT)
 
 /* APB1 peripheral clock enable register */
 
@@ -469,29 +469,29 @@ typedef struct rcc_reg_map {
 #define RCC_APB1ENR_TIM3EN_BIT          1
 #define RCC_APB1ENR_TIM2EN_BIT          0
 
-#define RCC_APB1ENR_DACEN               BIT(RCC_APB1ENR_DACEN_BIT)
-#define RCC_APB1ENR_PWREN               BIT(RCC_APB1ENR_PWREN_BIT)
-#define RCC_APB1ENR_CAN2EN              BIT(RCC_APB1ENR_CAN2EN_BIT)
-#define RCC_APB1ENR_CAN1EN              BIT(RCC_APB1ENR_CAN1EN_BIT)
-#define RCC_APB1ENR_I2C3EN              BIT(RCC_APB1ENR_I2C3EN_BIT)
-#define RCC_APB1ENR_I2C2EN              BIT(RCC_APB1ENR_I2C2EN_BIT)
-#define RCC_APB1ENR_I2C1EN              BIT(RCC_APB1ENR_I2C1EN_BIT)
-#define RCC_APB1ENR_UART5EN             BIT(RCC_APB1ENR_UART5EN_BIT)
-#define RCC_APB1ENR_UART4EN             BIT(RCC_APB1ENR_UART4EN_BIT)
-#define RCC_APB1ENR_USART3EN            BIT(RCC_APB1ENR_USART3EN_BIT)
-#define RCC_APB1ENR_USART2EN            BIT(RCC_APB1ENR_USART2EN_BIT)
-#define RCC_APB1ENR_SPI3EN              BIT(RCC_APB1ENR_SPI3EN_BIT)
-#define RCC_APB1ENR_SPI2EN              BIT(RCC_APB1ENR_SPI2EN_BIT)
-#define RCC_APB1ENR_WWDGEN              BIT(RCC_APB1ENR_WWDGEN_BIT)
-#define RCC_APB1ENR_TIM14EN             BIT(RCC_APB1ENR_TIM14EN_BIT)
-#define RCC_APB1ENR_TIM13EN             BIT(RCC_APB1ENR_TIM13EN_BIT)
-#define RCC_APB1ENR_TIM12EN             BIT(RCC_APB1ENR_TIM12EN_BIT)
-#define RCC_APB1ENR_TIM7EN              BIT(RCC_APB1ENR_TIM7EN_BIT)
-#define RCC_APB1ENR_TIM6EN              BIT(RCC_APB1ENR_TIM6EN_BIT)
-#define RCC_APB1ENR_TIM5EN              BIT(RCC_APB1ENR_TIM5EN_BIT)
-#define RCC_APB1ENR_TIM4EN              BIT(RCC_APB1ENR_TIM4EN_BIT)
-#define RCC_APB1ENR_TIM3EN              BIT(RCC_APB1ENR_TIM3EN_BIT)
-#define RCC_APB1ENR_TIM2EN              BIT(RCC_APB1ENR_TIM2EN_BIT)
+#define RCC_APB1ENR_DACEN               (1U << RCC_APB1ENR_DACEN_BIT)
+#define RCC_APB1ENR_PWREN               (1U << RCC_APB1ENR_PWREN_BIT)
+#define RCC_APB1ENR_CAN2EN              (1U << RCC_APB1ENR_CAN2EN_BIT)
+#define RCC_APB1ENR_CAN1EN              (1U << RCC_APB1ENR_CAN1EN_BIT)
+#define RCC_APB1ENR_I2C3EN              (1U << RCC_APB1ENR_I2C3EN_BIT)
+#define RCC_APB1ENR_I2C2EN              (1U << RCC_APB1ENR_I2C2EN_BIT)
+#define RCC_APB1ENR_I2C1EN              (1U << RCC_APB1ENR_I2C1EN_BIT)
+#define RCC_APB1ENR_UART5EN             (1U << RCC_APB1ENR_UART5EN_BIT)
+#define RCC_APB1ENR_UART4EN             (1U << RCC_APB1ENR_UART4EN_BIT)
+#define RCC_APB1ENR_USART3EN            (1U << RCC_APB1ENR_USART3EN_BIT)
+#define RCC_APB1ENR_USART2EN            (1U << RCC_APB1ENR_USART2EN_BIT)
+#define RCC_APB1ENR_SPI3EN              (1U << RCC_APB1ENR_SPI3EN_BIT)
+#define RCC_APB1ENR_SPI2EN              (1U << RCC_APB1ENR_SPI2EN_BIT)
+#define RCC_APB1ENR_WWDGEN              (1U << RCC_APB1ENR_WWDGEN_BIT)
+#define RCC_APB1ENR_TIM14EN             (1U << RCC_APB1ENR_TIM14EN_BIT)
+#define RCC_APB1ENR_TIM13EN             (1U << RCC_APB1ENR_TIM13EN_BIT)
+#define RCC_APB1ENR_TIM12EN             (1U << RCC_APB1ENR_TIM12EN_BIT)
+#define RCC_APB1ENR_TIM7EN              (1U << RCC_APB1ENR_TIM7EN_BIT)
+#define RCC_APB1ENR_TIM6EN              (1U << RCC_APB1ENR_TIM6EN_BIT)
+#define RCC_APB1ENR_TIM5EN              (1U << RCC_APB1ENR_TIM5EN_BIT)
+#define RCC_APB1ENR_TIM4EN              (1U << RCC_APB1ENR_TIM4EN_BIT)
+#define RCC_APB1ENR_TIM3EN              (1U << RCC_APB1ENR_TIM3EN_BIT)
+#define RCC_APB1ENR_TIM2EN              (1U << RCC_APB1ENR_TIM2EN_BIT)
 
 /* APB2 peripheral clock enable register */
 
@@ -509,19 +509,19 @@ typedef struct rcc_reg_map {
 #define RCC_APB2ENR_TIM8EN_BIT          1
 #define RCC_APB2ENR_TIM1EN_BIT          0
 
-#define RCC_APB2ENR_TIM11EN             BIT(RCC_APB2ENR_TIM11EN_BIT)
-#define RCC_APB2ENR_TIM10EN             BIT(RCC_APB2ENR_TIM10EN_BIT)
-#define RCC_APB2ENR_TIM9EN              BIT(RCC_APB2ENR_TIM9EN_BIT)
-#define RCC_APB2ENR_SYSCFGEN            BIT(RCC_APB2ENR_SYSCFGEN_BIT)
-#define RCC_APB2ENR_SPI1EN              BIT(RCC_APB2ENR_SPI1EN_BIT)
-#define RCC_APB2ENR_SDIOEN              BIT(RCC_APB2ENR_SDIOEN_BIT)
-#define RCC_APB2ENR_ADC3EN              BIT(RCC_APB2ENR_ADC3EN_BIT)
-#define RCC_APB2ENR_ADC2EN              BIT(RCC_APB2ENR_ADC2EN_BIT)
-#define RCC_APB2ENR_ADC1EN              BIT(RCC_APB2ENR_ADC1EN_BIT)
-#define RCC_APB2ENR_USART6EN            BIT(RCC_APB2ENR_USART6EN_BIT)
-#define RCC_APB2ENR_USART1EN            BIT(RCC_APB2ENR_USART1EN_BIT)
-#define RCC_APB2ENR_TIM8EN              BIT(RCC_APB2ENR_TIM8EN_BIT)
-#define RCC_APB2ENR_TIM1EN              BIT(RCC_APB2ENR_TIM1EN_BIT)
+#define RCC_APB2ENR_TIM11EN             (1U << RCC_APB2ENR_TIM11EN_BIT)
+#define RCC_APB2ENR_TIM10EN             (1U << RCC_APB2ENR_TIM10EN_BIT)
+#define RCC_APB2ENR_TIM9EN              (1U << RCC_APB2ENR_TIM9EN_BIT)
+#define RCC_APB2ENR_SYSCFGEN            (1U << RCC_APB2ENR_SYSCFGEN_BIT)
+#define RCC_APB2ENR_SPI1EN              (1U << RCC_APB2ENR_SPI1EN_BIT)
+#define RCC_APB2ENR_SDIOEN              (1U << RCC_APB2ENR_SDIOEN_BIT)
+#define RCC_APB2ENR_ADC3EN              (1U << RCC_APB2ENR_ADC3EN_BIT)
+#define RCC_APB2ENR_ADC2EN              (1U << RCC_APB2ENR_ADC2EN_BIT)
+#define RCC_APB2ENR_ADC1EN              (1U << RCC_APB2ENR_ADC1EN_BIT)
+#define RCC_APB2ENR_USART6EN            (1U << RCC_APB2ENR_USART6EN_BIT)
+#define RCC_APB2ENR_USART1EN            (1U << RCC_APB2ENR_USART1EN_BIT)
+#define RCC_APB2ENR_TIM8EN              (1U << RCC_APB2ENR_TIM8EN_BIT)
+#define RCC_APB2ENR_TIM1EN              (1U << RCC_APB2ENR_TIM1EN_BIT)
 
 /* AHB1 peripheral clock enable in low power mode register */
 
@@ -547,27 +547,27 @@ typedef struct rcc_reg_map {
 #define RCC_AHB1LPENR_GPIOBLPEN_BIT     1
 #define RCC_AHB1LPENR_GPIOALPEN_BIT     0
 
-#define RCC_AHB1LPENR_OTGHSULPILPEN     BIT(RCC_AHB1LPENR_OTGHSULPILPEN_BIT)
-#define RCC_AHB1LPENR_OTGHSLPEN         BIT(RCC_AHB1LPENR_OTGHSLPEN_BIT)
-#define RCC_AHB1LPENR_ETHMACPTPLPEN     BIT(RCC_AHB1LPENR_ETHMACPTPLPEN_BIT)
-#define RCC_AHB1LPENR_ETHMACRXLPEN      BIT(RCC_AHB1LPENR_ETHMACRXLPEN_BIT)
-#define RCC_AHB1LPENR_ETHMACTXLPEN      BIT(RCC_AHB1LPENR_ETHMACTXLPEN_BIT)
-#define RCC_AHB1LPENR_ETHMACLPEN        BIT(RCC_AHB1LPENR_ETHMACLPEN_BIT)
-#define RCC_AHB1LPENR_DMA2LPEN          BIT(RCC_AHB1LPENR_DMA2LPEN_BIT)
-#define RCC_AHB1LPENR_DMA1LPEN          BIT(RCC_AHB1LPENR_DMA1LPEN_BIT)
-#define RCC_AHB1LPENR_BKPSRAMLPEN       BIT(RCC_AHB1LPENR_BKPSRAMLPEN_BIT)
-#define RCC_AHB1LPENR_SRAM2LPEN         BIT(RCC_AHB1LPENR_SRAM2LPEN_BIT)
-#define RCC_AHB1LPENR_SRAM1LPEN         BIT(RCC_AHB1LPENR_SRAM1LPEN_BIT)
-#define RCC_AHB1LPENR_FLITFLPEN         BIT(RCC_AHB1LPENR_FLITFLPEN_BIT)
-#define RCC_AHB1LPENR_CRCLPEN           BIT(RCC_AHB1LPENR_CRCLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOILPEN         BIT(RCC_AHB1LPENR_GPIOILPEN_BIT)
-#define RCC_AHB1LPENR_GPIOGLPEN         BIT(RCC_AHB1LPENR_GPIOGLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOFLPEN         BIT(RCC_AHB1LPENR_GPIOFLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOELPEN         BIT(RCC_AHB1LPENR_GPIOELPEN_BIT)
-#define RCC_AHB1LPENR_GPIODLPEN         BIT(RCC_AHB1LPENR_GPIODLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOCLPEN         BIT(RCC_AHB1LPENR_GPIOCLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOBLPEN         BIT(RCC_AHB1LPENR_GPIOBLPEN_BIT)
-#define RCC_AHB1LPENR_GPIOALPEN         BIT(RCC_AHB1LPENR_GPIOALPEN_BIT)
+#define RCC_AHB1LPENR_OTGHSULPILPEN     (1U << RCC_AHB1LPENR_OTGHSULPILPEN_BIT)
+#define RCC_AHB1LPENR_OTGHSLPEN         (1U << RCC_AHB1LPENR_OTGHSLPEN_BIT)
+#define RCC_AHB1LPENR_ETHMACPTPLPEN     (1U << RCC_AHB1LPENR_ETHMACPTPLPEN_BIT)
+#define RCC_AHB1LPENR_ETHMACRXLPEN      (1U << RCC_AHB1LPENR_ETHMACRXLPEN_BIT)
+#define RCC_AHB1LPENR_ETHMACTXLPEN      (1U << RCC_AHB1LPENR_ETHMACTXLPEN_BIT)
+#define RCC_AHB1LPENR_ETHMACLPEN        (1U << RCC_AHB1LPENR_ETHMACLPEN_BIT)
+#define RCC_AHB1LPENR_DMA2LPEN          (1U << RCC_AHB1LPENR_DMA2LPEN_BIT)
+#define RCC_AHB1LPENR_DMA1LPEN          (1U << RCC_AHB1LPENR_DMA1LPEN_BIT)
+#define RCC_AHB1LPENR_BKPSRAMLPEN       (1U << RCC_AHB1LPENR_BKPSRAMLPEN_BIT)
+#define RCC_AHB1LPENR_SRAM2LPEN         (1U << RCC_AHB1LPENR_SRAM2LPEN_BIT)
+#define RCC_AHB1LPENR_SRAM1LPEN         (1U << RCC_AHB1LPENR_SRAM1LPEN_BIT)
+#define RCC_AHB1LPENR_FLITFLPEN         (1U << RCC_AHB1LPENR_FLITFLPEN_BIT)
+#define RCC_AHB1LPENR_CRCLPEN           (1U << RCC_AHB1LPENR_CRCLPEN_BIT)
+#define RCC_AHB1LPENR_GPIOILPEN         (1U << RCC_AHB1LPENR_GPIOILPEN_BIT)
+#define RCC_AHB1LPENR_GPIOGLPEN         (1U << RCC_AHB1LPENR_GPIOGLPEN_BIT)
+#define RCC_AHB1LPENR_GPIOFLPEN         (1U << RCC_AHB1LPENR_GPIOFLPEN_BIT)
+#define RCC_AHB1LPENR_GPIOELPEN         (1U << RCC_AHB1LPENR_GPIOELPEN_BIT)
+#define RCC_AHB1LPENR_GPIODLPEN         (1U << RCC_AHB1LPENR_GPIODLPEN_BIT)
+#define RCC_AHB1LPENR_GPIOCLPEN         (1U << RCC_AHB1LPENR_GPIOCLPEN_BIT)
+#define RCC_AHB1LPENR_GPIOBLPEN         (1U << RCC_AHB1LPENR_GPIOBLPEN_BIT)
+#define RCC_AHB1LPENR_GPIOALPEN         (1U << RCC_AHB1LPENR_GPIOALPEN_BIT)
 
 /* AHB2 peripheral clock enable in low power mode register */
 
@@ -577,17 +577,17 @@ typedef struct rcc_reg_map {
 #define RCC_AHB2LPENR_CRYPLPEN_BIT      4
 #define RCC_AHB2LPENR_DCMILPEN_BIT      0
 
-#define RCC_AHB2LPENR_OTGFSLPEN         BIT(RCC_AHB2LPENR_OTGFSLPEN_BIT)
-#define RCC_AHB2LPENR_RNGLPEN           BIT(RCC_AHB2LPENR_RNGLPEN_BIT)
-#define RCC_AHB2LPENR_HASHLPEN          BIT(RCC_AHB2LPENR_HASHLPEN_BIT)
-#define RCC_AHB2LPENR_CRYPLPEN          BIT(RCC_AHB2LPENR_CRYPLPEN_BIT)
-#define RCC_AHB2LPENR_DCMILPEN          BIT(RCC_AHB2LPENR_DCMILPEN_BIT)
+#define RCC_AHB2LPENR_OTGFSLPEN         (1U << RCC_AHB2LPENR_OTGFSLPEN_BIT)
+#define RCC_AHB2LPENR_RNGLPEN           (1U << RCC_AHB2LPENR_RNGLPEN_BIT)
+#define RCC_AHB2LPENR_HASHLPEN          (1U << RCC_AHB2LPENR_HASHLPEN_BIT)
+#define RCC_AHB2LPENR_CRYPLPEN          (1U << RCC_AHB2LPENR_CRYPLPEN_BIT)
+#define RCC_AHB2LPENR_DCMILPEN          (1U << RCC_AHB2LPENR_DCMILPEN_BIT)
 
 /* AHB3 peripheral clock enable in low power mode register */
 
 #define RCC_AHB3LPENR_FSMCLPEN_BIT      0
 
-#define RCC_AHB3LPENR_FSMCLPEN          BIT(RCC_AHB3LPENR_FSMCLPEN_BIT)
+#define RCC_AHB3LPENR_FSMCLPEN          (1U << RCC_AHB3LPENR_FSMCLPEN_BIT)
 
 /* APB1 peripheral clock enable in low power mode register */
 
@@ -615,29 +615,29 @@ typedef struct rcc_reg_map {
 #define RCC_APB1LPENR_TIM3LPEN_BIT      1
 #define RCC_APB1LPENR_TIM2LPEN_BIT      0
 
-#define RCC_APB1LPENR_DACLPEN           BIT(RCC_APB1LPENR_DACLPEN_BIT)
-#define RCC_APB1LPENR_PWRLPEN           BIT(RCC_APB1LPENR_PWRLPEN_BIT)
-#define RCC_APB1LPENR_CAN2LPEN          BIT(RCC_APB1LPENR_CAN2LPEN_BIT)
-#define RCC_APB1LPENR_CAN1LPEN          BIT(RCC_APB1LPENR_CAN1LPEN_BIT)
-#define RCC_APB1LPENR_I2C3LPEN          BIT(RCC_APB1LPENR_I2C3LPEN_BIT)
-#define RCC_APB1LPENR_I2C2LPEN          BIT(RCC_APB1LPENR_I2C2LPEN_BIT)
-#define RCC_APB1LPENR_I2C1LPEN          BIT(RCC_APB1LPENR_I2C1LPEN_BIT)
-#define RCC_APB1LPENR_UART5LPEN         BIT(RCC_APB1LPENR_UART5LPEN_BIT)
-#define RCC_APB1LPENR_UART4LPEN         BIT(RCC_APB1LPENR_UART4LPEN_BIT)
-#define RCC_APB1LPENR_USART3LPEN        BIT(RCC_APB1LPENR_USART3LPEN_BIT)
-#define RCC_APB1LPENR_USART2LPEN        BIT(RCC_APB1LPENR_USART2LPEN_BIT)
-#define RCC_APB1LPENR_SPI3LPEN          BIT(RCC_APB1LPENR_SPI3LPEN_BIT)
-#define RCC_APB1LPENR_SPI2LPEN          BIT(RCC_APB1LPENR_SPI2LPEN_BIT)
-#define RCC_APB1LPENR_WWDGLPEN          BIT(RCC_APB1LPENR_WWDGLPEN_BIT)
-#define RCC_APB1LPENR_TIM14LPEN         BIT(RCC_APB1LPENR_TIM14LPEN_BIT)
-#define RCC_APB1LPENR_TIM13LPEN         BIT(RCC_APB1LPENR_TIM13LPEN_BIT)
-#define RCC_APB1LPENR_TIM12LPEN         BIT(RCC_APB1LPENR_TIM12LPEN_BIT)
-#define RCC_APB1LPENR_TIM7LPEN          BIT(RCC_APB1LPENR_TIM7LPEN_BIT)
-#define RCC_APB1LPENR_TIM6LPEN          BIT(RCC_APB1LPENR_TIM6LPEN_BIT)
-#define RCC_APB1LPENR_TIM5LPEN          BIT(RCC_APB1LPENR_TIM5LPEN_BIT)
-#define RCC_APB1LPENR_TIM4LPEN          BIT(RCC_APB1LPENR_TIM4LPEN_BIT)
-#define RCC_APB1LPENR_TIM3LPEN          BIT(RCC_APB1LPENR_TIM3LPEN_BIT)
-#define RCC_APB1LPENR_TIM2LPEN          BIT(RCC_APB1LPENR_TIM2LPEN_BIT)
+#define RCC_APB1LPENR_DACLPEN           (1U << RCC_APB1LPENR_DACLPEN_BIT)
+#define RCC_APB1LPENR_PWRLPEN           (1U << RCC_APB1LPENR_PWRLPEN_BIT)
+#define RCC_APB1LPENR_CAN2LPEN          (1U << RCC_APB1LPENR_CAN2LPEN_BIT)
+#define RCC_APB1LPENR_CAN1LPEN          (1U << RCC_APB1LPENR_CAN1LPEN_BIT)
+#define RCC_APB1LPENR_I2C3LPEN          (1U << RCC_APB1LPENR_I2C3LPEN_BIT)
+#define RCC_APB1LPENR_I2C2LPEN          (1U << RCC_APB1LPENR_I2C2LPEN_BIT)
+#define RCC_APB1LPENR_I2C1LPEN          (1U << RCC_APB1LPENR_I2C1LPEN_BIT)
+#define RCC_APB1LPENR_UART5LPEN         (1U << RCC_APB1LPENR_UART5LPEN_BIT)
+#define RCC_APB1LPENR_UART4LPEN         (1U << RCC_APB1LPENR_UART4LPEN_BIT)
+#define RCC_APB1LPENR_USART3LPEN        (1U << RCC_APB1LPENR_USART3LPEN_BIT)
+#define RCC_APB1LPENR_USART2LPEN        (1U << RCC_APB1LPENR_USART2LPEN_BIT)
+#define RCC_APB1LPENR_SPI3LPEN          (1U << RCC_APB1LPENR_SPI3LPEN_BIT)
+#define RCC_APB1LPENR_SPI2LPEN          (1U << RCC_APB1LPENR_SPI2LPEN_BIT)
+#define RCC_APB1LPENR_WWDGLPEN          (1U << RCC_APB1LPENR_WWDGLPEN_BIT)
+#define RCC_APB1LPENR_TIM14LPEN         (1U << RCC_APB1LPENR_TIM14LPEN_BIT)
+#define RCC_APB1LPENR_TIM13LPEN         (1U << RCC_APB1LPENR_TIM13LPEN_BIT)
+#define RCC_APB1LPENR_TIM12LPEN         (1U << RCC_APB1LPENR_TIM12LPEN_BIT)
+#define RCC_APB1LPENR_TIM7LPEN          (1U << RCC_APB1LPENR_TIM7LPEN_BIT)
+#define RCC_APB1LPENR_TIM6LPEN          (1U << RCC_APB1LPENR_TIM6LPEN_BIT)
+#define RCC_APB1LPENR_TIM5LPEN          (1U << RCC_APB1LPENR_TIM5LPEN_BIT)
+#define RCC_APB1LPENR_TIM4LPEN          (1U << RCC_APB1LPENR_TIM4LPEN_BIT)
+#define RCC_APB1LPENR_TIM3LPEN          (1U << RCC_APB1LPENR_TIM3LPEN_BIT)
+#define RCC_APB1LPENR_TIM2LPEN          (1U << RCC_APB1LPENR_TIM2LPEN_BIT)
 
 /* APB2 peripheral clock enable in low power mode register */
 
@@ -655,19 +655,19 @@ typedef struct rcc_reg_map {
 #define RCC_APB2LPENR_TIM8LPEN_BIT      1
 #define RCC_APB2LPENR_TIM1LPEN_BIT      0
 
-#define RCC_APB2LPENR_TIM11LPEN         BIT(RCC_APB2LPENR_TIM11LPEN_BIT)
-#define RCC_APB2LPENR_TIM10LPEN         BIT(RCC_APB2LPENR_TIM10LPEN_BIT)
-#define RCC_APB2LPENR_TIM9LPEN          BIT(RCC_APB2LPENR_TIM9LPEN_BIT)
-#define RCC_APB2LPENR_SYSCFGLPEN        BIT(RCC_APB2LPENR_SYSCFGLPEN_BIT)
-#define RCC_APB2LPENR_SPI1LPEN          BIT(RCC_APB2LPENR_SPI1LPEN_BIT)
-#define RCC_APB2LPENR_SDIOLPEN          BIT(RCC_APB2LPENR_SDIOLPEN_BIT)
-#define RCC_APB2LPENR_ADC3LPEN          BIT(RCC_APB2LPENR_ADC3LPEN_BIT)
-#define RCC_APB2LPENR_ADC2LPEN          BIT(RCC_APB2LPENR_ADC2LPEN_BIT)
-#define RCC_APB2LPENR_ADC1LPEN          BIT(RCC_APB2LPENR_ADC1LPEN_BIT)
-#define RCC_APB2LPENR_USART6LPEN        BIT(RCC_APB2LPENR_USART6LPEN_BIT)
-#define RCC_APB2LPENR_USART1LPEN        BIT(RCC_APB2LPENR_USART1LPEN_BIT)
-#define RCC_APB2LPENR_TIM8LPEN          BIT(RCC_APB2LPENR_TIM8LPEN_BIT)
-#define RCC_APB2LPENR_TIM1LPEN          BIT(RCC_APB2LPENR_TIM1LPEN_BIT)
+#define RCC_APB2LPENR_TIM11LPEN         (1U << RCC_APB2LPENR_TIM11LPEN_BIT)
+#define RCC_APB2LPENR_TIM10LPEN         (1U << RCC_APB2LPENR_TIM10LPEN_BIT)
+#define RCC_APB2LPENR_TIM9LPEN          (1U << RCC_APB2LPENR_TIM9LPEN_BIT)
+#define RCC_APB2LPENR_SYSCFGLPEN        (1U << RCC_APB2LPENR_SYSCFGLPEN_BIT)
+#define RCC_APB2LPENR_SPI1LPEN          (1U << RCC_APB2LPENR_SPI1LPEN_BIT)
+#define RCC_APB2LPENR_SDIOLPEN          (1U << RCC_APB2LPENR_SDIOLPEN_BIT)
+#define RCC_APB2LPENR_ADC3LPEN          (1U << RCC_APB2LPENR_ADC3LPEN_BIT)
+#define RCC_APB2LPENR_ADC2LPEN          (1U << RCC_APB2LPENR_ADC2LPEN_BIT)
+#define RCC_APB2LPENR_ADC1LPEN          (1U << RCC_APB2LPENR_ADC1LPEN_BIT)
+#define RCC_APB2LPENR_USART6LPEN        (1U << RCC_APB2LPENR_USART6LPEN_BIT)
+#define RCC_APB2LPENR_USART1LPEN        (1U << RCC_APB2LPENR_USART1LPEN_BIT)
+#define RCC_APB2LPENR_TIM8LPEN          (1U << RCC_APB2LPENR_TIM8LPEN_BIT)
+#define RCC_APB2LPENR_TIM1LPEN          (1U << RCC_APB2LPENR_TIM1LPEN_BIT)
 
 /* Backup domain control register */
 
@@ -677,16 +677,16 @@ typedef struct rcc_reg_map {
 #define RCC_BDCR_LSERDY_BIT             1
 #define RCC_BDCR_LSEON_BIT              0
 
-#define RCC_BDCR_BDRST                  BIT(RCC_BDCR_BDRST_BIT)
-#define RCC_BDCR_RTCEN                  BIT(RCC_BDCR_RTCEN_BIT)
+#define RCC_BDCR_BDRST                  (1U << RCC_BDCR_BDRST_BIT)
+#define RCC_BDCR_RTCEN                  (1U << RCC_BDCR_RTCEN_BIT)
 #define RCC_BDCR_RTCSEL                 (0x3 << 8)
 #define RCC_BDCR_RTCSEL_NOCLOCK         (0x0 << 8)
 #define RCC_BDCR_RTCSEL_LSE             (0x1 << 8)
 #define RCC_BDCR_RTCSEL_LSI             (0x2 << 8)
 #define RCC_BDCR_RTCSEL_HSE_DIV         (0x3 << 8)
-#define RCC_BDCR_LSEBYP                 BIT(RCC_BDCR_LSEBYP_BIT)
-#define RCC_BDCR_LSERDY                 BIT(RCC_BDCR_LSERDY_BIT)
-#define RCC_BDCR_LSEON                  BIT(RCC_BDCR_LSEON_BIT)
+#define RCC_BDCR_LSEBYP                 (1U << RCC_BDCR_LSEBYP_BIT)
+#define RCC_BDCR_LSERDY                 (1U << RCC_BDCR_LSERDY_BIT)
+#define RCC_BDCR_LSEON                  (1U << RCC_BDCR_LSEON_BIT)
 
 /* Clock control and status register */
 
@@ -701,24 +701,24 @@ typedef struct rcc_reg_map {
 #define RCC_CSR_LSIRDY_BIT              1
 #define RCC_CSR_LSION_BIT               0
 
-#define RCC_CSR_LPWRRSTF                BIT(RCC_CSR_LPWRRSTF_BIT)
-#define RCC_CSR_WWDGRSTF                BIT(RCC_CSR_WWDGRSTF_BIT)
-#define RCC_CSR_IWDGRSTF                BIT(RCC_CSR_IWDGRSTF_BIT)
-#define RCC_CSR_SFTRSTF                 BIT(RCC_CSR_SFTRSTF_BIT)
-#define RCC_CSR_PORRSTF                 BIT(RCC_CSR_PORRSTF_BIT)
-#define RCC_CSR_PINRSTF                 BIT(RCC_CSR_PINRSTF_BIT)
-#define RCC_CSR_BORRSTF                 BIT(RCC_CSR_BORRSTF_BIT)
-#define RCC_CSR_RMVF                    BIT(RCC_CSR_RMVF_BIT)
-#define RCC_CSR_LSIRDY                  BIT(RCC_CSR_LSIRDY_BIT)
-#define RCC_CSR_LSION                   BIT(RCC_CSR_LSION_BIT)
+#define RCC_CSR_LPWRRSTF                (1U << RCC_CSR_LPWRRSTF_BIT)
+#define RCC_CSR_WWDGRSTF                (1U << RCC_CSR_WWDGRSTF_BIT)
+#define RCC_CSR_IWDGRSTF                (1U << RCC_CSR_IWDGRSTF_BIT)
+#define RCC_CSR_SFTRSTF                 (1U << RCC_CSR_SFTRSTF_BIT)
+#define RCC_CSR_PORRSTF                 (1U << RCC_CSR_PORRSTF_BIT)
+#define RCC_CSR_PINRSTF                 (1U << RCC_CSR_PINRSTF_BIT)
+#define RCC_CSR_BORRSTF                 (1U << RCC_CSR_BORRSTF_BIT)
+#define RCC_CSR_RMVF                    (1U << RCC_CSR_RMVF_BIT)
+#define RCC_CSR_LSIRDY                  (1U << RCC_CSR_LSIRDY_BIT)
+#define RCC_CSR_LSION                   (1U << RCC_CSR_LSION_BIT)
 
 /* Spread spectrum clock generation register */
 
 #define RCC_SSCGR_SSCGEN_BIT            31
 #define RCC_SSCGR_SPREADSEL_BIT         30
 
-#define RCC_SSCGR_SSCGEN                BIT(RCC_SSCGR_SSCGEN_BIT)
-#define RCC_SSCGR_SPREADSEL             BIT(RCC_SSCGR_SPREADSEL_BIT)
+#define RCC_SSCGR_SSCGEN                (1U << RCC_SSCGR_SSCGEN_BIT)
+#define RCC_SSCGR_SPREADSEL             (1U << RCC_SSCGR_SPREADSEL_BIT)
 #define RCC_SSCGR_SPREADSEL_CENTER      (0x0 << RCC_SSCGR_SPREADSEL_BIT)
 #define RCC_SSCGR_SPREADSEL_DOWN        (0x1 << RCC_SSCGR_SPREADSEL_BIT)
 #define RCC_SSCGR_INCSTEP               (0xFFF << 16)