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| author | Marti Bolivar <mbolivar@leaflabs.com> | 2012-06-01 03:05:56 -0400 |
|---|---|---|
| committer | Marti Bolivar <mbolivar@leaflabs.com> | 2012-06-01 03:05:56 -0400 |
| commit | 5befb0826a1ff77994c55f42cd73ccf0905a5ce0 (patch) | |
| tree | c5c5d3f3eb024533ef134f22cd5f94e67bbd2fcf /libmaple/stm32f1 | |
| parent | 33a2fff2fc60ea0e6938d72c81812b2afb3bfb0e (diff) | |
| download | librambutan-5befb0826a1ff77994c55f42cd73ccf0905a5ce0.tar.gz librambutan-5befb0826a1ff77994c55f42cd73ccf0905a5ce0.zip | |
libmaple/stm32.h: Add STM32_TIMER_MASK, STM32_HAVE_TIMER.
Feature-test macros for dealing with the fact that timer support has
holes. STM32_TIMER_MASK is a bitmask where bit n is set when TIMERn is
present. STM32_HAVE_TIMER(n) just tests whether bit n is set in
STM32_TIMER_MASK.
This is necessary because e.g. the STM32F100RB has timers 1-4, 6, 7,
and 15-17. Because of this, the usual STM32_NR_whatever won't work,
and we use a bitmask instead.
For F1 performance line (F103s), STM32_TIMER_MASK can be derived from
the density. For F1 value line, I'm not as sure, so just add it for
the single MCU we support (the STM32F100RB). Same story for F2: add it
for the STM32F207IC. We can fix this up later if necessary.
Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
Diffstat (limited to 'libmaple/stm32f1')
| -rw-r--r-- | libmaple/stm32f1/include/series/stm32.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/libmaple/stm32f1/include/series/stm32.h b/libmaple/stm32f1/include/series/stm32.h index e01c494..59205c3 100644 --- a/libmaple/stm32f1/include/series/stm32.h +++ b/libmaple/stm32f1/include/series/stm32.h @@ -94,6 +94,7 @@ extern "C" { #elif defined(MCU_STM32F100RB) # define STM32_F1_LINE STM32_F1_LINE_VALUE # define STM32_NR_GPIO_PORTS 4 +# define STM32_TIMER_MASK 0x380DE /* Timers: 1-4, 6, 7, 15-17. */ # define STM32_SRAM_END ((void*)0x20002000) # define STM32_MEDIUM_DENSITY @@ -112,9 +113,16 @@ extern "C" { # ifdef STM32_MEDIUM_DENSITY # define STM32_NR_INTERRUPTS 43 +# define STM32_TIMER_MASK 0x1E /* TIMER1--TIMER4 */ # define STM32_HAVE_FSMC 0 # elif defined(STM32_HIGH_DENSITY) # define STM32_NR_INTERRUPTS 60 +# define STM32_TIMER_MASK 0x1FE /* TIMER1--TIMER8 */ +# define STM32_HAVE_FSMC 1 +# endif +# elif defined(STM32_XL_DENSITY) +# define STM32_NR_INTERRUPTS 60 +# define STM32_TIMER_MASK 0x7FFE /* TIMER1--TIMER14 */ # define STM32_HAVE_FSMC 1 # endif |