Merge branch 'wip-family-support'

Merge the long-lived (too long; future changes like these will need to
proceed more incrementally) development branch of libmaple, containing
experimental STM32F2 and STM32F1 value line support, into master.

This required many changes to the structure of the library. The most
important structural reorganizations occurred in:

- 954f9e5: moves public headers to include directories
- 3efa313: uses "series" instead of "family"
- c0d60e3: adds board files to the build system, to make it easier to
  add new boards
- 096d86c: adds build logic for targeting different STM32 series
  (e.g. STM32F1, STM32F2)

This last commit in particular (096d86c) is the basis for the
repartitioning of libmaple into portable sections, which work on all
supported MCUs, and nonportable sections, which are segregated into
separate directories and contain all series-specific code. Moving
existing STM32F1-only code into libmaple/stm32f1 and wirish/stm32f1,
along with adding equivalents under .../stm32f2 directories, was the
principal project of this branch.

Important API changes occur in several places. Existing code is still
expected to work on STM32F1 targets, but there have been many
deprecations. A detailed changelog explaining the situation needs to
be prepared.

F2 and F1 value line support is not complete; the merge is proceeding
prematurely in this respect. We've been getting more libmaple patches
from the community lately, and I'm worried that the merge conflicts
with the old tree structure will become painful to manage.

Conflicts:
	Makefile

Resolved Makefile conflicts manually; this required propagating
-Xlinker usage into support/make/target-config.mk.

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

2 files changed, 377 insertions, 0 deletions

diff --git a/libmaple/stm32f1/performance/isrs.S b/libmaple/stm32f1/performance/isrs.S
new file mode 100644
index 0000000..a8f0709
--- /dev/null
+++ b/libmaple/stm32f1/performance/isrs.S
@@ -0,0 +1,261 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/* STM32F1 performance line ISR weak declarations */
+
+	.thumb
+
+/* Default handler for all non-overridden interrupts and exceptions */
+	.globl	__default_handler
+	.type	__default_handler, %function
+
+__default_handler:
+	b .
+
+	.weak	__exc_nmi
+	.globl	__exc_nmi
+	.set	__exc_nmi, __default_handler
+	.weak	__exc_hardfault
+	.globl	__exc_hardfault
+	.set	__exc_hardfault, __default_handler
+	.weak	__exc_memmanage
+	.globl	__exc_memmanage
+	.set	__exc_memmanage, __default_handler
+	.weak	__exc_busfault
+	.globl	__exc_busfault
+	.set	__exc_busfault, __default_handler
+	.weak	__exc_usagefault
+	.globl	__exc_usagefault
+	.set	__exc_usagefault, __default_handler
+	.weak	__stm32reservedexception7
+	.globl	__stm32reservedexception7
+	.set	__stm32reservedexception7, __default_handler
+	.weak	__stm32reservedexception8
+	.globl	__stm32reservedexception8
+	.set	__stm32reservedexception8, __default_handler
+	.weak	__stm32reservedexception9
+	.globl	__stm32reservedexception9
+	.set	__stm32reservedexception9, __default_handler
+	.weak	__stm32reservedexception10
+	.globl	__stm32reservedexception10
+	.set	__stm32reservedexception10, __default_handler
+	.weak	__exc_svc
+	.globl	__exc_svc
+	.set	__exc_svc, __default_handler
+	.weak	__exc_debug_monitor
+	.globl	__exc_debug_monitor
+	.set	__exc_debug_monitor, __default_handler
+	.weak	__stm32reservedexception13
+	.globl	__stm32reservedexception13
+	.set	__stm32reservedexception13, __default_handler
+	.weak	__exc_pendsv
+	.globl	__exc_pendsv
+	.set	__exc_pendsv, __default_handler
+	.weak	__exc_systick
+	.globl	__exc_systick
+	.set	__exc_systick, __default_handler
+	.weak	__irq_wwdg
+	.globl	__irq_wwdg
+	.set	__irq_wwdg, __default_handler
+	.weak	__irq_pvd
+	.globl	__irq_pvd
+	.set	__irq_pvd, __default_handler
+	.weak	__irq_tamper
+	.globl	__irq_tamper
+	.set	__irq_tamper, __default_handler
+	.weak	__irq_rtc
+	.globl	__irq_rtc
+	.set	__irq_rtc, __default_handler
+	.weak	__irq_flash
+	.globl	__irq_flash
+	.set	__irq_flash, __default_handler
+	.weak	__irq_rcc
+	.globl	__irq_rcc
+	.set	__irq_rcc, __default_handler
+	.weak	__irq_exti0
+	.globl	__irq_exti0
+	.set	__irq_exti0, __default_handler
+	.weak	__irq_exti1
+	.globl	__irq_exti1
+	.set	__irq_exti1, __default_handler
+	.weak	__irq_exti2
+	.globl	__irq_exti2
+	.set	__irq_exti2, __default_handler
+	.weak	__irq_exti3
+	.globl	__irq_exti3
+	.set	__irq_exti3, __default_handler
+	.weak	__irq_exti4
+	.globl	__irq_exti4
+	.set	__irq_exti4, __default_handler
+	.weak	__irq_dma1_channel1
+	.globl	__irq_dma1_channel1
+	.set	__irq_dma1_channel1, __default_handler
+	.weak	__irq_dma1_channel2
+	.globl	__irq_dma1_channel2
+	.set	__irq_dma1_channel2, __default_handler
+	.weak	__irq_dma1_channel3
+	.globl	__irq_dma1_channel3
+	.set	__irq_dma1_channel3, __default_handler
+	.weak	__irq_dma1_channel4
+	.globl	__irq_dma1_channel4
+	.set	__irq_dma1_channel4, __default_handler
+	.weak	__irq_dma1_channel5
+	.globl	__irq_dma1_channel5
+	.set	__irq_dma1_channel5, __default_handler
+	.weak	__irq_dma1_channel6
+	.globl	__irq_dma1_channel6
+	.set	__irq_dma1_channel6, __default_handler
+	.weak	__irq_dma1_channel7
+	.globl	__irq_dma1_channel7
+	.set	__irq_dma1_channel7, __default_handler
+	.weak	__irq_adc
+	.globl	__irq_adc
+	.set	__irq_adc, __default_handler
+	.weak	__irq_usb_hp_can_tx
+	.globl	__irq_usb_hp_can_tx
+	.set	__irq_usb_hp_can_tx, __default_handler
+	.weak	__irq_usb_lp_can_rx0
+	.globl	__irq_usb_lp_can_rx0
+	.set	__irq_usb_lp_can_rx0, __default_handler
+	.weak	__irq_can_rx1
+	.globl	__irq_can_rx1
+	.set	__irq_can_rx1, __default_handler
+	.weak	__irq_can_sce
+	.globl	__irq_can_sce
+	.set	__irq_can_sce, __default_handler
+	.weak	__irq_exti9_5
+	.globl	__irq_exti9_5
+	.set	__irq_exti9_5, __default_handler
+	.weak	__irq_tim1_brk
+	.globl	__irq_tim1_brk
+	.set	__irq_tim1_brk, __default_handler
+	.weak	__irq_tim1_up
+	.globl	__irq_tim1_up
+	.set	__irq_tim1_up, __default_handler
+	.weak	__irq_tim1_trg_com
+	.globl	__irq_tim1_trg_com
+	.set	__irq_tim1_trg_com, __default_handler
+	.weak	__irq_tim1_cc
+	.globl	__irq_tim1_cc
+	.set	__irq_tim1_cc, __default_handler
+	.weak	__irq_tim2
+	.globl	__irq_tim2
+	.set	__irq_tim2, __default_handler
+	.weak	__irq_tim3
+	.globl	__irq_tim3
+	.set	__irq_tim3, __default_handler
+	.weak	__irq_tim4
+	.globl	__irq_tim4
+	.set	__irq_tim4, __default_handler
+	.weak	__irq_i2c1_ev
+	.globl	__irq_i2c1_ev
+	.set	__irq_i2c1_ev, __default_handler
+	.weak	__irq_i2c1_er
+	.globl	__irq_i2c1_er
+	.set	__irq_i2c1_er, __default_handler
+	.weak	__irq_i2c2_ev
+	.globl	__irq_i2c2_ev
+	.set	__irq_i2c2_ev, __default_handler
+	.weak	__irq_i2c2_er
+	.globl	__irq_i2c2_er
+	.set	__irq_i2c2_er, __default_handler
+	.weak	__irq_spi1
+	.globl	__irq_spi1
+	.set	__irq_spi1, __default_handler
+	.weak	__irq_spi2
+	.globl	__irq_spi2
+	.set	__irq_spi2, __default_handler
+	.weak	__irq_usart1
+	.globl	__irq_usart1
+	.set	__irq_usart1, __default_handler
+	.weak	__irq_usart2
+	.globl	__irq_usart2
+	.set	__irq_usart2, __default_handler
+	.weak	__irq_usart3
+	.globl	__irq_usart3
+	.set	__irq_usart3, __default_handler
+	.weak	__irq_exti15_10
+	.globl	__irq_exti15_10
+	.set	__irq_exti15_10, __default_handler
+	.weak	__irq_rtcalarm
+	.globl	__irq_rtcalarm
+	.set	__irq_rtcalarm, __default_handler
+	.weak	__irq_usbwakeup
+	.globl	__irq_usbwakeup
+	.set	__irq_usbwakeup, __default_handler
+#if defined (STM32_HIGH_DENSITY)
+	.weak	__irq_tim8_brk
+	.globl	__irq_tim8_brk
+	.set	__irq_tim8_brk, __default_handler
+	.weak	__irq_tim8_up
+	.globl	__irq_tim8_up
+	.set	__irq_tim8_up, __default_handler
+	.weak	__irq_tim8_trg_com
+	.globl	__irq_tim8_trg_com
+	.set	__irq_tim8_trg_com, __default_handler
+	.weak	__irq_tim8_cc
+	.globl	__irq_tim8_cc
+	.set	__irq_tim8_cc, __default_handler
+	.weak	__irq_adc3
+	.globl	__irq_adc3
+	.set	__irq_adc3, __default_handler
+	.weak	__irq_fsmc
+	.globl	__irq_fsmc
+	.set	__irq_fsmc, __default_handler
+	.weak	__irq_sdio
+	.globl	__irq_sdio
+	.set	__irq_sdio, __default_handler
+	.weak	__irq_tim5
+	.globl	__irq_tim5
+	.set	__irq_tim5, __default_handler
+	.weak	__irq_spi3
+	.globl	__irq_spi3
+	.set	__irq_spi3, __default_handler
+	.weak	__irq_uart4
+	.globl	__irq_uart4
+	.set	__irq_uart4, __default_handler
+	.weak	__irq_uart5
+	.globl	__irq_uart5
+	.set	__irq_uart5, __default_handler
+	.weak	__irq_tim6
+	.globl	__irq_tim6
+	.set	__irq_tim6, __default_handler
+	.weak	__irq_tim7
+	.globl	__irq_tim7
+	.set	__irq_tim7, __default_handler
+	.weak	__irq_dma2_channel1
+	.globl	__irq_dma2_channel1
+	.set	__irq_dma2_channel1, __default_handler
+	.weak	__irq_dma2_channel2
+	.globl	__irq_dma2_channel2
+	.set	__irq_dma2_channel2, __default_handler
+	.weak	__irq_dma2_channel3
+	.globl	__irq_dma2_channel3
+	.set	__irq_dma2_channel3, __default_handler
+	.weak	__irq_dma2_channel4_5
+	.globl	__irq_dma2_channel4_5
+	.set	__irq_dma2_channel4_5, __default_handler
+#endif /* STM32_HIGH_DENSITY */
diff --git a/libmaple/stm32f1/performance/vector_table.S b/libmaple/stm32f1/performance/vector_table.S
new file mode 100644
index 0000000..b489b94
--- /dev/null
+++ b/libmaple/stm32f1/performance/vector_table.S
@@ -0,0 +1,116 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/* STM32F1 performance line vector table */
+
+	.section	".stm32.interrupt_vector"
+
+	.globl	__stm32_vector_table
+	.type	__stm32_vector_table, %object
+
+__stm32_vector_table:
+/* CM3 core interrupts */
+	.long	__msp_init
+	.long	__exc_reset
+	.long	__exc_nmi
+	.long	__exc_hardfault
+	.long	__exc_memmanage
+	.long	__exc_busfault
+	.long	__exc_usagefault
+	.long	__stm32reservedexception7
+	.long	__stm32reservedexception8
+	.long	__stm32reservedexception9
+	.long	__stm32reservedexception10
+	.long	__exc_svc
+	.long	__exc_debug_monitor
+	.long	__stm32reservedexception13
+	.long	__exc_pendsv
+	.long	__exc_systick
+/* Peripheral interrupts */
+	.long	__irq_wwdg
+	.long	__irq_pvd
+	.long	__irq_tamper
+	.long	__irq_rtc
+	.long	__irq_flash
+	.long	__irq_rcc
+	.long	__irq_exti0
+	.long	__irq_exti1
+	.long	__irq_exti2
+	.long	__irq_exti3
+	.long	__irq_exti4
+	.long	__irq_dma1_channel1
+	.long	__irq_dma1_channel2
+	.long	__irq_dma1_channel3
+	.long	__irq_dma1_channel4
+	.long	__irq_dma1_channel5
+	.long	__irq_dma1_channel6
+	.long	__irq_dma1_channel7
+	.long	__irq_adc
+	.long	__irq_usb_hp_can_tx
+	.long	__irq_usb_lp_can_rx0
+	.long	__irq_can_rx1
+	.long	__irq_can_sce
+	.long	__irq_exti9_5
+	.long	__irq_tim1_brk
+	.long	__irq_tim1_up
+	.long	__irq_tim1_trg_com
+	.long	__irq_tim1_cc
+	.long	__irq_tim2
+	.long	__irq_tim3
+	.long	__irq_tim4
+	.long	__irq_i2c1_ev
+	.long	__irq_i2c1_er
+	.long	__irq_i2c2_ev
+	.long	__irq_i2c2_er
+	.long	__irq_spi1
+	.long	__irq_spi2
+	.long	__irq_usart1
+	.long	__irq_usart2
+	.long	__irq_usart3
+	.long	__irq_exti15_10
+	.long	__irq_rtcalarm
+	.long	__irq_usbwakeup
+#if defined (STM32_HIGH_DENSITY)
+	.long	__irq_tim8_brk
+	.long	__irq_tim8_up
+	.long	__irq_tim8_trg_com
+	.long	__irq_tim8_cc
+	.long	__irq_adc3
+	.long	__irq_fsmc
+	.long	__irq_sdio
+	.long	__irq_tim5
+	.long	__irq_spi3
+	.long	__irq_uart4
+	.long	__irq_uart5
+	.long	__irq_tim6
+	.long	__irq_tim7
+	.long	__irq_dma2_channel1
+	.long	__irq_dma2_channel2
+	.long	__irq_dma2_channel3
+	.long	__irq_dma2_channel4_5
+#endif /* STM32_HIGH_DENSITY */
+
+	.size	__stm32_vector_table, . - __stm32_vector_table