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| author | Perry Hung <iperry@alum.mit.edu> | 2010-04-24 04:16:47 -0400 |
|---|---|---|
| committer | Perry Hung <iperry@alum.mit.edu> | 2010-04-24 04:16:47 -0400 |
| commit | e608ac87afd39ed837ad3518bec652e3fd6eeffa (patch) | |
| tree | 232efb6fb9cd55a57a6632bd88218bc93e540844 /libmaple/rcc.h | |
| parent | cb3284fad5347fc9622a170d6e3cd870fd9e2846 (diff) | |
| download | librambutan-e608ac87afd39ed837ad3518bec652e3fd6eeffa.tar.gz librambutan-e608ac87afd39ed837ad3518bec652e3fd6eeffa.zip | |
Initial SPI implementation.
Squashed commit of the following:
commit b41eb846ca60559cff242d0c550699eb8f309909
Author: Perry Hung <iperry@alum.mit.edu>
Date: Sat Apr 24 04:09:16 2010 -0400
Turn the other peripherals back on. Not extensively tested for
interactions between peripherals.
commit bf4fc3bf6bc02342ae508b52fb4515d361d626f6
Author: Perry Hung <iperry@alum.mit.edu>
Date: Sat Apr 24 03:16:35 2010 -0400
Upper level libmaple interface
Added a C++ HardwareSPI class to access the SPI interface. See
HardwareSPI.cpp and HardwareSPI.h for documentation.
commit 17e0e5edde60e9bf2aa4d52173ad7d47d6d6da75
Author: Perry Hung <iperry@alum.mit.edu>
Date: Thu Apr 22 02:36:01 2010 -0400
Initial SPI Polling implementation.
Initial commit of a polling-based SPI driver. The driver is limited to
synchronous, blocking sends and a 8-bit data frame format. Tested on
SPI1 and SPI2.
Other peripherals are temporarily disabled, and the rx function
is untested until I find a good peripheral to test everything on.
Diffstat (limited to 'libmaple/rcc.h')
| -rw-r--r-- | libmaple/rcc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/libmaple/rcc.h b/libmaple/rcc.h index 8f786ee..9973bca 100644 --- a/libmaple/rcc.h +++ b/libmaple/rcc.h @@ -100,6 +100,10 @@ #define RCC_APB1ENR_TIM4EN BIT(2) #define RCC_APB1ENR_USART2EN BIT(17) #define RCC_APB1ENR_USART3EN BIT(18) +#define RCC_APB1ENR_SPI2EN BIT(14) + +#define rcc_enable_clk_spi1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_SPI1EN) +#define rcc_enable_clk_spi2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_SPI2EN) #define rcc_enable_clk_timer1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_TIM1EN) #define rcc_enable_clk_timer2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM2EN) |