Fix improper interrupt clearing

Interrupts should be cleared by writing to the interrupt clear-enable
register (ICER). This commit fixes an improper read-modify-write on
NVIC_ICER[n] that incorrectly cleared interrupt-enable bits on
non-designated channels.

1 files changed, 4 insertions, 14 deletions

diff --git a/libmaple/nvic.c b/libmaple/nvic.c
index 60e7eac..b911e35 100644
--- a/libmaple/nvic.c
+++ b/libmaple/nvic.c
@@ -42,13 +42,8 @@ void nvic_set_vector_table(uint32 addr, uint32 offset) {
  *  @param n interrupt number
  */
 void nvic_irq_enable(uint32 n) {
-    if (n < 32) {
-        REG_SET_BIT(NVIC_ISER0, n);
-    } else if(n < 64) {
-        REG_SET_BIT(NVIC_ISER1, n - 32);
-    } else {
-        REG_SET_BIT(NVIC_ISER2, n - 64);
-    }
+    uint32 *iser = &((uint32*)NVIC_ISER0)[(n/32)];
+    __write(iser, BIT(n % 32));
 }
 
 /**
@@ -56,13 +51,8 @@ void nvic_irq_enable(uint32 n) {
  *  @param n interrupt number
  */
 void nvic_irq_disable(uint32 n) {
-    if (n < 32) {
-        REG_SET_BIT(NVIC_ICER0, n);
-    } else if(n < 64) {
-        REG_SET_BIT(NVIC_ICER1, n - 32);
-    } else {
-        REG_SET_BIT(NVIC_ICER2, n - 64);
-    }
+    uint32 *icer = &((uint32*)NVIC_ICER0)[(n/32)];
+    __write(icer, BIT(n % 32));
 }
 
 void nvic_irq_disable_all(void) {