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author | Marti Bolivar <mbolivar@leaflabs.com> | 2011-02-15 22:29:45 -0500 |
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committer | Marti Bolivar <mbolivar@leaflabs.com> | 2011-02-16 01:17:21 -0500 |
commit | 2764748208816043a3149eae3a433d02325a1a36 (patch) | |
tree | cc5afb0af0c6f1d2282db08d3dad1dae9b4d33e6 /libmaple/nvic.c | |
parent | 1fb0e0d727089e23d4b30e1efba5410dc4b4da14 (diff) | |
parent | 620740bf1986311041a40bd2992d1b549f84b2ba (diff) | |
download | librambutan-2764748208816043a3149eae3a433d02325a1a36.tar.gz librambutan-2764748208816043a3149eae3a433d02325a1a36.zip |
Merge branch 'nzmichaelh-master' into master.
This provides DMA, IWDG, PWR, and BKP support, and fixes several bugs.
Conflicts:
libmaple/adc.h
libmaple/libmaple.h
libmaple/ring_buffer.h
Diffstat (limited to 'libmaple/nvic.c')
-rw-r--r-- | libmaple/nvic.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/libmaple/nvic.c b/libmaple/nvic.c index fc77054..b1da605 100644 --- a/libmaple/nvic.c +++ b/libmaple/nvic.c @@ -53,15 +53,20 @@ void nvic_irq_disable(uint32 n) { } void nvic_irq_disable_all(void) { - short n; - for(n=0; n<65; n++) { - nvic_irq_disable(n); - } + /* Each ICER register contains 1 bit per interrupt. Writing a 1 + to that bit disables the corresponding interrupt. So each of + the following lines disables up to 32 interrupts at a time. + Since low, medium, and high-density devices all have less than + 64 interrupts, this suffices. */ + /* TODO: fix for connectivity line: __write(NVIC_ICER2,1), + requires connectivity line support in libmaple.h */ + __write(NVIC_ICER0, 0xFFFFFFFF); + __write(NVIC_ICER1, 0xFFFFFFFF); } /** - * @brief Initialice the NVIC at address addr - * @param addr Address to set the vector table at + * @brief Initialize the NVIC according to VECT_TAB_FLASH, + * VECT_TAB_RAM, or VECT_TAB_BASE. */ void nvic_init(void) { #ifdef VECT_TAB_FLASH |