Reverting commits between `git merge-head master refactor` and master.

This is a combination of 11 revert commits, and allows for a clean
merge of the work done in the refactor branch.

The combined commit messages follow.

Revert "Committing basic ring_buffer test."

This reverts commit 987fa5f433e0cd41b1621dad8b4e331cf82d49f3.

Revert "qa-slave-shield.cpp and test-session.cpp fixes for Mini and RET6 Edition."

This reverts commit cdd367bdd264c9e19180032c119850fbba2115ba.

Revert "Brought examples/ up to date; PIN_MAP bugfix for D24."

This reverts commit b4c2d4514c6d52cac8a649c5d5c24b68a3c0a416.

Revert "Separated GPIO config to a separate FSMC routine."

This reverts commit 744848ad0fc33eed66acc44e41c3c9d646c5b100.

Revert "Slightly faster RAM writes (6.5MHz)."

This reverts commit 8ba0b6bb065acb4aff26bc9c838de5f37515caf1.

Revert "FSMC working but slow (~6 MHz)."

This reverts commit 0dc9490cf4f4f10a23b08fef1728773f10c1b76a.

Revert "Maple Mini ERROR_LED_PIN fix."

This reverts commit 07d437706840901db1e09ff0ab88229c67c1fa8a.

Revert "Fixing USBSerial::read(void*, uint32) return value (thanks, Crenn!)"

This reverts commit 3ba7196712a5bfe4fe1166b6c34d49c3d7254568.

Revert "Trivial gpio_init() bugfix"

This reverts commit f6ce003bb935f26eeefa54acf7c2ae6afaabd871.

Revert "Trivial changes to test-session.cpp"

This reverts commit a32a37b121ac7e62660d2a83fe67c857fe705122.

Revert ".gitignore: Ignore cscope* files"

This reverts commit d8c72c17bd6d7416a0846e69f4f5ae5cb229d58e.

1 files changed, 81 insertions, 57 deletions

diff --git a/libmaple/fsmc.c b/libmaple/fsmc.c
index db77ff1..49526f4 100644
--- a/libmaple/fsmc.c
+++ b/libmaple/fsmc.c
@@ -31,58 +31,10 @@
 #include "gpio.h"
 #include "fsmc.h"
 
-void fsmc_init_gpios(void) {
-    /* Data lines... */
-    gpio_set_mode(GPIOD_BASE,  0, MODE_AF_OUTPUT_PP); /* D2 */
-    gpio_set_mode(GPIOD_BASE,  1, MODE_AF_OUTPUT_PP); /* D3 */
-    gpio_set_mode(GPIOD_BASE,  8, MODE_AF_OUTPUT_PP); /* D13 */
-    gpio_set_mode(GPIOD_BASE,  9, MODE_AF_OUTPUT_PP); /* D14 */
-    gpio_set_mode(GPIOD_BASE, 10, MODE_AF_OUTPUT_PP); /* D15 */
-    gpio_set_mode(GPIOD_BASE, 14, MODE_AF_OUTPUT_PP); /* D0 */
-    gpio_set_mode(GPIOD_BASE, 15, MODE_AF_OUTPUT_PP); /* D1 */
-    gpio_set_mode(GPIOE_BASE,  7, MODE_AF_OUTPUT_PP); /* D4 */
-    gpio_set_mode(GPIOE_BASE,  8, MODE_AF_OUTPUT_PP); /* D5 */
-    gpio_set_mode(GPIOE_BASE,  9, MODE_AF_OUTPUT_PP); /* D6 */
-    gpio_set_mode(GPIOE_BASE, 10, MODE_AF_OUTPUT_PP); /* D7 */
-    gpio_set_mode(GPIOE_BASE, 11, MODE_AF_OUTPUT_PP); /* D8 */
-    gpio_set_mode(GPIOE_BASE, 12, MODE_AF_OUTPUT_PP); /* D9 */
-    gpio_set_mode(GPIOE_BASE, 13, MODE_AF_OUTPUT_PP); /* D10 */
-    gpio_set_mode(GPIOE_BASE, 14, MODE_AF_OUTPUT_PP); /* D11 */
-    gpio_set_mode(GPIOE_BASE, 15, MODE_AF_OUTPUT_PP); /* D12 */
-
-    /* Address lines... */
-    gpio_set_mode(GPIOD_BASE, 11, MODE_AF_OUTPUT_PP); /* A16 */
-    gpio_set_mode(GPIOD_BASE, 12, MODE_AF_OUTPUT_PP); /* A17 */
-    gpio_set_mode(GPIOD_BASE, 13, MODE_AF_OUTPUT_PP); /* A18 */
-    gpio_set_mode(GPIOF_BASE,  0, MODE_AF_OUTPUT_PP); /* A0 */
-    gpio_set_mode(GPIOF_BASE,  1, MODE_AF_OUTPUT_PP); /* A1 */
-    gpio_set_mode(GPIOF_BASE,  2, MODE_AF_OUTPUT_PP); /* A2 */
-    gpio_set_mode(GPIOF_BASE,  3, MODE_AF_OUTPUT_PP); /* A3 */
-    gpio_set_mode(GPIOF_BASE,  4, MODE_AF_OUTPUT_PP); /* A4 */
-    gpio_set_mode(GPIOF_BASE,  5, MODE_AF_OUTPUT_PP); /* A5 */
-    gpio_set_mode(GPIOF_BASE, 12, MODE_AF_OUTPUT_PP); /* A6 */
-    gpio_set_mode(GPIOF_BASE, 13, MODE_AF_OUTPUT_PP); /* A7 */
-    gpio_set_mode(GPIOF_BASE, 14, MODE_AF_OUTPUT_PP); /* A8 */
-    gpio_set_mode(GPIOF_BASE, 15, MODE_AF_OUTPUT_PP); /* A9 */
-    gpio_set_mode(GPIOG_BASE,  0, MODE_AF_OUTPUT_PP); /* A10 */
-    gpio_set_mode(GPIOG_BASE,  1, MODE_AF_OUTPUT_PP); /* A11 */
-    gpio_set_mode(GPIOG_BASE,  2, MODE_AF_OUTPUT_PP); /* A12 */
-    gpio_set_mode(GPIOG_BASE,  3, MODE_AF_OUTPUT_PP); /* A13 */
-    gpio_set_mode(GPIOG_BASE,  4, MODE_AF_OUTPUT_PP); /* A14 */
-    gpio_set_mode(GPIOG_BASE,  5, MODE_AF_OUTPUT_PP); /* A15 */
-
-    /* And control lines... */
-    gpio_set_mode(GPIOD_BASE,  4, MODE_AF_OUTPUT_PP); /* NOE */
-    gpio_set_mode(GPIOD_BASE,  5, MODE_AF_OUTPUT_PP); /* NWE */
-
-    gpio_set_mode(GPIOD_BASE,  7, MODE_AF_OUTPUT_PP); /* NE1 */
-    gpio_set_mode(GPIOG_BASE,  9, MODE_AF_OUTPUT_PP); /* NE2 */
-    gpio_set_mode(GPIOG_BASE, 10, MODE_AF_OUTPUT_PP); /* NE3 */
-    gpio_set_mode(GPIOG_BASE, 12, MODE_AF_OUTPUT_PP); /* NE4 */
-
-    gpio_set_mode(GPIOE_BASE,  0, MODE_AF_OUTPUT_PP); /* NBL0 */
-    gpio_set_mode(GPIOE_BASE,  1, MODE_AF_OUTPUT_PP); /* NBL1 */
-}
+/* These values determined for a particular SRAM chip by following the
+ * calculations in the ST FSMC application note. */
+#define FSMC_ADDSET 0x0
+#define FSMC_DATAST 0x3
 
 /* Sets up the FSMC peripheral to use the SRAM chip on the maple
  * native as an external segment of system memory space.  This
@@ -91,8 +43,57 @@ void fsmc_init_gpios(void) {
 void fsmc_native_sram_init(void) {
     FSMC_Bank *bank;
 
-    /* First set up the GPIO pins */
-    fsmc_init_gpios();
+    /* First we setup all the GPIO pins. */
+    /* Data lines... */
+    gpio_set_mode(GPIOD_BASE,  0, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE,  1, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE,  8, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE,  9, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 10, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 14, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 15, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE,  7, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE,  8, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE,  9, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 10, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 11, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 12, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 13, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 14, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOE_BASE, 15, MODE_AF_OUTPUT_PP);
+
+    /* Address lines... */
+    gpio_set_mode(GPIOD_BASE, 11, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 12, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOD_BASE, 13, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  0, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  1, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  2, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  3, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  4, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE,  5, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE, 12, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE, 13, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE, 14, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOF_BASE, 15, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  0, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  1, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  2, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  3, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  4, MODE_AF_OUTPUT_PP);
+    gpio_set_mode(GPIOG_BASE,  5, MODE_AF_OUTPUT_PP);
+
+    /* And control lines... */
+    gpio_set_mode(GPIOD_BASE,  4, MODE_AF_OUTPUT_PP);   // NOE
+    gpio_set_mode(GPIOD_BASE,  5, MODE_AF_OUTPUT_PP);   // NWE
+
+    gpio_set_mode(GPIOD_BASE,  7, MODE_AF_OUTPUT_PP);   // NE1
+    gpio_set_mode(GPIOG_BASE,  9, MODE_AF_OUTPUT_PP);   // NE2
+    gpio_set_mode(GPIOG_BASE, 10, MODE_AF_OUTPUT_PP);   // NE3
+    gpio_set_mode(GPIOG_BASE, 12, MODE_AF_OUTPUT_PP);   // NE4
+
+    gpio_set_mode(GPIOE_BASE,  0, MODE_AF_OUTPUT_PP);   // NBL0
+    gpio_set_mode(GPIOE_BASE,  1, MODE_AF_OUTPUT_PP);   // NBL1
 
     /* Next enable the clock */
     rcc_clk_enable(RCC_FSMC);
@@ -101,9 +102,32 @@ void fsmc_native_sram_init(void) {
      * channels are in "Bank 1" of the FSMC) */
     bank = (FSMC_Bank*)(FSMC1_BASE);
 
-    /* FIXME replace with macros from fsmc.h */
-    bank->BCR = (1 << 12) | (1 << 4) | 1;
-    bank->BTR = (3 << 8);
+    /* Everything else is cleared (BCR1) */
+    bank->BCR = 0x0000;
+
+    /* Memory type is SRAM */
+    bank->BCR &= ~(FSMC_BCR_MTYP);  // '00'
+
+    /* Databus width is 16bits */
+    bank->BCR &= ~(FSMC_BCR_MWID);
+    bank->BCR |= 0x1 << 4;          // '01'
+
+    /* Memory is nonmultiplexed */
+    bank->BCR &= ~(FSMC_BCR_MUXEN); // '0'
+
+    /* Need write enable to write to the chip */
+    bank->BCR |= FSMC_BCR_WREN;
+
+    /* Set ADDSET */
+    bank->BTR &= ~(FSMC_BTR_ADDSET);
+    bank->BTR |= (FSMC_BTR_ADDSET | FSMC_ADDSET);
+
+    /* Set DATAST */
+    bank->BTR &= ~(FSMC_BTR_DATAST);
+    bank->BTR |= (FSMC_BTR_DATAST | (FSMC_DATAST << 8));
+
+    /* Enable channel 1 */
+    bank->BCR |= FSMC_BCR_MBKEN;    // '1'
 
     /* (FSMC_BWTR3 not used for this simple configuration.) */
 }