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| author | Marti Bolivar <mbolivar@leaflabs.com> | 2011-03-12 23:28:53 -0500 |
|---|---|---|
| committer | Marti Bolivar <mbolivar@leaflabs.com> | 2011-03-12 23:28:53 -0500 |
| commit | e3fae0984dab4f1044ea3ffc1aa41b2df12370b2 (patch) | |
| tree | 9de019bb440aa7403da64b21d76428544ff6709d /libmaple/exti.c | |
| parent | 9579e9487c2039df38cc4fd0ac2846ef07cc0947 (diff) | |
| download | librambutan-e3fae0984dab4f1044ea3ffc1aa41b2df12370b2.tar.gz librambutan-e3fae0984dab4f1044ea3ffc1aa41b2df12370b2.zip | |
RCC refactor, bugfixes
Diffstat (limited to 'libmaple/exti.c')
| -rw-r--r-- | libmaple/exti.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/libmaple/exti.c b/libmaple/exti.c index 8177e1e..7f56712 100644 --- a/libmaple/exti.c +++ b/libmaple/exti.c @@ -98,14 +98,14 @@ void exti_attach_interrupt(afio_exti_num num, /* Set trigger mode */ switch (mode) { case EXTI_RISING: - *bb_peripv(&EXTI_BASE->RTSR, num) = 1; + *bb_perip(&EXTI_BASE->RTSR, num) = 1; break; case EXTI_FALLING: - *bb_peripv(&EXTI_BASE->FTSR, num) = 1; + *bb_perip(&EXTI_BASE->FTSR, num) = 1; break; case EXTI_RISING_FALLING: - *bb_peripv(&EXTI_BASE->RTSR, num) = 1; - *bb_peripv(&EXTI_BASE->FTSR, num) = 1; + *bb_perip(&EXTI_BASE->RTSR, num) = 1; + *bb_perip(&EXTI_BASE->FTSR, num) = 1; break; } @@ -113,7 +113,7 @@ void exti_attach_interrupt(afio_exti_num num, afio_exti_select(num, port); /* Unmask external interrupt request */ - *bb_peripv(&EXTI_BASE->IMR, num) = 1; + *bb_perip(&EXTI_BASE->IMR, num) = 1; /* Enable the interrupt line */ enable_irq(num); @@ -126,11 +126,11 @@ void exti_attach_interrupt(afio_exti_num num, */ void exti_detach_interrupt(afio_exti_num num) { /* First, mask the interrupt request */ - *bb_peripv(&EXTI_BASE->IMR, num) = 0; + *bb_perip(&EXTI_BASE->IMR, num) = 0; /* Then, clear the trigger selection registers */ - *bb_peripv(&EXTI_BASE->FTSR, num) = 0; - *bb_peripv(&EXTI_BASE->RTSR, num) = 0; + *bb_perip(&EXTI_BASE->FTSR, num) = 0; + *bb_perip(&EXTI_BASE->RTSR, num) = 0; /* Next, disable the IRQ, unless it's multiplexed and there are * other active external interrupts on the same IRQ line */ @@ -210,7 +210,7 @@ void __irq_exti15_10(void) { */ static inline void clear_pending(uint32 exti_num) { - *bb_peripv(&EXTI_BASE->PR, exti_num) = 1; + *bb_perip(&EXTI_BASE->PR, exti_num) = 1; /* If the pending bit is cleared as the last instruction in an ISR, * it won't actually be cleared in time and the ISR will fire again. * Insert a 2-cycle buffer to allow it to take effect. */ |