libmaple: Refactor ADC routines

ADC routines rewritten, support for ADC2, 3, added.

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

10 files changed, 389 insertions, 280 deletions

diff --git a/libmaple/adc.c b/libmaple/adc.c
index 3e6818c..adadc63 100644
--- a/libmaple/adc.c
+++ b/libmaple/adc.c
@@ -24,82 +24,85 @@
 
 /**
  * @brief Analog to digital converter routines
+ *
+ * IMPORTANT: maximum external impedance must be below 0.4kOhms for 1.5
+ * sample conversion time.
+ *
+ * At 55.5 cycles/sample, the external input impedance < 50kOhms.
+ *
+ * See stm32 manual RM008 for how to calculate this.
  */
 
 #include "libmaple.h"
 #include "rcc.h"
 #include "adc.h"
 
-/* The ADC input clock is generated from PCLK2/APB2 divided by a prescaler
- * and it must not exceed 14MHz.
- *
- * ADC1 and ADC2 are clocked by APB2
- *
- * 1) Power on by setting ADON in ADC_CR2
- * Conversion starts when ADON is set for a second time after some
- * time t > t_stab.
- *
- * Up to 16 selected conversion must be selected in ADC_SQRx
- *
- * Single conversion mode:
- * Set the ADON bit in the ADC_CR2 register
- * Once the conversion is complete:
- *  Converted data is stored in ADC_DR
- *  EOC flag is set
- *  Interrupt is generated if EOCIE is set
- *
- * Calibration:
- * Calibration is started by setting the CAL bit in the ADC_CR2 register.
- * Once calibration is over, the CAL bit is reset by hardware and normal
- * conversion can be performed. Calibrate at power-on.
- *
- * ALIGN in ADC_CR2 selects the alignment of data
- *
- * IMPORTANT: maximum external impedance must be below 0.4kOhms for 1.5
- * sample conversion time.
- *
- * At 55.5 cycles/sample, the external input impedance < 50kOhms*/
+adc_dev adc1 = {
+    .regs   = (adc_reg_map*)ADC1_BASE,
+    .clk_id = RCC_ADC1
+};
+const adc_dev *ADC1 = &adc1;
 
-void set_adc_smprx(adc_smp_rate smp_rate);
+adc_dev adc2 = {
+    .regs   = (adc_reg_map*)ADC2_BASE,
+    .clk_id = RCC_ADC2
+};
+const adc_dev *ADC2 = &adc2;
 
-void adc_init(adc_smp_rate smp_rate) {
-    rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6);
-    rcc_clk_enable(RCC_ADC1);
-    rcc_reset_dev(RCC_ADC1);
+#if NR_ADCS >= 3
+adc_dev adc3 = {
+    .regs   = (adc_reg_map*)ADC3_BASE,
+    .clk_id = RCC_ADC3
+};
+const adc_dev *ADC3 = &adc3;
+#endif
 
-    ADC_CR1  = 0;
-    /* Software triggers conversions */
-    ADC_CR2  = CR2_EXTSEL_SWSTART | CR2_EXTTRIG;
-    ADC_SQR1 = 0;
+static void adc_calibrate(adc_reg_map *regs);
 
-    /* Set the sample conversion time.  See note above for impedance
-       requirements. */
-    adc_set_sample_rate(smp_rate);
+/**
+ * @brief Initialize an ADC peripheral. Only supports software triggered
+ * conversions.
+ * @param dev ADC peripheral to initialize
+ * @param flags unused
+ */
+void adc_init(const adc_dev *dev, uint32 flags) {
+    /* Spin up the clocks */
+    rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6);
+    rcc_clk_enable(dev->clk_id);
+    rcc_reset_dev(dev->clk_id);
 
-    /* Enable the ADC */
-    CR2_ADON_BIT = 1;
+    /* Software triggers conversions, conversion on external events */
+    adc_set_extsel(dev->regs, 7);
+    adc_set_exttrig(dev->regs, 1);
 
-    /* Reset the calibration registers and then perform a reset */
-    CR2_RSTCAL_BIT = 1;
-    while(CR2_RSTCAL_BIT)
-        ;
+    /* Enable the ADC */
+    adc_enable(dev->regs);
 
-    CR2_CAL_BIT = 1;
-    while(CR2_CAL_BIT)
-        ;
+    /* Calibrate ADC */
+    adc_calibrate(dev->regs);
 }
 
-
-void adc_disable(void) {
-    CR2_ADON_BIT = 0;
+/**
+ * @brief Set external event select for regular group
+ * @param regs adc register map
+ * @param trigger event to select. See ADC_CR2 EXTSEL[2:0] bits.
+ */
+void adc_set_extsel(adc_reg_map *regs, uint8 trigger) {
+    uint32 cr2 = regs->CR2;
+    cr2 &= ~ADC_CR2_EXTSEL;
+    cr2 |= (trigger & 0x7) << 17;
+    regs->CR2 = cr2;
 }
 
-/* Turn the given sample rate into values for ADC_SMPRx.  (Don't
- * precompute in order to avoid wasting space).
- *
- * Don't call this during conversion!
+
+/**
+ * @brief Turn the given sample rate into values for ADC_SMPRx. Don't
+ * call this during conversion.
+ * @param regs adc register map
+ * @param smp_rate sample rate to set
+ * @see adc_smp_rate
  */
-void adc_set_sample_rate(adc_smp_rate smp_rate) {
+void adc_set_sample_rate(adc_reg_map *regs, adc_smp_rate smp_rate) {
     uint32 adc_smpr1_val = 0, adc_smpr2_val = 0;
     int i;
     for (i = 0; i < 10; i++) {
@@ -110,6 +113,23 @@ void adc_set_sample_rate(adc_smp_rate smp_rate) {
         /* ADC_SMPR2 determines sample time for channels [0,9] */
         adc_smpr2_val |= smp_rate << (i * 3);
     }
-    ADC_SMPR1 = adc_smpr1_val;
-    ADC_SMPR2 = adc_smpr2_val;
+    regs->SMPR1 = adc_smpr1_val;
+    regs->SMPR2 = adc_smpr2_val;
+}
+
+/**
+ * @brief Calibrate an ADC peripheral
+ * @param regs adc register map
+ */
+static void adc_calibrate(adc_reg_map *regs) {
+    __io uint32 *rstcal_bit = (__io uint32*)BITBAND_PERI(&(regs->CR2), 3);
+    __io uint32 *cal_bit = (__io uint32*)BITBAND_PERI(&(regs->CR2), 2);
+
+    *rstcal_bit = 1;
+    while (*rstcal_bit)
+        ;
+
+    *cal_bit = 1;
+    while (*cal_bit)
+        ;
 }
diff --git a/libmaple/adc.h b/libmaple/adc.h
index 976986f..4997d14 100644
--- a/libmaple/adc.h
+++ b/libmaple/adc.h
@@ -25,87 +25,168 @@
 /**
  *  @file adc.h
  *
- *  @brief Analog-to-Digital Conversion (ADC) routines.
+ *  @brief Analog-to-Digital Conversion (ADC) header.
  */
 
 #ifndef _ADC_H_
 #define _ADC_H_
 #include "util.h"
 
+#include "rcc.h"
+
 #ifdef __cplusplus
 extern "C"{
 #endif
 
-/* Notes:
- * The maximum input impedance on each channel MUST be below .4kohms,
- * or face the wrath of incorrect readings...
- * This can be changed at the expense of sample time... see datasheet
- *
- * Need to up the sample time if otherwise... see datasheet */
+typedef struct adc_reg_map {
+    __io uint32 SR;             ///< Status register
+    __io uint32 CR1;            ///< Control register 1
+    __io uint32 CR2;            ///< Control register 2
+    __io uint32 SMPR1;          ///< Sample time register 1
+    __io uint32 SMPR2;          ///< Sample time register 2
+    __io uint32 JOFR1;          ///< Injected channel data offset register 1
+    __io uint32 JOFR2;          ///< Injected channel data offset register 2
+    __io uint32 JOFR3;          ///< Injected channel data offset register 3
+    __io uint32 JOFR4;          ///< Injected channel data offset register 4
+    __io uint32 HTR;            ///< Watchdog high threshold register
+    __io uint32 LTR;            ///< Watchdog low threshold register
+    __io uint32 SQR1;           ///< Regular sequence register 1
+    __io uint32 SQR2;           ///< Regular sequence register 2
+    __io uint32 SQR3;           ///< Regular sequence register 3
+    __io uint32 JSQR;           ///< Injected sequence register
+    __io uint32 JDR1;           ///< Injected data register 1
+    __io uint32 JDR2;           ///< Injected data register 2
+    __io uint32 JDR3;           ///< Injected data register 3
+    __io uint32 JDR4;           ///< Injected data register 4
+    __io uint32 DR;             ///< Regular data register
+} adc_reg_map;
+
+typedef struct adc_dev {
+    adc_reg_map *regs;
+    rcc_clk_id clk_id;
+} adc_dev;
+
+extern const adc_dev *ADC1;
+extern const adc_dev *ADC2;
+#if NR_ADCS >= 3
+extern const adc_dev *ADC3;
+#endif
 
-/* TODO: We'll only use ADC1 for now.  See page 41 of the manual for
-   ADC2 and ADC3's real addresses.  */
+/*
+ * ADC peripheral base addresses
+ */
 #define ADC1_BASE                 0x40012400
-#define ADC2_BASE                 0x40012400
-#define ADC3_BASE                 0x40012400
-
-#define ADC_SR                   *(volatile uint32*)(ADC1_BASE + 0)
-#define ADC_CR1                  *(volatile uint32*)(ADC1_BASE + 0x4)
-#define ADC_CR2                  *(volatile uint32*)(ADC1_BASE + 0x8)
-#define ADC_SMPR1                *(volatile uint32*)(ADC1_BASE + 0xC)
-#define ADC_SMPR2                *(volatile uint32*)(ADC1_BASE + 0x10)
-#define ADC_SQR1                 *(volatile uint32*)(ADC1_BASE + 0x2C)
-#define ADC_SQR3                 *(volatile uint32*)(ADC1_BASE + 0x34)
-#define ADC_DR                   *(volatile uint32*)(ADC1_BASE + 0x4C)
-
-#define CR2_EXTSEL_SWSTART       (0xE << 16)
-#define CR2_RSTCAL               (BIT(3))
-#define CR2_EXTTRIG              (BIT(20))
-
-/* Bit banded bits  */
-#define CR2_ADON_BIT    *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0x8, 0))
-#define CR2_CAL_BIT     *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0x8, 2))
-#define CR2_RSTCAL_BIT  *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0x8, 3))
-#define CR2_SWSTART_BIT *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0x8, 22))
-#define SR_EOC_BIT      *(volatile uint32*)(BITBAND_PERI(ADC1_BASE+0, 1))
-/* (NR_ANALOG_PINS is board specific) */
+#define ADC2_BASE                 0x40012800
+#define ADC3_BASE                 0x40013C00
+
+/*
+ * Register bit definitions
+ */
+
+/* Status register */
+#define ADC_SR_AWD              BIT(0)
+#define ADC_SR_EOC              BIT(1)
+#define ADC_SR_JEOC             BIT(2)
+#define ADC_SR_JSTRT            BIT(3)
+#define ADC_SR_STRT             BIT(4)
+
+/* Control register 1 */
+#define ADC_CR1_AWDCH           (0x1F)
+#define ADC_CR1_EOCIE           BIT(5)
+#define ADC_CR1_AWDIE           BIT(6)
+#define ADC_CR1_JEOCIE          BIT(7)
+#define ADC_CR1_SCAN            BIT(8)
+#define ADC_CR1_AWDSGL          BIT(9)
+#define ADC_CR1_JAUTO           BIT(10)
+#define ADC_CR1_DISCEN          BIT(11)
+#define ADC_CR1_JDISCEN         BIT(12)
+#define ADC_CR1_DISCNUM         (0xE000)
+#define ADC_CR1_JAWDEN          BIT(22)
+#define ADC_CR1_AWDEN           BIT(23)
+
+/* Control register 2 */
+#define ADC_CR2_ADON            BIT(0)
+#define ADC_CR2_CONT            BIT(1)
+#define ADC_CR2_CAL             BIT(2)
+#define ADC_CR2_RSTCAL          BIT(3)
+#define ADC_CR2_DMA             BIT(8)
+#define ADC_CR2_ALIGN           BIT(11)
+#define ADC_CR2_JEXTSEL         (0x7000)
+#define ADC_CR2_JEXTTRIG        BIT(15)
+#define ADC_CR2_EXTSEL          (0xE0000)
+#define ADC_CR2_EXTTRIG         BIT(20)
+#define ADC_CR2_JSWSTART        BIT(21)
+#define ADC_CR2_SWSTART         BIT(22)
+#define ADC_CR2_TSEREFE         BIT(23)
+
+void adc_init(const adc_dev *dev, uint32 flags);
+void adc_set_extsel(adc_reg_map *regs, uint8 trigger);
 
 /** ADC per-sample conversion times, in ADC clock cycles */
 typedef enum {
-    ADC_SMPR_1_5,
-    ADC_SMPR_7_5,
-    ADC_SMPR_13_5,
-    ADC_SMPR_28_5,
-    ADC_SMPR_41_5,
-    ADC_SMPR_55_5,
-    ADC_SMPR_71_5,
-    ADC_SMPR_239_5
+    ADC_SMPR_1_5,               ///< 1.5 ADC cycles
+    ADC_SMPR_7_5,               ///< 7.5 ADC cycles
+    ADC_SMPR_13_5,              ///< 13.5 ADC cycles
+    ADC_SMPR_28_5,              ///< 28.5 ADC cycles
+    ADC_SMPR_41_5,              ///< 41.5 ADC cycles
+    ADC_SMPR_55_5,              ///< 55.5 ADC cycles
+    ADC_SMPR_71_5,              ///< 71.5 ADC cycles
+    ADC_SMPR_239_5              ///< 239.5 ADC cycles
 } adc_smp_rate;
 
-/** Initialize ADC1 to do one-shot conversions at the given sample
-    rate. */
-void adc_init(adc_smp_rate smp_rate);
-
-void adc_set_sample_rate(adc_smp_rate smp_rate);
-
-void adc_disable(void);
+void adc_set_sample_rate(adc_reg_map *regs, adc_smp_rate smp_rate);
 
 /**
- * Perform a single conversion on ADC[0-15].
- * PRECONDITIONS:
- *   adc initialized */
-static inline int adc_read(int channel) {
-    /* Set channel */
-    ADC_SQR3 = channel;
+ * @brief Perform a single synchronous software triggered conversion on a
+ * channel
+ * @param regs ADC register map
+ * @param channel channel to convert
+ * @return conversion result
+ */
+static inline uint32 adc_read(adc_reg_map *regs, uint8 channel) {
+    /* Set target channel */
+    regs->SQR3 = channel;
 
     /* Start the conversion */
-    CR2_SWSTART_BIT = 1;
+    regs->CR2 |= ADC_CR2_SWSTART;
 
     /* Wait for it to finish */
-    while(SR_EOC_BIT == 0)
+    while((regs->SR & ADC_SR_EOC) == 0)
         ;
 
-    return ADC_DR;
+    return regs->DR;
+}
+
+/**
+ * @brief Set external trigger conversion mode event for regular channels
+ * @param regs adc register map
+ * @param enable if 1, conversion on external events is enabled, 0 to disable
+ */
+static inline void adc_set_exttrig(adc_reg_map *regs, uint8 enable) {
+    __write(BITBAND_PERI(&(regs->CR2), 20), enable);
+}
+
+/**
+ * @brief Enable an adc peripheral
+ * @param regs register map of peripheral to enable
+ */
+static inline void adc_enable(adc_reg_map *regs) {
+    __write(BITBAND_PERI(&(regs->CR2), 0), 1);
+}
+
+/**
+ * @brief Disable an adc peripheral
+ * @param regs register map of peripheral to disable
+ */
+static inline void adc_disable(adc_reg_map *regs) {
+    __write(BITBAND_PERI(&(regs->CR2), 0), 0);
+}
+
+/**
+ * @brief Disable all ADCs
+ */
+static inline void adc_disable_all(void) {
+    adc_disable(ADC1->regs);
 }
 
 #ifdef __cplusplus
diff --git a/libmaple/libmaple.h b/libmaple/libmaple.h
index 02e27d3..4f9a71a 100644
--- a/libmaple/libmaple.h
+++ b/libmaple/libmaple.h
@@ -61,6 +61,9 @@
     /* Number of USART ports */
     #define NR_USART                  3
 
+    /* Number of ADCs */
+    #define NR_ADCS                   2
+
     /* Has an FSMC bus? */
     #define NR_FSMC                   0
 
@@ -109,6 +112,7 @@
     #define NR_BKP_REGS              42 /* TODO test on Native */
     #define NR_TIMERS                 8
     #define NR_USART                  5 /* NB: 4 and 5 are UART only */
+    #define NR_ADCS                   3
     #define NR_FSMC                   1
     #define NR_DAC_PINS               2
 
@@ -147,6 +151,7 @@
     #define NR_BKP_REGS   10    /* TODO test on Mini */
     #define NR_TIMERS     4
     #define NR_USART      3
+    #define NR_ADCS       2
     #define NR_FSMC       0
     #define NR_DAC_PINS   0
 
diff --git a/libmaple/rcc.c b/libmaple/rcc.c
index 6905c22..a9d7c96 100644
--- a/libmaple/rcc.c
+++ b/libmaple/rcc.c
@@ -54,6 +54,7 @@ static const struct rcc_dev_info rcc_dev_table[] = {
     [RCC_AFIO]   = { .clk_domain = APB2, .line_num = 0 },
     [RCC_ADC1]   = { .clk_domain = APB2, .line_num = 9 },
     [RCC_ADC2]   = { .clk_domain = APB2, .line_num = 10 },
+    [RCC_ADC3]   = { .clk_domain = APB2, .line_num = 15 },
     [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
     [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
     [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
diff --git a/libmaple/rcc.h b/libmaple/rcc.h
index 4b1f35d..5daca57 100644
--- a/libmaple/rcc.h
+++ b/libmaple/rcc.h
@@ -144,8 +144,10 @@ enum {
     RCC_PRESCALER_ADC
 };
 
-// RCC Devices
-enum {
+/*
+ * Identifies bus and clock line for a device
+ */
+typedef enum {
     RCC_GPIOA,
     RCC_GPIOB,
     RCC_GPIOC,
@@ -156,6 +158,7 @@ enum {
     RCC_AFIO,
     RCC_ADC1,
     RCC_ADC2,
+    RCC_ADC3,
     RCC_USART1,
     RCC_USART2,
     RCC_USART3,
@@ -175,7 +178,7 @@ enum {
     RCC_DAC,         // High-density devices only (Maple Native)
     RCC_DMA1,
     RCC_DMA2,        // High-density devices only (Maple Native)
-};
+} rcc_clk_id;
 
 
 void rcc_clk_init(uint32 sysclk_src, uint32 pll_src, uint32 pll_mul);
diff --git a/libmaple/util.c b/libmaple/util.c
index 135f005..11f9b34 100644
--- a/libmaple/util.c
+++ b/libmaple/util.c
@@ -48,7 +48,7 @@ void _fail(const char* file, int line, const char* exp) {
     timer_disable_all();
 
     /* Turn off ADC */
-    adc_disable();
+    adc_disable_all();
 
     /* Turn off all usarts */
     usart_disable_all();
diff --git a/libmaple/util.h b/libmaple/util.h
index 64782d9..63427cc 100644
--- a/libmaple/util.h
+++ b/libmaple/util.h
@@ -44,7 +44,8 @@
 /* Convert SRAM address */
 #define BITBAND_SRAM(a,b) ((BITBAND_SRAM_BASE+(a-BITBAND_SRAM_REF)*32+(b*4)))
 /* Convert PERI address */
-#define BITBAND_PERI(a,b) ((BITBAND_PERI_BASE+(a-BITBAND_PERI_REF)*32+(b*4)))
+#define BITBAND_PERI(a, b) ((BITBAND_PERI_BASE +                \
+                            ((uint32)a - BITBAND_PERI_REF) * 32 + (b * 4)))
 
 #define REG_SET(reg, val)         (*(volatile uint32*)(reg)  = (val))
 #define REG_SET_BIT(reg, bit)     (*(volatile uint32*)(reg) |= BIT(bit))
diff --git a/wirish/boards.h b/wirish/boards.h
index f8505ab..ac3a74d 100644
--- a/wirish/boards.h
+++ b/wirish/boards.h
@@ -51,18 +51,13 @@ enum {
     D92, D93, D94, D95, D96, D97, D98, D99, D100, D101, D102, D103, D104, D105,
     D106, D107, D108, D109, D110, D111, };
 
-/* Set of all possible analog pin names; not all boards have all these */
-enum {
-    ADC0, ADC1, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, ADC10, ADC11,
-    ADC12, ADC13, ADC14, ADC15, ADC16, ADC17, ADC18, ADC19, ADC20, };
-
 #define ADC_INVALID       0xFFFFFFFF
 
 /* Types used for the tables below */
 typedef struct PinMapping {
     GPIO_Port *port;
     uint32 pin;
-    uint32 adc;
+    uint32 adc_channel;
     TimerCCR timer_ccr;
     uint32 exti_port;
     timer_dev_num timer_num;
@@ -80,89 +75,89 @@ typedef struct PinMapping {
 
     static __attribute__ ((unused)) PinMapping PIN_MAP[NR_GPIO_PINS] = {
         /* D0/PA3 */
-        {GPIOA_BASE,  3,        ADC3, TIMER2_CH4_CCR,  EXTI_CONFIG_PORTA, TIMER2, 4},
+        {GPIOA_BASE,  3,           3, TIMER2_CH4_CCR, EXTI_CONFIG_PORTA, TIMER2, 4},
         /* D1/PA2 */
-        {GPIOA_BASE,  2,        ADC2, TIMER2_CH3_CCR,  EXTI_CONFIG_PORTA, TIMER2, 3},
+        {GPIOA_BASE,  2,           2, TIMER2_CH3_CCR, EXTI_CONFIG_PORTA, TIMER2, 3},
         /* D2/PA0 */
-        {GPIOA_BASE,  0,        ADC0, TIMER2_CH1_CCR,  EXTI_CONFIG_PORTA, TIMER2, 1},
+        {GPIOA_BASE,  0,           0, TIMER2_CH1_CCR, EXTI_CONFIG_PORTA, TIMER2, 1},
         /* D3/PA1 */
-        {GPIOA_BASE,  1,        ADC1, TIMER2_CH2_CCR,  EXTI_CONFIG_PORTA, TIMER2, 2},
+        {GPIOA_BASE,  1,           1, TIMER2_CH2_CCR, EXTI_CONFIG_PORTA, TIMER2, 2},
         /* D4/PB5 */
-        {GPIOB_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D5/PB6 */
-        {GPIOB_BASE,  6, ADC_INVALID, TIMER4_CH1_CCR,  EXTI_CONFIG_PORTB, TIMER4, 1},
+        {GPIOB_BASE,  6, ADC_INVALID, TIMER4_CH1_CCR, EXTI_CONFIG_PORTB, TIMER4, 1},
         /* D6/PA8 */
-        {GPIOA_BASE,  8, ADC_INVALID, TIMER1_CH1_CCR,  EXTI_CONFIG_PORTA, TIMER1, 1},
+        {GPIOA_BASE,  8, ADC_INVALID, TIMER1_CH1_CCR, EXTI_CONFIG_PORTA, TIMER1, 1},
         /* D7/PA9 */
-        {GPIOA_BASE,  9, ADC_INVALID, TIMER1_CH2_CCR,  EXTI_CONFIG_PORTA, TIMER1, 2},
+        {GPIOA_BASE,  9, ADC_INVALID, TIMER1_CH2_CCR, EXTI_CONFIG_PORTA, TIMER1, 2},
         /* D8/PA10 */
-        {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR,  EXTI_CONFIG_PORTA, TIMER1, 3},
+        {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR, EXTI_CONFIG_PORTA, TIMER1, 3},
         /* D9/PB7 */
-        {GPIOB_BASE,  7, ADC_INVALID, TIMER4_CH2_CCR,  EXTI_CONFIG_PORTB, TIMER4, 2},
+        {GPIOB_BASE,  7, ADC_INVALID, TIMER4_CH2_CCR, EXTI_CONFIG_PORTB, TIMER4, 2},
         /* D10/PA4 */
-        {GPIOA_BASE,  4,        ADC4,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  4,           4,              0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D11/PA7 */
-        {GPIOA_BASE,  7,        ADC7, TIMER3_CH2_CCR,  EXTI_CONFIG_PORTA, TIMER3, 2},
+        {GPIOA_BASE,  7,           7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA, TIMER3, 2},
         /* D12/PA6 */
-        {GPIOA_BASE,  6,        ADC6, TIMER3_CH1_CCR,  EXTI_CONFIG_PORTA, TIMER3, 1},
+        {GPIOA_BASE,  6,           6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA, TIMER3, 1},
         /* D13/PA5 */
-        {GPIOA_BASE,  5,        ADC5,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  5,           5,              0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D14/PB8 */
-        {GPIOB_BASE,  8, ADC_INVALID, TIMER4_CH3_CCR,  EXTI_CONFIG_PORTB, TIMER4, 3},
+        {GPIOB_BASE,  8, ADC_INVALID, TIMER4_CH3_CCR, EXTI_CONFIG_PORTB, TIMER4, 3},
 
         /* Little header */
 
         /* D15/PC0 */
-        {GPIOC_BASE,  0,       ADC10,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  0,          10,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D16/PC1 */
-        {GPIOC_BASE,  1,       ADC11,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  1,          11,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D17/PC2 */
-        {GPIOC_BASE,  2,       ADC12,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  2,          12,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D18/PC3 */
-        {GPIOC_BASE,  3,       ADC13,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  3,          13,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D19/PC4 */
-        {GPIOC_BASE,  4,       ADC14,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  4,          14,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D20/PC5 */
-        {GPIOC_BASE,  5,       ADC15,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  5,          15,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
 
         /* External header */
 
         /* D21/PC13 */
-        {GPIOC_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D22/PC14 */
-        {GPIOC_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D23/PC15 */
-        {GPIOC_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D24/PB9 */
-        {GPIOB_BASE,  9, ADC_INVALID, TIMER4_CH4_CCR,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE,  9, ADC_INVALID, TIMER4_CH4_CCR, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D25/PD2 */
-        {GPIOD_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D26/PC10 */
-        {GPIOC_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D27/PB0 */
-        {GPIOB_BASE,  0,        ADC8, TIMER3_CH3_CCR,  EXTI_CONFIG_PORTB, TIMER3, 3},
+        {GPIOB_BASE,  0,           8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB, TIMER3, 3},
         /* D28/PB1 */
-        {GPIOB_BASE,  1,        ADC9, TIMER3_CH4_CCR,  EXTI_CONFIG_PORTB, TIMER3, 4},
+        {GPIOB_BASE,  1,           9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB, TIMER3, 4},
         /* D29/PB10 */
-        {GPIOB_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D30/PB11 */
-        {GPIOB_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D31/PB12 */
-        {GPIOB_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D32/PB13 */
-        {GPIOB_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D33/PB14 */
-        {GPIOB_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D34/PB15 */
-        {GPIOB_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D35/PC6 */
-        {GPIOC_BASE,  6, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  6, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D36/PC7 */
-        {GPIOC_BASE,  7, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  7, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D37/PC8 */
-        {GPIOC_BASE,  8, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  8, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D38/PC9 (BUT) */
-        {GPIOC_BASE,  9, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID}
+        {GPIOC_BASE,  9, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID}
     };
 
     #define BOARD_INIT do {                           \
@@ -182,212 +177,212 @@ typedef struct PinMapping {
         /* Top header */
 
         /* D0/PB10 */
-        {GPIOB_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D1/PB2 */
-        {GPIOB_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D2/PB12 */
-        {GPIOB_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D3/PB13 */
-        {GPIOB_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D4/PB14 */
-        {GPIOB_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D5/PB15 */
-        {GPIOB_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D6/PC0 */
-        {GPIOC_BASE,  0,       ADC10,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  0,          10,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D7/PC1 */
-        {GPIOC_BASE,  1,       ADC11,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  1,          11,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D8/PC2 */
-        {GPIOC_BASE,  2,       ADC12,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  2,          12,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D9/PC3 */
-        {GPIOC_BASE,  3,       ADC13,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  3,          13,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D10/PC4 */
-        {GPIOC_BASE,  4,       ADC14,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  4,          14,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D11/PC5 */
-        {GPIOC_BASE,  5,       ADC15,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE,  5,          15,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D12/PC6 */
-        {GPIOC_BASE,  6, ADC_INVALID, TIMER8_CH1_CCR,  EXTI_CONFIG_PORTC,        TIMER8, 1},
+        {GPIOC_BASE,  6, ADC_INVALID, TIMER8_CH1_CCR, EXTI_CONFIG_PORTC,        TIMER8, 1},
         /* D13/PC7 */
-        {GPIOC_BASE,  7, ADC_INVALID, TIMER8_CH2_CCR,  EXTI_CONFIG_PORTC,        TIMER8, 2},
+        {GPIOC_BASE,  7, ADC_INVALID, TIMER8_CH2_CCR, EXTI_CONFIG_PORTC,        TIMER8, 2},
         /* D14/PC8 */
-        {GPIOC_BASE,  8, ADC_INVALID, TIMER8_CH3_CCR,  EXTI_CONFIG_PORTC,        TIMER8, 3},
+        {GPIOC_BASE,  8, ADC_INVALID, TIMER8_CH3_CCR, EXTI_CONFIG_PORTC,        TIMER8, 3},
         /* D15/PC9 */
-        {GPIOC_BASE,  9, ADC_INVALID, TIMER8_CH4_CCR,  EXTI_CONFIG_PORTC,        TIMER8, 4},
+        {GPIOC_BASE,  9, ADC_INVALID, TIMER8_CH4_CCR, EXTI_CONFIG_PORTC,        TIMER8, 4},
         /* D16/PC10 */
-        {GPIOC_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D17/PC11 */
-        {GPIOC_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D18/PC12 */
-        {GPIOC_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D19/PC13 */
-        {GPIOC_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D20/PC14 */
-        {GPIOC_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D21/PC15 */
-        {GPIOC_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        {GPIOC_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D22/PA8 */
-        {GPIOA_BASE,  8, ADC_INVALID, TIMER1_CH1_CCR,  EXTI_CONFIG_PORTA,        TIMER1, 1},
+        {GPIOA_BASE,  8, ADC_INVALID, TIMER1_CH1_CCR, EXTI_CONFIG_PORTA,        TIMER1, 1},
         /* D23/PA9 */
-        {GPIOA_BASE,  9, ADC_INVALID, TIMER1_CH2_CCR,  EXTI_CONFIG_PORTA,        TIMER1, 2},
+        {GPIOA_BASE,  9, ADC_INVALID, TIMER1_CH2_CCR, EXTI_CONFIG_PORTA,        TIMER1, 2},
         /* D24/PA10 */
-        {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR,  EXTI_CONFIG_PORTA,        TIMER1, 3},
+        {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR, EXTI_CONFIG_PORTA,        TIMER1, 3},
         /* D25/PB9 */
-        {GPIOB_BASE,  9, ADC_INVALID, TIMER4_CH4_CCR,  EXTI_CONFIG_PORTB,        TIMER4, 4},
+        {GPIOB_BASE,  9, ADC_INVALID, TIMER4_CH4_CCR, EXTI_CONFIG_PORTB,        TIMER4, 4},
 
         /* Bottom header */
 
         /* D26/PD2 */
-        {GPIOD_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D27/PD3 */
-        {GPIOD_BASE,  3, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  3, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D28/PD6 */
-        {GPIOD_BASE,  6, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  6, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D29/PG11 */
-        {GPIOG_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D30/PG12 */
-        {GPIOG_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D31/PG13 */
-        {GPIOG_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D32/PG14 */
-        {GPIOG_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D33/PG8 */
-        {GPIOG_BASE,  8, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  8, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D34/PG7 */
-        {GPIOG_BASE,  7, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  7, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D35/PG6 */
-        {GPIOG_BASE,  6, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  6, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D36/PB5 */
-        {GPIOB_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        {GPIOB_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D37/PB6 */
-        {GPIOB_BASE,  6, ADC_INVALID, TIMER4_CH1_CCR,  EXTI_CONFIG_PORTB,        TIMER4, 1},
+        {GPIOB_BASE,  6, ADC_INVALID, TIMER4_CH1_CCR, EXTI_CONFIG_PORTB,        TIMER4, 1},
         /* D38/PB7 */
-        {GPIOB_BASE,  7, ADC_INVALID, TIMER4_CH2_CCR,  EXTI_CONFIG_PORTB,        TIMER4, 2},
+        {GPIOB_BASE,  7, ADC_INVALID, TIMER4_CH2_CCR, EXTI_CONFIG_PORTB,        TIMER4, 2},
         /* D39/PF6 */
-        {GPIOF_BASE,  6,        ADC4,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  6,           4,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D40/PF7 */
-        {GPIOF_BASE,  7,        ADC5,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  7,           5,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D41/PF8 */
-        {GPIOF_BASE,  8,        ADC6,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  8,           6,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D42/PF9 */
-        {GPIOF_BASE,  9,        ADC7,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  9,           7,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D43/PF10 */
-        {GPIOF_BASE, 10,        ADC8,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 10,           8,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D44/PF11 */
-        {GPIOF_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D45/PB1 */
-        {GPIOB_BASE,  1,        ADC9, TIMER3_CH4_CCR,  EXTI_CONFIG_PORTB,        TIMER3, 4},
+        {GPIOB_BASE,  1,           9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB,        TIMER3, 4},
         /* D46/PB0 */
-        {GPIOB_BASE,  0,        ADC8, TIMER3_CH3_CCR,  EXTI_CONFIG_PORTB,        TIMER3, 3},
+        {GPIOB_BASE,  0,           8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB,        TIMER3, 3},
         /* D47/PA0 */
-        {GPIOA_BASE,  0,        ADC0, TIMER5_CH1_CCR,  EXTI_CONFIG_PORTA,        TIMER5, 1},
+        {GPIOA_BASE,  0,           0, TIMER5_CH1_CCR, EXTI_CONFIG_PORTA,        TIMER5, 1},
         /* D48/PA1 */
-        {GPIOA_BASE,  1,        ADC1, TIMER5_CH2_CCR,  EXTI_CONFIG_PORTA,        TIMER5, 2}, /* FIXME (?) what to do about D48--D50
-                                                                                                also being TIMER2_CH[2,3,4]? */
+        {GPIOA_BASE,  1,           1, TIMER5_CH2_CCR, EXTI_CONFIG_PORTA,        TIMER5, 2}, /* FIXME (?) what to do about D48--D50
+                                                                                               also being TIMER2_CH[2,3,4]? */
         /* D49/PA2 */
-        {GPIOA_BASE,  2,        ADC2, TIMER5_CH3_CCR,  EXTI_CONFIG_PORTA,        TIMER5, 3},
+        {GPIOA_BASE,  2,           2, TIMER5_CH3_CCR, EXTI_CONFIG_PORTA,        TIMER5, 3},
         /* D50/PA3 */
-        {GPIOA_BASE,  3,        ADC3, TIMER5_CH4_CCR,  EXTI_CONFIG_PORTA,        TIMER5, 4},
+        {GPIOA_BASE,  3,           3, TIMER5_CH4_CCR, EXTI_CONFIG_PORTA,        TIMER5, 4},
         /* D51/PA4 */
-        {GPIOA_BASE,  4,        ADC4,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  4,           4,              0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D52/PA5 */
-        {GPIOA_BASE,  5,        ADC5,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  5,           5,              0, EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D53/PA6 */
-        {GPIOA_BASE,  6,        ADC6, TIMER3_CH1_CCR,  EXTI_CONFIG_PORTA,        TIMER3, 1},
+        {GPIOA_BASE,  6,           6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA,        TIMER3, 1},
         /* D54/PA7 */
-        {GPIOA_BASE,  7,        ADC7, TIMER3_CH2_CCR,  EXTI_CONFIG_PORTA,        TIMER3, 2},
+        {GPIOA_BASE,  7,           7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA,        TIMER3, 2},
 
         /* Right (triple) header */
 
         /* D55/PF0 */
-        {GPIOF_BASE,  0, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  0, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D56/PD11 */
-        {GPIOD_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D57/PD14 */
-        {GPIOD_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D58/PF1 */
-        {GPIOF_BASE,  1, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  1, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D59/PD12 */
-        {GPIOD_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D60/PD15 */
-        {GPIOD_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D61/PF2 */
-        {GPIOF_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D62/PD13 */
-        {GPIOD_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D63/PD0 */
-        {GPIOD_BASE,  0, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  0, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D64/PF3 */
-        {GPIOF_BASE,  3, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  3, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D65/PE3 */
-        {GPIOE_BASE,  3, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  3, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D66/PD1 */
-        {GPIOD_BASE,  1, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  1, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D67/PF4 */
-        {GPIOF_BASE,  4, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  4, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D68/PE4 */
-        {GPIOE_BASE,  4, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  4, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D69/PE7 */
-        {GPIOE_BASE,  7, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  7, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D70/PF5 */
-        {GPIOF_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D71/PE5 */
-        {GPIOE_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D72/PE8 */
-        {GPIOE_BASE,  8, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  8, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D73/PF12 */
-        {GPIOF_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D74/PE6 */
-        {GPIOE_BASE,  6, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  6, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D75/PE9 */
-        {GPIOE_BASE,  9, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  9, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D76/PF13 */
-        {GPIOF_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D77/PE10 */
-        {GPIOE_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D78/PF14 */
-        {GPIOF_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D79/PG9 */
-        {GPIOG_BASE,  9, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  9, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D80/PE11 */
-        {GPIOE_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 11, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D81/PF15 */
-        {GPIOF_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
+        {GPIOF_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTF, TIMER_INVALID, TIMER_INVALID},
         /* D82/PG10 */
-        {GPIOG_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D83/PE12 */
-        {GPIOE_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 12, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D84/PG0 */
-        {GPIOG_BASE,  0, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  0, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D85/PD5 */
-        {GPIOD_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D86/PE13 */
-        {GPIOE_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 13, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D87/PG1 */
-        {GPIOG_BASE,  1, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  1, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D88/PD4 */
-        {GPIOD_BASE,  4, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  4, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D89/PE14 */
-        {GPIOE_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 14, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D90/PG2 */
-        {GPIOG_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  2, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D91/PE1 */
-        {GPIOE_BASE,  1, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  1, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D92/PE15 */
-        {GPIOE_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE, 15, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D93/PG3 */
-        {GPIOG_BASE,  3, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  3, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D94/PE0 */
-        {GPIOE_BASE,  0, ADC_INVALID,              0,  EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
+        {GPIOE_BASE,  0, ADC_INVALID,              0, EXTI_CONFIG_PORTE, TIMER_INVALID, TIMER_INVALID},
         /* D95/PD8 */
-        {GPIOD_BASE,  8, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  8, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D96/PG4 */
-        {GPIOG_BASE,  4, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  4, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D97/PD9 */
-        {GPIOD_BASE,  9, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        {GPIOD_BASE,  9, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
         /* D98/PG5 */
-        {GPIOG_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
+        {GPIOG_BASE,  5, ADC_INVALID,              0, EXTI_CONFIG_PORTG, TIMER_INVALID, TIMER_INVALID},
         /* D99/PD10 */
-        {GPIOD_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID}
+        {GPIOD_BASE, 10, ADC_INVALID,              0, EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID}
     };
 
     #define BOARD_INIT do {                           \
@@ -409,23 +404,23 @@ typedef struct PinMapping {
         /* D2/PB2 */
         {GPIOB_BASE,  2,  ADC_INVALID,              0, EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
         /* D3/PB0 */
-        {GPIOB_BASE,  0,  ADC8,        TIMER3_CH3_CCR, EXTI_CONFIG_PORTB, TIMER3,        3},
+        {GPIOB_BASE,  0,            8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB, TIMER3,        3},
         /* D4/PA7 */
-        {GPIOA_BASE,  7,  ADC7,        TIMER3_CH2_CCR, EXTI_CONFIG_PORTA, TIMER3,        2},
+        {GPIOA_BASE,  7,            7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA, TIMER3,        2},
         /* D5/PA6 */
-        {GPIOA_BASE,  6,  ADC6,        TIMER3_CH1_CCR, EXTI_CONFIG_PORTA, TIMER3,        1},
+        {GPIOA_BASE,  6,            6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA, TIMER3,        1},
         /* D6/PA5 */
-        {GPIOA_BASE,  5,  ADC5,                    0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  5,            5,             0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D7/PA4 */
-        {GPIOA_BASE,  4,  ADC4,                    0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        {GPIOA_BASE,  4,            4,             0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
         /* D8/PA3 */
-        {GPIOA_BASE,  3,  ADC3,        TIMER2_CH4_CCR, EXTI_CONFIG_PORTA, TIMER2,        4},
+        {GPIOA_BASE,  3,            3, TIMER2_CH4_CCR, EXTI_CONFIG_PORTA, TIMER2,        4},
         /* D9/PA2 */
-        {GPIOA_BASE,  2,  ADC2,        TIMER2_CH3_CCR, EXTI_CONFIG_PORTA, TIMER2,        3},
+        {GPIOA_BASE,  2,            2, TIMER2_CH3_CCR, EXTI_CONFIG_PORTA, TIMER2,        3},
         /* D10/PA1 */
-        {GPIOA_BASE,  1,  ADC1,        TIMER2_CH2_CCR, EXTI_CONFIG_PORTA, TIMER2,        2},
+        {GPIOA_BASE,  1,            1, TIMER2_CH2_CCR, EXTI_CONFIG_PORTA, TIMER2,        2},
         /* D11/PA0 */
-        {GPIOA_BASE,  0,  ADC0,        TIMER2_CH1_CCR, EXTI_CONFIG_PORTA, TIMER2,        1},
+        {GPIOA_BASE,  0,            0, TIMER2_CH1_CCR, EXTI_CONFIG_PORTA, TIMER2,        1},
         /* D12/PC15 */
         {GPIOC_BASE, 15,  ADC_INVALID,              0, EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
         /* D13/PC14 */
@@ -469,7 +464,7 @@ typedef struct PinMapping {
         /* D32/PB8 */
         {GPIOB_BASE,  8,  ADC_INVALID, TIMER4_CH3_CCR, EXTI_CONFIG_PORTB, TIMER4,        3},
         /* D33/PB1 */
-        {GPIOB_BASE,  1,  ADC9,        TIMER3_CH4_CCR, EXTI_CONFIG_PORTB, TIMER3,        4},
+        {GPIOB_BASE,  1,            9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB, TIMER3,        4},
     };
 
     /* since we want the Serial Wire/JTAG pins as GPIOs, disable both
diff --git a/wirish/wirish.c b/wirish/wirish.c
index aaae9d4..1ea4863 100644
--- a/wirish/wirish.c
+++ b/wirish/wirish.c
@@ -64,9 +64,12 @@ void init(void) {
     nvic_init();
     systick_init(SYSTICK_RELOAD_VAL);
     gpio_init();
+
     /* Initialize the ADC for slow conversions, to allow for high
        impedance inputs. */
-    adc_init(ADC_SMPR_55_5);
+    adc_init(ADC1, 0);
+    adc_set_sample_rate(ADC1->regs, ADC_SMPR_55_5);
+
     timer_init(TIMER1, 1);
     timer_init(TIMER2, 1);
     timer_init(TIMER3, 1);
diff --git a/wirish/wirish_analog.c b/wirish/wirish_analog.c
index 3c63342..ba1290d 100644
--- a/wirish/wirish_analog.c
+++ b/wirish/wirish_analog.c
@@ -33,9 +33,9 @@
 /* Assumes that the ADC has been initialized and that the pin is set
  * to ANALOG_INPUT */
 uint32 analogRead(uint8 pin) {
-    if(PIN_MAP[pin].adc == ADC_INVALID) {
+    if(PIN_MAP[pin].adc_channel == ADC_INVALID) {
         return 0;
     }
 
-    return adc_read(PIN_MAP[pin].adc);
+    return adc_read(ADC1->regs, PIN_MAP[pin].adc_channel);
 }