qa-slave-shield.cpp and test-session.cpp fixes for Mini and RET6 Edition.

There's a bit of a hack on the RET6 NR_DAC_PINS: due to the fact that
PA5 is hooked up to the built-in LED and DAC channel 2, I set
NR_DAC_PINS to 0 for the STM32F103RE (in libmaple.h), so that init()
doesn't dac_init() and mess with the LED.

Not too worried about it since this is just a beta board, but we'll
need to fix this in the design for the real version.

Also, BUT should be moved, since it steals Timer 8's channel 4 CC
connection.

9 files changed, 785 insertions, 64 deletions

diff --git a/Makefile b/Makefile
index a709696..a953088 100644
--- a/Makefile
+++ b/Makefile
@@ -21,6 +21,10 @@ ifeq ($(BOARD), maple_mini)
    MCU := STM32F103CB
    PRODUCT_ID := 0003
 endif
+ifeq ($(BOARD), maple_RET6)
+   MCU := STM32F103RE
+   PRODUCT_ID := 0003
+endif
 
 # Useful paths
 ifeq ($(LIB_MAPLE_HOME),)
diff --git a/examples/qa-slave-shield.cpp b/examples/qa-slave-shield.cpp
index 5ca451d..fc33a4a 100644
--- a/examples/qa-slave-shield.cpp
+++ b/examples/qa-slave-shield.cpp
@@ -24,7 +24,6 @@ bool skip_pin_p(uint8 pin);
 void setup() {
     /* Set up the LED to blink  */
     pinMode(LED_PIN, OUTPUT);
-    digitalWrite(LED_PIN, HIGH);
 
     for(int i = 0; i < NR_GPIO_PINS; i++) {
         if (skip_pin_p(i)) {
@@ -39,7 +38,6 @@ void setup() {
 void loop() {
     toggleLED();
     delay(100);
-    toggleLED();
 
     for(int i = 0; i < NR_GPIO_PINS; i++) {
         if (skip_pin_p(i)) {
diff --git a/examples/test-session.cpp b/examples/test-session.cpp
index cf1f4ec..c473521 100644
--- a/examples/test-session.cpp
+++ b/examples/test-session.cpp
@@ -55,6 +55,14 @@ const uint8 adc_pins[] = {
     46, 47, 48, 49, 50, 51, 52, 53, 54};
 const uint8 pins_to_skip[] = {LED_PIN};
 
+#elif defined(BOARD_maple_RET6)
+const uint8 pwm_pins[] =
+    {0, 1, 2, 3, 5, 6, 7, 8, 9, 11, 12, 14, 24, 25, 27, 28, 35, 37, 37,
+     38};                       // NB 38 is BUT
+const uint8 adc_pins[] =
+    {0, 1, 2, 10, 11, 12, 13, 15, 16, 17, 18, 19, 20, 27, 28};
+const uint8 pins_to_skip[] = {LED_PIN};
+
 #else
 #error "Board type has not been selected correctly."
 #endif
@@ -497,10 +505,12 @@ void cmd_gpio_qa(void) {
             COMM.println(i);
             continue;
         }
-        COMM.print("Checking pin ")
+        COMM.print("Checking pin ");
         COMM.print(i, DEC);
         while(digitalRead(i) == 0) continue;
         for(int j = 0; j < NR_GPIO_PINS; j++) {
+            if (skip_pin_p(j))
+                continue;
             if(digitalRead(j) && j != i) {
                 COMM.print(": FAIL ########################### D");
                 COMM.println(j, DEC);
@@ -509,6 +519,8 @@ void cmd_gpio_qa(void) {
         }
         while(digitalRead(i) == 1) continue;
         for(int j = 0; j < NR_GPIO_PINS; j++) {
+            if (skip_pin_p(j))
+                continue;
             if(digitalRead(j) && j != i) {
                 COMM.print(": FAIL ########################### D");
                 COMM.println(j, DEC);
diff --git a/libmaple/libmaple.h b/libmaple/libmaple.h
index 6b49c45..f893cff 100644
--- a/libmaple/libmaple.h
+++ b/libmaple/libmaple.h
@@ -42,6 +42,20 @@
 #define DEBUG_LEVEL DEBUG_ALL
 #endif
 
+/* Bitbanded Memory sections */
+#define BITBAND_SRAM_REF   0x20000000
+#define BITBAND_SRAM_BASE  0x22000000
+#define BITBAND_PERI_REF   0x40000000
+#define BITBAND_PERI_BASE  0x42000000
+
+#define USB_CONFIG_MAX_POWER      (100 >> 1)
+#define RESET_DELAY               (100)
+
+#define ERROR_USART_NUM        USART2
+#define ERROR_USART_BAUD       9600
+#define ERROR_TX_PORT          GPIOA_BASE
+#define ERROR_TX_PIN           2
+
 /* MCU-specific configuration */
 #if defined(MCU_STM32F103RB)
     /* e.g., LeafLabs Maple */
@@ -74,39 +88,21 @@
     #define VCOM_ID_PRODUCT   0x0004
     #define USB_DISC_BANK     GPIOC_BASE
     #define USB_DISC_PIN      12
-    #define USB_CONFIG_MAX_POWER      (100 >> 1)
-    #define RESET_DELAY               (100)
 
     /* Where to put usercode (based on space reserved for bootloader) */
     #define USER_ADDR_ROM 0x08005000
     #define USER_ADDR_RAM 0x20000C00
-    #define STACK_TOP     0x20000800
+    #define STACK_TOP     0x20000800 /* FIXME can this possibly be correct? */
 
-    /* Debug port settings (from ASSERT) */
     #define ERROR_LED_PORT         GPIOB_BASE
     #define ERROR_LED_PIN          12
-    #define ERROR_USART_NUM        USART2
-    #define ERROR_USART_BAUD       9600
-    #define ERROR_TX_PORT          GPIOA_BASE
-    #define ERROR_TX_PIN           2
-
-    /* Just in case, most boards have at least some memory */
-    #ifndef RAMSIZE
-    #  define RAMSIZE             (caddr_t)0x50000
-    #endif
-
-    /* Bitbanded Memory sections */
-    #define BITBAND_SRAM_REF   0x20000000
-    #define BITBAND_SRAM_BASE  0x22000000
-    #define BITBAND_PERI_REF   0x40000000
-    #define BITBAND_PERI_BASE  0x42000000
 
 #elif defined(MCU_STM32F103ZE)
     /* e.g., LeafLabs Maple Native */
 
     #define NR_GPIO_PORTS             7
     #define NR_GPIO_PINS            100
-    #define NR_BKP_REGS              42 /* TODO test on Native */
+    #define NR_BKP_REGS              42
     #define NR_TIMERS                 8
     #define NR_USART                  5 /* NB: 4 and 5 are UART only */
     #define NR_FSMC                   1
@@ -116,8 +112,6 @@
     #define VCOM_ID_PRODUCT   0x0004
     #define USB_DISC_BANK     GPIOB_BASE
     #define USB_DISC_PIN      8
-    #define USB_CONFIG_MAX_POWER      (100 >> 1)
-    #define RESET_DELAY               (100)
 
     #define USER_ADDR_ROM 0x08005000
     #define USER_ADDR_RAM 0x20000C00
@@ -125,26 +119,13 @@
 
     #define ERROR_LED_PORT         GPIOC_BASE
     #define ERROR_LED_PIN          15
-    #define ERROR_USART_NUM        USART1
-    #define ERROR_USART_BAUD       9600
-    #define ERROR_TX_PORT          GPIOA_BASE
-    #define ERROR_TX_PIN           10
-
-    #ifndef RAMSIZE
-    #  define RAMSIZE             (caddr_t)0x50000
-    #endif
-
-    #define BITBAND_SRAM_REF   0x20000000
-    #define BITBAND_SRAM_BASE  0x22000000
-    #define BITBAND_PERI_REF   0x40000000
-    #define BITBAND_PERI_BASE  0x42000000
 
 #elif defined(MCU_STM32F103CB)
     /* e.g., LeafLabs Maple Mini */
 
     #define NR_GPIO_PORTS 3
     #define NR_GPIO_PINS  34
-    #define NR_BKP_REGS   10    /* TODO test on Mini */
+    #define NR_BKP_REGS   10
     #define NR_TIMERS     4
     #define NR_USART      3
     #define NR_FSMC       0
@@ -154,8 +135,6 @@
     #define VCOM_ID_PRODUCT      0x0005
     #define USB_DISC_BANK        GPIOB_BASE
     #define USB_DISC_PIN         9
-    #define USB_CONFIG_MAX_POWER (100 >> 1)
-    #define RESET_DELAY          100
 
     #define USER_ADDR_ROM 0x08005000
     #define USER_ADDR_RAM 0x20000C00
@@ -163,20 +142,29 @@
 
     #define ERROR_LED_PORT   GPIOB_BASE
     #define ERROR_LED_PIN    1
-    #define ERROR_USART_NUM  USART2
-    #define ERROR_USART_BAUD 9600
-    #define ERROR_TX_PORT    GPIOA_BASE
-    #define ERROR_TX_PIN     2
-
-    #ifndef RAMSIZE
-    #  define RAMSIZE             (caddr_t)0x50000
-    #endif
-
-    /* Bitbanded Memory sections */
-    #define BITBAND_SRAM_REF   0x20000000
-    #define BITBAND_SRAM_BASE  0x22000000
-    #define BITBAND_PERI_REF   0x40000000
-    #define BITBAND_PERI_BASE  0x42000000
+
+#elif defined(MCU_STM32F103RE)
+    /* e.g., LeafLabs Maple RET6 Edition */
+
+    #define NR_GPIO_PORTS             4
+    #define NR_GPIO_PINS             39
+    #define NR_BKP_REGS              42
+    #define NR_TIMERS                 8
+    #define NR_USART                  5 /* NB: 4 and 5 are UART only */
+    #define NR_FSMC                   0
+    #define NR_DAC_PINS               0 /* HACK: LED hooked up to DAC2 */
+
+    #define VCOM_ID_VENDOR    0x1EAF
+    #define VCOM_ID_PRODUCT   0x0004
+    #define USB_DISC_BANK     GPIOC_BASE
+    #define USB_DISC_PIN      12
+
+    #define USER_ADDR_ROM 0x08005000
+    #define USER_ADDR_RAM 0x20000C00
+    #define STACK_TOP     0x20000800
+
+    #define ERROR_LED_PORT         GPIOA_BASE
+    #define ERROR_LED_PIN          5
 
 #else
 
diff --git a/libmaple/usb/usb_callbacks.c b/libmaple/usb/usb_callbacks.c
index ccb0fdd..375d204 100644
--- a/libmaple/usb/usb_callbacks.c
+++ b/libmaple/usb/usb_callbacks.c
@@ -88,19 +88,19 @@ void vcomDataRxCb(void) {
       }
 
       if (cmpMatch) {
-          asm volatile("mov r0, %[stack_top]      \n\t"             // Reset the stack
+          asm volatile("mov r0, %[stack_top]      \n\t" // Reset the stack
                        "mov sp, r0                \n\t"
                        "mov r0, #1                \n\t"
                        "mov r1, %[target_addr]    \n\t"
                        "mov r2, %[cpsr]           \n\t"
-                       "push {r2}                 \n\t"             // Fake xPSR
-                       "push {r1}                 \n\t"             // Target address for PC
-                       "push {r0}                 \n\t"             // Fake LR
-                       "push {r0}                 \n\t"             // Fake R12
-                       "push {r0}                 \n\t"             // Fake R3
-                       "push {r0}                 \n\t"             // Fake R2
-                       "push {r0}                 \n\t"             // Fake R1
-                       "push {r0}                 \n\t"             // Fake R0
+                       "push {r2}                 \n\t" // Fake xPSR
+                       "push {r1}                 \n\t" // Target address for PC
+                       "push {r0}                 \n\t" // Fake LR
+                       "push {r0}                 \n\t" // Fake R12
+                       "push {r0}                 \n\t" // Fake R3
+                       "push {r0}                 \n\t" // Fake R2
+                       "push {r0}                 \n\t" // Fake R1
+                       "push {r0}                 \n\t" // Fake R0
                        "mov lr, %[exc_return]     \n\t"
                        "bx lr"
                        :
diff --git a/support/ld/maple_RET6/flash.ld b/support/ld/maple_RET6/flash.ld
new file mode 100644
index 0000000..4e820d2
--- /dev/null
+++ b/support/ld/maple_RET6/flash.ld
@@ -0,0 +1,211 @@
+/* Linker script for STM32 (by Lanchon with Mods by LeafLabs)

+ *

+ * Version:Sourcery G++ 4.2-84

+ * BugURL:https://support.codesourcery.com/GNUToolchain/

+ *

+ *  Copyright 2007 CodeSourcery.

+ *

+ * The authors hereby grant permission to use, copy, modify, distribute,

+ * and license this software and its documentation for any purpose, provided

+ * that existing copyright notices are retained in all copies and that this

+ * notice is included verbatim in any distributions. No written agreement,

+ * license, or royalty fee is required for any of the authorized uses.

+ * Modifications to this software may be copyrighted by their authors

+ * and need not follow the licensing terms described here, provided that

+ * the new terms are clearly indicated on the first page of each file where

+ * they apply. */

+

+/* Linker script for STM32 (by Lanchon),

+ * ROM and RAM relocated to their positions 

+ * as placed by Maple bootloader

+ *

+ * Configure target memory and included script

+ * according to your application requirements. */

+

+/* Define memory spaces. */

+MEMORY

+{

+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K

+  rom (rx)  : ORIGIN = 0x08005000, LENGTH = 492K

+}

+

+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

+ENTRY(_start)

+SEARCH_DIR(.)

+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */

+GROUP(libgcc.a libc.a libm.a libcs3-lanchon-stm32.a)

+

+/* These force the linker to search for particular symbols from

+ * the start of the link process and thus ensure the user's

+ * overrides are picked up

+ */

+EXTERN(__cs3_reset_lanchon_stm32)

+INCLUDE names.inc

+EXTERN(__cs3_interrupt_vector_lanchon_stm32)

+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)

+EXTERN(_start)

+

+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);

+PROVIDE(__cs3_heap_start = _end);

+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);

+

+SECTIONS

+{

+  .text :

+  {

+    CREATE_OBJECT_SYMBOLS

+    __cs3_region_start_rom = .;

+    *(.cs3.region-head.rom)

+    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;

+    *(.cs3.interrupt_vector)

+    /* Make sure we pulled in an interrupt vector.  */

+    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");

+    *(.rom)

+    *(.rom.b)

+

+    PROVIDE(__cs3_reset_lanchon_stm32 = _start);

+    __cs3_reset = __cs3_reset_lanchon_stm32;

+    *(.cs3.reset)

+

+    *(.text .text.* .gnu.linkonce.t.*)

+    *(.plt)

+    *(.gnu.warning)

+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)

+

+    *(.rodata .rodata.* .gnu.linkonce.r.*)

+

+    *(.ARM.extab* .gnu.linkonce.armextab.*)

+    *(.gcc_except_table)

+    *(.eh_frame_hdr)

+    *(.eh_frame)

+

+    . = ALIGN(4);

+    KEEP(*(.init))

+

+    . = ALIGN(4);

+    __preinit_array_start = .;

+    KEEP (*(.preinit_array))

+    __preinit_array_end = .;

+

+    . = ALIGN(4);

+    __init_array_start = .;

+    KEEP (*(SORT(.init_array.*)))

+    KEEP (*(.init_array))

+    __init_array_end = .;

+

+    . = ALIGN(0x4);

+    KEEP (*crtbegin.o(.ctors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))

+    KEEP (*(SORT(.ctors.*)))

+    KEEP (*crtend.o(.ctors))

+

+    . = ALIGN(4);

+    KEEP(*(.fini))

+

+    . = ALIGN(4);

+    __fini_array_start = .;

+    KEEP (*(.fini_array))

+    KEEP (*(SORT(.fini_array.*)))

+    __fini_array_end = .;

+

+    KEEP (*crtbegin.o(.dtors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))

+    KEEP (*(SORT(.dtors.*)))

+    KEEP (*crtend.o(.dtors))

+

+    . = ALIGN(4);

+    __cs3_regions = .;

+    LONG (0)

+    LONG (__cs3_region_init_ram)

+    LONG (__cs3_region_start_ram)

+    LONG (__cs3_region_init_size_ram)

+    LONG (__cs3_region_zero_size_ram)

+  } >rom

+

+  /* .ARM.exidx is sorted, so has to go in its own output section.  */

+  __exidx_start = .;

+  .ARM.exidx :

+  {

+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+  } >rom

+  __exidx_end = .;

+  .text.align :

+  {

+    . = ALIGN(8);

+    _etext = .;

+  } >rom

+

+/* expose a custom rom only section */

+  .USER_FLASH :

+  {

+    *(.USER_FLASH)

+  } >rom

+

+

+  /* __cs3_region_end_rom is deprecated */

+  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);

+  __cs3_region_size_rom = LENGTH(rom);

+  __cs3_region_num = 1;

+

+  .data :

+  {

+    __cs3_region_start_ram = .;

+    *(.cs3.region-head.ram)

+    KEEP(*(.jcr))

+    *(.got.plt) *(.got)

+    *(.shdata)

+    *(.data .data.* .gnu.linkonce.d.*)

+    *(.ram)

+    . = ALIGN (8);

+    _edata = .;

+  } >ram AT>rom

+  .bss :

+  {

+    *(.shbss)

+    *(.bss .bss.* .gnu.linkonce.b.*)

+    *(COMMON)

+    *(.ram.b)

+    . = ALIGN (8);

+    _end = .;

+    __end = .;

+  } >ram AT>rom

+  /* __cs3_region_end_ram is deprecated */

+  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);

+  __cs3_region_size_ram = LENGTH(ram);

+  __cs3_region_init_ram = LOADADDR (.data);

+  __cs3_region_init_size_ram = _edata - ADDR (.data);

+  __cs3_region_zero_size_ram = _end - _edata;

+  __cs3_region_num = 1;

+

+  .stab 0 (NOLOAD) : { *(.stab) }

+  .stabstr 0 (NOLOAD) : { *(.stabstr) }

+  /* DWARF debug sections.

+   * Symbols in the DWARF debugging sections are relative to the beginning

+   * of the section so we begin them at 0.  */

+  /* DWARF 1 */

+  .debug          0 : { *(.debug) }

+  .line           0 : { *(.line) }

+  /* GNU DWARF 1 extensions */

+  .debug_srcinfo  0 : { *(.debug_srcinfo) }

+  .debug_sfnames  0 : { *(.debug_sfnames) }

+  /* DWARF 1.1 and DWARF 2 */

+  .debug_aranges  0 : { *(.debug_aranges) }

+  .debug_pubnames 0 : { *(.debug_pubnames) }

+  /* DWARF 2 */

+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }

+  .debug_abbrev   0 : { *(.debug_abbrev) }

+  .debug_line     0 : { *(.debug_line) }

+  .debug_frame    0 : { *(.debug_frame) }

+  .debug_str      0 : { *(.debug_str) }

+  .debug_loc      0 : { *(.debug_loc) }

+  .debug_macinfo  0 : { *(.debug_macinfo) }

+  /* SGI/MIPS DWARF 2 extensions */

+  .debug_weaknames 0 : { *(.debug_weaknames) }

+  .debug_funcnames 0 : { *(.debug_funcnames) }

+  .debug_typenames 0 : { *(.debug_typenames) }

+  .debug_varnames  0 : { *(.debug_varnames) }

+

+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }

+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }

+  /DISCARD/ : { *(.note.GNU-stack) }

+}

diff --git a/support/ld/maple_RET6/jtag.ld b/support/ld/maple_RET6/jtag.ld
new file mode 100644
index 0000000..90a0a3f
--- /dev/null
+++ b/support/ld/maple_RET6/jtag.ld
@@ -0,0 +1,186 @@
+/* Linker script for STM32 (by Lanchon),

+ * ROM and RAM relocated to their positions 

+ * as placed by Maple bootloader

+ *

+ * Configure target memory and included script

+ * according to your application requirements. */

+

+/* Define memory spaces. */

+MEMORY

+{

+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K

+  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 512K

+}

+

+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

+ENTRY(_start)

+SEARCH_DIR(.)

+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */

+GROUP(libgcc.a libc.a libm.a libcs3-lanchon-stm32.a)

+

+/* These force the linker to search for particular symbols from

+ * the start of the link process and thus ensure the user's

+ * overrides are picked up

+ */

+EXTERN(__cs3_reset_lanchon_stm32)

+INCLUDE names.inc

+EXTERN(__cs3_interrupt_vector_lanchon_stm32)

+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)

+EXTERN(_start)

+

+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);

+PROVIDE(__cs3_heap_start = _end);

+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);

+

+SECTIONS

+{

+  .text :

+  {

+    CREATE_OBJECT_SYMBOLS

+    __cs3_region_start_rom = .;

+    *(.cs3.region-head.rom)

+    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;

+    *(.cs3.interrupt_vector)

+    /* Make sure we pulled in an interrupt vector.  */

+    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");

+    *(.rom)

+    *(.rom.b)

+

+    PROVIDE(__cs3_reset_lanchon_stm32 = _start);

+    __cs3_reset = __cs3_reset_lanchon_stm32;

+    *(.cs3.reset)

+

+    *(.text .text.* .gnu.linkonce.t.*)

+    *(.plt)

+    *(.gnu.warning)

+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)

+

+    *(.rodata .rodata.* .gnu.linkonce.r.*)

+

+    *(.ARM.extab* .gnu.linkonce.armextab.*)

+    *(.gcc_except_table)

+    *(.eh_frame_hdr)

+    *(.eh_frame)

+

+    . = ALIGN(4);

+    KEEP(*(.init))

+

+    . = ALIGN(4);

+    __preinit_array_start = .;

+    KEEP (*(.preinit_array))

+    __preinit_array_end = .;

+

+    . = ALIGN(4);

+    __init_array_start = .;

+    KEEP (*(SORT(.init_array.*)))

+    KEEP (*(.init_array))

+    __init_array_end = .;

+

+    . = ALIGN(0x4);

+    KEEP (*crtbegin.o(.ctors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))

+    KEEP (*(SORT(.ctors.*)))

+    KEEP (*crtend.o(.ctors))

+

+    . = ALIGN(4);

+    KEEP(*(.fini))

+

+    . = ALIGN(4);

+    __fini_array_start = .;

+    KEEP (*(.fini_array))

+    KEEP (*(SORT(.fini_array.*)))

+    __fini_array_end = .;

+

+    KEEP (*crtbegin.o(.dtors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))

+    KEEP (*(SORT(.dtors.*)))

+    KEEP (*crtend.o(.dtors))

+

+    . = ALIGN(4);

+    __cs3_regions = .;

+    LONG (0)

+    LONG (__cs3_region_init_ram)

+    LONG (__cs3_region_start_ram)

+    LONG (__cs3_region_init_size_ram)

+    LONG (__cs3_region_zero_size_ram)

+  } >rom

+

+  /* .ARM.exidx is sorted, so has to go in its own output section.  */

+  __exidx_start = .;

+  .ARM.exidx :

+  {

+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+  } >rom

+  __exidx_end = .;

+  .text.align :

+  {

+    . = ALIGN(8);

+    _etext = .;

+  } >rom

+  /* __cs3_region_end_rom is deprecated */

+  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);

+  __cs3_region_size_rom = LENGTH(rom);

+  __cs3_region_num = 1;

+

+  .data :

+  {

+    __cs3_region_start_ram = .;

+    *(.cs3.region-head.ram)

+    KEEP(*(.jcr))

+    *(.got.plt) *(.got)

+    *(.shdata)

+    *(.data .data.* .gnu.linkonce.d.*)

+    *(.ram)

+    . = ALIGN (8);

+    _edata = .;

+  } >ram AT>rom

+  .bss :

+  {

+    *(.shbss)

+    *(.bss .bss.* .gnu.linkonce.b.*)

+    *(COMMON)

+    *(.ram.b)

+    . = ALIGN (8);

+    _end = .;

+    __end = .;

+  } >ram AT>rom

+  /* __cs3_region_end_ram is deprecated */

+  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);

+  __cs3_region_size_ram = LENGTH(ram);

+  __cs3_region_init_ram = LOADADDR (.data);

+  __cs3_region_init_size_ram = _edata - ADDR (.data);

+  __cs3_region_zero_size_ram = _end - _edata;

+  __cs3_region_num = 1;

+

+  .stab 0 (NOLOAD) : { *(.stab) }

+  .stabstr 0 (NOLOAD) : { *(.stabstr) }

+  /* DWARF debug sections.

+   * Symbols in the DWARF debugging sections are relative to the beginning

+   * of the section so we begin them at 0.  */

+  /* DWARF 1 */

+  .debug          0 : { *(.debug) }

+  .line           0 : { *(.line) }

+  /* GNU DWARF 1 extensions */

+  .debug_srcinfo  0 : { *(.debug_srcinfo) }

+  .debug_sfnames  0 : { *(.debug_sfnames) }

+  /* DWARF 1.1 and DWARF 2 */

+  .debug_aranges  0 : { *(.debug_aranges) }

+  .debug_pubnames 0 : { *(.debug_pubnames) }

+  /* DWARF 2 */

+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }

+  .debug_abbrev   0 : { *(.debug_abbrev) }

+  .debug_line     0 : { *(.debug_line) }

+  .debug_frame    0 : { *(.debug_frame) }

+  .debug_str      0 : { *(.debug_str) }

+  .debug_loc      0 : { *(.debug_loc) }

+  .debug_macinfo  0 : { *(.debug_macinfo) }

+  /* SGI/MIPS DWARF 2 extensions */

+  .debug_weaknames 0 : { *(.debug_weaknames) }

+  .debug_funcnames 0 : { *(.debug_funcnames) }

+  .debug_typenames 0 : { *(.debug_typenames) }

+  .debug_varnames  0 : { *(.debug_varnames) }

+

+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }

+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }

+  /DISCARD/ : { *(.note.GNU-stack) }

+}

diff --git a/support/ld/maple_RET6/ram.ld b/support/ld/maple_RET6/ram.ld
new file mode 100644
index 0000000..a5e1482
--- /dev/null
+++ b/support/ld/maple_RET6/ram.ld
@@ -0,0 +1,220 @@
+/* Linker script for STM32 (by Lanchon with Mods by LeafLabs)

+ *

+ * Version:Sourcery G++ 4.2-84

+ * BugURL:https://support.codesourcery.com/GNUToolchain/

+ *

+ *  Copyright 2007 CodeSourcery.

+ *

+ * The authors hereby grant permission to use, copy, modify, distribute,

+ * and license this software and its documentation for any purpose, provided

+ * that existing copyright notices are retained in all copies and that this

+ * notice is included verbatim in any distributions. No written agreement,

+ * license, or royalty fee is required for any of the authorized uses.

+ * Modifications to this software may be copyrighted by their authors

+ * and need not follow the licensing terms described here, provided that

+ * the new terms are clearly indicated on the first page of each file where

+ * they apply. */

+

+/* Linker script for STM32 (by Lanchon),

+ * ROM and RAM relocated to their positions 

+ * as placed by Maple bootloader

+ *

+ * Configure target memory and included script

+ * according to your application requirements. */

+

+/* Define memory spaces. */

+MEMORY

+{

+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K

+  rom (rx)  : ORIGIN = 0x08005000, LENGTH = 0K

+}

+

+

+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

+ENTRY(_start)

+SEARCH_DIR(.)

+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */

+GROUP(libgcc.a libc.a libm.a libcs3-lanchon-stm32.a)

+

+/* These force the linker to search for particular symbols from

+ * the start of the link process and thus ensure the user's

+ * overrides are picked up

+ */

+EXTERN(__cs3_reset_lanchon_stm32)

+INCLUDE names.inc

+EXTERN(__cs3_interrupt_vector_lanchon_stm32)

+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)

+EXTERN(_start)

+

+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);

+PROVIDE(__cs3_heap_start = _end);

+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);

+

+SECTIONS

+{

+  .text :

+  {

+    CREATE_OBJECT_SYMBOLS

+    __cs3_region_start_ram = .;

+    *(.cs3.region-head.ram)

+    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;

+    *(.cs3.interrupt_vector)

+    /* Make sure we pulled in an interrupt vector.  */

+    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");

+

+    PROVIDE(__cs3_reset_lanchon_stm32 = _start);

+    __cs3_reset = __cs3_reset_lanchon_stm32;

+    *(.cs3.reset)

+

+    *(.text .text.* .gnu.linkonce.t.*)

+    *(.plt)

+    *(.gnu.warning)

+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)

+

+    *(.rodata .rodata.* .gnu.linkonce.r.*)

+

+    *(.ARM.extab* .gnu.linkonce.armextab.*)

+    *(.gcc_except_table)

+    *(.eh_frame_hdr)

+    *(.eh_frame)

+

+    . = ALIGN(4);

+    KEEP(*(.init))

+

+    . = ALIGN(4);

+    __preinit_array_start = .;

+    KEEP (*(.preinit_array))

+    __preinit_array_end = .;

+

+    . = ALIGN(4);

+    __init_array_start = .;

+    KEEP (*(SORT(.init_array.*)))

+    KEEP (*(.init_array))

+    __init_array_end = .;

+

+    . = ALIGN(0x4);

+    KEEP (*crtbegin.o(.ctors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))

+    KEEP (*(SORT(.ctors.*)))

+    KEEP (*crtend.o(.ctors))

+

+    . = ALIGN(4);

+    KEEP(*(.fini))

+

+    . = ALIGN(4);

+    __fini_array_start = .;

+    KEEP (*(.fini_array))

+    KEEP (*(SORT(.fini_array.*)))

+    __fini_array_end = .;

+

+    KEEP (*crtbegin.o(.dtors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))

+    KEEP (*(SORT(.dtors.*)))

+    KEEP (*crtend.o(.dtors))

+

+    . = ALIGN(4);

+    __cs3_regions = .;

+    LONG (0)

+    LONG (__cs3_region_init_ram)

+    LONG (__cs3_region_start_ram)

+    LONG (__cs3_region_init_size_ram)

+    LONG (__cs3_region_zero_size_ram)

+  } >ram

+

+  /* .ARM.exidx is sorted, so has to go in its own output section.  */

+  /* even cs3.rom is in ram since its running as user code under the Maple

+     bootloader */

+  __exidx_start = .;

+  .ARM.exidx :

+  {

+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+  } >ram

+  __exidx_end = .;

+  .text.align :

+  {

+    . = ALIGN(8);

+    _etext = .;

+  } >ram

+

+  .cs3.rom :

+  {

+    __cs3_region_start_rom = .;

+    *(.cs3.region-head.rom)

+    *(.rom)

+    . = ALIGN (8);

+  } >ram

+

+  .cs3.rom.bss :

+  {

+    *(.rom.b)

+    . = ALIGN (8);

+  } >ram

+  /* __cs3_region_end_rom is deprecated */

+  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(ram);

+  __cs3_region_size_rom = LENGTH(ram);

+  __cs3_region_init_rom = LOADADDR (.cs3.rom);

+  __cs3_region_init_size_rom = SIZEOF(.cs3.rom);

+  __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);

+

+  .data :

+  {

+

+    KEEP(*(.jcr))

+    *(.got.plt) *(.got)

+    *(.shdata)

+    *(.data .data.* .gnu.linkonce.d.*)

+    *(.ram)

+    . = ALIGN (8);

+    _edata = .;

+  } >ram

+  .bss :

+  {

+    *(.shbss)

+    *(.bss .bss.* .gnu.linkonce.b.*)

+    *(COMMON)

+    *(.ram.b)

+    . = ALIGN (8);

+    _end = .;

+    __end = .;

+  } >ram

+  /* __cs3_region_end_ram is deprecated */

+  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);

+  __cs3_region_size_ram = LENGTH(ram);

+  __cs3_region_init_ram = LOADADDR (.text);

+  __cs3_region_init_size_ram = _edata - ADDR (.text);

+  __cs3_region_zero_size_ram = _end - _edata;

+  __cs3_region_num = 1;

+

+  .stab 0 (NOLOAD) : { *(.stab) }

+  .stabstr 0 (NOLOAD) : { *(.stabstr) }

+  /* DWARF debug sections.

+   * Symbols in the DWARF debugging sections are relative to the beginning

+   * of the section so we begin them at 0.  */

+  /* DWARF 1 */

+  .debug          0 : { *(.debug) }

+  .line           0 : { *(.line) }

+  /* GNU DWARF 1 extensions */

+  .debug_srcinfo  0 : { *(.debug_srcinfo) }

+  .debug_sfnames  0 : { *(.debug_sfnames) }

+  /* DWARF 1.1 and DWARF 2 */

+  .debug_aranges  0 : { *(.debug_aranges) }

+  .debug_pubnames 0 : { *(.debug_pubnames) }

+  /* DWARF 2 */

+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }

+  .debug_abbrev   0 : { *(.debug_abbrev) }

+  .debug_line     0 : { *(.debug_line) }

+  .debug_frame    0 : { *(.debug_frame) }

+  .debug_str      0 : { *(.debug_str) }

+  .debug_loc      0 : { *(.debug_loc) }

+  .debug_macinfo  0 : { *(.debug_macinfo) }

+  /* SGI/MIPS DWARF 2 extensions */

+  .debug_weaknames 0 : { *(.debug_weaknames) }

+  .debug_funcnames 0 : { *(.debug_funcnames) }

+  .debug_typenames 0 : { *(.debug_typenames) }

+  .debug_varnames  0 : { *(.debug_varnames) }

+

+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }

+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }

+  /DISCARD/ : { *(.note.GNU-stack) }

+}

+

diff --git a/wirish/boards.h b/wirish/boards.h
index ecb5f69..98c58ef 100644
--- a/wirish/boards.h
+++ b/wirish/boards.h
@@ -480,6 +480,108 @@ typedef struct PinMapping {
             *AFIO_MAPR = (*AFIO_MAPR | BIT(26)) & ~(BIT(25) | BIT(24)); \
         } while (0)
 
+#elif defined(BOARD_maple_RET6)
+
+    // Just like Maple, except PC6 -- PC9 have Timer 8 capture/compare
+    // channels 1 -- 4 hooked up (which makes PC9 an unfortunate
+    // choice for the button).
+
+    #define CYCLES_PER_MICROSECOND  72
+    #define SYSTICK_RELOAD_VAL      71999 /* takes a cycle to reload */
+
+    #define BOARD_BUTTON_PIN   38
+    #define BOARD_LED_PIN      13
+
+    static __attribute__ ((unused)) PinMapping PIN_MAP[NR_GPIO_PINS] = {
+        /* D0/PA3 */
+        {GPIOA_BASE,  3,        ADC3, TIMER2_CH4_CCR,  EXTI_CONFIG_PORTA, TIMER2, 4},
+        /* D1/PA2 */
+        {GPIOA_BASE,  2,        ADC2, TIMER2_CH3_CCR,  EXTI_CONFIG_PORTA, TIMER2, 3},
+        /* D2/PA0 */
+        {GPIOA_BASE,  0,        ADC0, TIMER2_CH1_CCR,  EXTI_CONFIG_PORTA, TIMER2, 1},
+        /* D3/PA1 */
+        {GPIOA_BASE,  1,        ADC1, TIMER2_CH2_CCR,  EXTI_CONFIG_PORTA, TIMER2, 2},
+        /* D4/PB5 */
+        {GPIOB_BASE,  5, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        /* D5/PB6 */
+        {GPIOB_BASE,  6, ADC_INVALID, TIMER4_CH1_CCR,  EXTI_CONFIG_PORTB, TIMER4, 1},
+        /* D6/PA8 */
+        {GPIOA_BASE,  8, ADC_INVALID, TIMER1_CH1_CCR,  EXTI_CONFIG_PORTA, TIMER1, 1},
+        /* D7/PA9 */
+        {GPIOA_BASE,  9, ADC_INVALID, TIMER1_CH2_CCR,  EXTI_CONFIG_PORTA, TIMER1, 2},
+        /* D8/PA10 */
+        {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR,  EXTI_CONFIG_PORTA, TIMER1, 3},
+        /* D9/PB7 */
+        {GPIOB_BASE,  7, ADC_INVALID, TIMER4_CH2_CCR,  EXTI_CONFIG_PORTB, TIMER4, 2},
+        /* D10/PA4 */
+        {GPIOA_BASE,  4,        ADC4,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        /* D11/PA7 */
+        {GPIOA_BASE,  7,        ADC7, TIMER3_CH2_CCR,  EXTI_CONFIG_PORTA, TIMER3, 2},
+        /* D12/PA6 */
+        {GPIOA_BASE,  6,        ADC6, TIMER3_CH1_CCR,  EXTI_CONFIG_PORTA, TIMER3, 1},
+        /* D13/PA5 */
+        {GPIOA_BASE,  5,        ADC5,              0,  EXTI_CONFIG_PORTA, TIMER_INVALID, TIMER_INVALID},
+        /* D14/PB8 */
+        {GPIOB_BASE,  8, ADC_INVALID, TIMER4_CH3_CCR,  EXTI_CONFIG_PORTB, TIMER4, 3},
+
+        /* Little header */
+
+        /* D15/PC0 */
+        {GPIOC_BASE,  0,       ADC10,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        /* D16/PC1 */
+        {GPIOC_BASE,  1,       ADC11,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        /* D17/PC2 */
+        {GPIOC_BASE,  2,       ADC12,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        /* D18/PC3 */
+        {GPIOC_BASE,  3,       ADC13,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        /* D19/PC4 */
+        {GPIOC_BASE,  4,       ADC14,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        /* D20/PC5 */
+        {GPIOC_BASE,  5,       ADC15,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+
+        /* External header */
+
+        /* D21/PC13 */
+        {GPIOC_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        /* D22/PC14 */
+        {GPIOC_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        /* D23/PC15 */
+        {GPIOC_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        /* D24/PB9 */
+        {GPIOB_BASE,  9, ADC_INVALID, TIMER4_CH4_CCR,  EXTI_CONFIG_PORTB, TIMER4,                    4},
+        /* D25/PD2 */
+        {GPIOD_BASE,  2, ADC_INVALID,              0,  EXTI_CONFIG_PORTD, TIMER_INVALID, TIMER_INVALID},
+        /* D26/PC10 */
+        {GPIOC_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTC, TIMER_INVALID, TIMER_INVALID},
+        /* D27/PB0 */
+        {GPIOB_BASE,  0,        ADC8, TIMER3_CH3_CCR,  EXTI_CONFIG_PORTB, TIMER3, 3},
+        /* D28/PB1 */
+        {GPIOB_BASE,  1,        ADC9, TIMER3_CH4_CCR,  EXTI_CONFIG_PORTB, TIMER3, 4},
+        /* D29/PB10 */
+        {GPIOB_BASE, 10, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        /* D30/PB11 */
+        {GPIOB_BASE, 11, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        /* D31/PB12 */
+        {GPIOB_BASE, 12, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        /* D32/PB13 */
+        {GPIOB_BASE, 13, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        /* D33/PB14 */
+        {GPIOB_BASE, 14, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        /* D34/PB15 */
+        {GPIOB_BASE, 15, ADC_INVALID,              0,  EXTI_CONFIG_PORTB, TIMER_INVALID, TIMER_INVALID},
+        /* D35/PC6 */
+        {GPIOC_BASE,  6, ADC_INVALID, TIMER8_CH1_CCR,  EXTI_CONFIG_PORTC,        TIMER8,             1},
+        /* D36/PC7 */
+        {GPIOC_BASE,  7, ADC_INVALID, TIMER8_CH2_CCR,  EXTI_CONFIG_PORTC,        TIMER8,             2},
+        /* D37/PC8 */
+        {GPIOC_BASE,  8, ADC_INVALID, TIMER8_CH3_CCR,  EXTI_CONFIG_PORTC,        TIMER8,             3},
+        /* D38/PC9 (BUT) */
+        {GPIOC_BASE,  9, ADC_INVALID, TIMER8_CH4_CCR,  EXTI_CONFIG_PORTC,        TIMER8,             4}
+    };
+
+    #define BOARD_INIT do {                           \
+        } while(0)
+
 #else
 
 #error "Board type has not been selected correctly."