added USB support (TX over virtual com port), the linker modifications to work with the bootloader, a modified libcs-lanchon-stm32.a, and the arduino-required main.cxx and WProgram.h

git-svn-id: https://leaflabs.googlecode.com/svn/trunk/library@72 749a229e-a60e-11de-b98f-4500b42dc123

14 files changed, 1148 insertions, 8 deletions

diff --git a/Makefile b/Makefile
index 00db7a9..8da91d2 100644
--- a/Makefile
+++ b/Makefile
@@ -33,15 +33,17 @@ INCLUDES = -Isrc/stm32lib/inc \
 	   -Isrc/wiring \
 	   -Isrc/wiring/comm
 
+DEFFLAGS=VECT_TAB_BASE
 CFLAGS  =  -I./ $(INCLUDES) -c \
            -Os\
            -g -mcpu=cortex-m3 -mthumb  -march=armv7-m -nostdlib \
-           -ffunction-sections -fdata-sections -Wl,--gc-sections
-
+           -ffunction-sections -fdata-sections -Wl,--gc-sections \
+	   -D$(DEFFLAGS)
 
 CPPFLAGS = -fno-rtti -fno-exceptions -Wall
 
-LFLAGS  = -Tstm32conf/lanchon-stm32.ld -L stm32conf/lanchon-stm32 \
+LINKER=lanchon-stm32.ld
+LFLAGS  = -Tstm32conf/$(LINKER) -L stm32conf/lanchon-stm32 \
           -mcpu=cortex-m3 -mthumb -Xlinker \
           --gc-sections --print-gc-sections --march=armv7-m -Wall
 
@@ -63,6 +65,7 @@ CSRC = lib/systick.c                        \
 	   lib/exti.c 			    \
 	   lib/gpio.c 			    \
 	   lib/usart.c 			    \
+	   lib/usb.c                        \
 	   wiring/wiring.c 		    \
 	   wiring/wiring_shift.c            \
 	   wiring/wiring_analog.c           \
diff --git a/src/lib/usb.c b/src/lib/usb.c
new file mode 100644
index 0000000..e0d7d42
--- /dev/null
+++ b/src/lib/usb.c
@@ -0,0 +1,56 @@
+#include "usb.h"
+#include <inttypes.h>
+
+void usb_lpIRQHandler(void)
+{
+  typedef void (*funcPtr)(void);
+  
+  const uint32_t usbIsrAddr = *(uint32_t*)(USB_ISR_ADDR);
+  void (*ptrToUsbISR)(void) = (funcPtr) usbIsrAddr;
+  ptrToUsbISR();
+}
+
+void UserToPMABufferCopy(u8 *pbUsrBuf, u16 wPMABufAddr, u16 wNBytes)
+{
+  u32 n = (wNBytes + 1) >> 1;   /* n = (wNBytes + 1) / 2 */
+  u32 i, temp1, temp2;
+  u16 *pdwVal;
+  pdwVal = (u16 *)(wPMABufAddr * 2 + PMAAddr);
+  for (i = n; i != 0; i--)
+    {
+      temp1 = (u16) * pbUsrBuf;
+      pbUsrBuf++;
+      temp2 = temp1 | (u16) * pbUsrBuf << 8;
+      *pdwVal++ = temp2;
+      pdwVal++;
+      pbUsrBuf++;
+    }
+}
+
+void PMAToUserBufferCopy(u8 *pbUsrBuf, u16 wPMABufAddr, u16 wNBytes)
+{
+  u32 n = (wNBytes + 1) >> 1;/* /2*/
+  u32 i;
+  u32 *pdwVal;
+  pdwVal = (u32 *)(wPMABufAddr * 2 + PMAAddr);
+  for (i = n; i != 0; i--)
+    {
+      *(u16*)pbUsrBuf++ = *pdwVal++;
+      pbUsrBuf++;
+    }
+}
+
+void serialWriteStr(char* outStr) {
+  u8 offset=0;
+  while ((outStr[offset] != 0)
+	 && (offset < USB_SERIAL_BUF_SIZE)) {
+    offset++;
+  }
+
+  while (_GetEPTxCount(USB_SERIAL_ENDP_TX) > 0) {}
+
+  UserToPMABufferCopy(outStr,USB_SERIAL_ENDP_TXADDR,offset);
+  _SetEPTxCount(USB_SERIAL_ENDP_TX,offset);
+  _SetEPTxValid(USB_SERIAL_ENDP_TX);
+}
+
diff --git a/src/lib/usb.h b/src/lib/usb.h
new file mode 100644
index 0000000..be632dd
--- /dev/null
+++ b/src/lib/usb.h
@@ -0,0 +1,33 @@
+#ifndef _USB_H_
+#define _USB_H_
+
+#include <inttypes.h>
+#include "util.h"
+#include "cortexm3_macro.h"
+#include "usb_regs.h"
+
+#ifdef __cpluscplus
+extern "C" {
+#endif
+
+#define USB_ISR_ADDR              (0x08000090)
+#define USB_SERIAL_ENDP_TXADDR    ((uint32_t) 0xC0)
+#define USB_SERIAL_ENDP_RXADDR    ((uint32_t) 0x110)
+#define USB_SERIAL_ENDP_TX        ((uint16_t) 0x1)
+#define USB_SERIAL_ENDP_RX        ((uint16_t) 0x3)
+#define USB_SERIAL_BUF_SIZE       (0x40)
+
+void usb_lpIRQHandler(void);  
+void usb_userToPMABufferCopy(uint8_t  *pbUsrBuf,
+			     uint16_t *wPMABufAddr,
+			     uint16_t *wNBytes);
+void usb_PMABToUserufferCopy(uint8_t  *pbUsrBuf,
+			     uint16_t *wPMABufAddr,
+			     uint16_t *wNBytes);
+void usb_serialWriteStr(char* str);
+
+
+#ifdef __cpluscplus
+} // extern "C"
+#endif
+#endif //_USB_H
diff --git a/src/lib/usb_regs.h b/src/lib/usb_regs.h
new file mode 100644
index 0000000..135d645
--- /dev/null
+++ b/src/lib/usb_regs.h
@@ -0,0 +1,555 @@
+/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************

+* File Name          : usb_regs.h

+* Author             : MCD Application Team

+* Version            : V2.2.1

+* Date               : 09/22/2008

+* Description        : Interface prototype functions to USB cell registers

+********************************************************************************

+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.

+* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,

+* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE

+* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING

+* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

+*******************************************************************************/

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __USB_REGS_H

+#define __USB_REGS_H

+

+/* Includes ------------------------------------------------------------------*/

+/* Exported types ------------------------------------------------------------*/

+#include "stm32f10x_type.h"

+

+typedef enum _EP_DBUF_DIR

+{

+  /* double buffered endpoint direction */

+  EP_DBUF_ERR,

+  EP_DBUF_OUT,

+  EP_DBUF_IN

+}EP_DBUF_DIR;

+

+/* endpoint buffer number */

+enum EP_BUF_NUM

+{

+  EP_NOBUF,

+  EP_BUF0,

+  EP_BUF1

+};

+

+/* Exported constants --------------------------------------------------------*/

+#define RegBase  (0x40005C00L)  /* USB_IP Peripheral Registers base address */

+#define PMAAddr  (0x40006000L)  /* USB_IP Packet Memory Area base address   */

+

+/******************************************************************************/

+/*                         General registers                                  */

+/******************************************************************************/

+

+/* Control register */

+#define CNTR    ((volatile unsigned *)(RegBase + 0x40))

+/* Interrupt status register */

+#define ISTR    ((volatile unsigned *)(RegBase + 0x44))

+/* Frame number register */

+#define FNR     ((volatile unsigned *)(RegBase + 0x48))

+/* Device address register */

+#define DADDR   ((volatile unsigned *)(RegBase + 0x4C))

+/* Buffer Table address register */

+#define BTABLE  ((volatile unsigned *)(RegBase + 0x50))

+/******************************************************************************/

+/*                         Endpoint registers                                 */

+/******************************************************************************/

+#define EP0REG  ((volatile unsigned *)(RegBase)) /* endpoint 0 register address */

+

+/* endpoints enumeration */

+#define ENDP0   ((u8)0)

+#define ENDP1   ((u8)1)

+#define ENDP2   ((u8)2)

+#define ENDP3   ((u8)3)

+#define ENDP4   ((u8)4)

+#define ENDP5   ((u8)5)

+#define ENDP6   ((u8)6)

+#define ENDP7   ((u8)7)

+/******************************************************************************/

+/*                       ISTR interrupt events                                */

+/******************************************************************************/

+#define ISTR_CTR    (0x8000) /* Correct TRansfer (clear-only bit) */

+#define ISTR_DOVR   (0x4000) /* DMA OVeR/underrun (clear-only bit) */

+#define ISTR_ERR    (0x2000) /* ERRor (clear-only bit) */

+#define ISTR_WKUP   (0x1000) /* WaKe UP (clear-only bit) */

+#define ISTR_SUSP   (0x0800) /* SUSPend (clear-only bit) */

+#define ISTR_RESET  (0x0400) /* RESET (clear-only bit) */

+#define ISTR_SOF    (0x0200) /* Start Of Frame (clear-only bit) */

+#define ISTR_ESOF   (0x0100) /* Expected Start Of Frame (clear-only bit) */

+

+

+#define ISTR_DIR    (0x0010)  /* DIRection of transaction (read-only bit)  */

+#define ISTR_EP_ID  (0x000F)  /* EndPoint IDentifier (read-only bit)  */

+

+#define CLR_CTR    (~ISTR_CTR)   /* clear Correct TRansfer bit */

+#define CLR_DOVR   (~ISTR_DOVR)  /* clear DMA OVeR/underrun bit*/

+#define CLR_ERR    (~ISTR_ERR)   /* clear ERRor bit */

+#define CLR_WKUP   (~ISTR_WKUP)  /* clear WaKe UP bit     */

+#define CLR_SUSP   (~ISTR_SUSP)  /* clear SUSPend bit     */

+#define CLR_RESET  (~ISTR_RESET) /* clear RESET bit      */

+#define CLR_SOF    (~ISTR_SOF)   /* clear Start Of Frame bit   */

+#define CLR_ESOF   (~ISTR_ESOF)  /* clear Expected Start Of Frame bit */

+

+/******************************************************************************/

+/*             CNTR control register bits definitions                         */

+/******************************************************************************/

+#define CNTR_CTRM   (0x8000) /* Correct TRansfer Mask */

+#define CNTR_DOVRM  (0x4000) /* DMA OVeR/underrun Mask */

+#define CNTR_ERRM   (0x2000) /* ERRor Mask */

+#define CNTR_WKUPM  (0x1000) /* WaKe UP Mask */

+#define CNTR_SUSPM  (0x0800) /* SUSPend Mask */

+#define CNTR_RESETM (0x0400) /* RESET Mask   */

+#define CNTR_SOFM   (0x0200) /* Start Of Frame Mask */

+#define CNTR_ESOFM  (0x0100) /* Expected Start Of Frame Mask */

+

+

+#define CNTR_RESUME (0x0010) /* RESUME request */

+#define CNTR_FSUSP  (0x0008) /* Force SUSPend */

+#define CNTR_LPMODE (0x0004) /* Low-power MODE */

+#define CNTR_PDWN   (0x0002) /* Power DoWN */

+#define CNTR_FRES   (0x0001) /* Force USB RESet */

+

+/******************************************************************************/

+/*                FNR Frame Number Register bit definitions                   */

+/******************************************************************************/

+#define FNR_RXDP (0x8000) /* status of D+ data line */

+#define FNR_RXDM (0x4000) /* status of D- data line */

+#define FNR_LCK  (0x2000) /* LoCKed */

+#define FNR_LSOF (0x1800) /* Lost SOF */

+#define FNR_FN  (0x07FF) /* Frame Number */

+/******************************************************************************/

+/*               DADDR Device ADDRess bit definitions                         */

+/******************************************************************************/

+#define DADDR_EF (0x80)

+#define DADDR_ADD (0x7F)

+/******************************************************************************/

+/*                            Endpoint register                               */

+/******************************************************************************/

+/* bit positions */

+#define EP_CTR_RX      (0x8000) /* EndPoint Correct TRansfer RX */

+#define EP_DTOG_RX     (0x4000) /* EndPoint Data TOGGLE RX */

+#define EPRX_STAT      (0x3000) /* EndPoint RX STATus bit field */

+#define EP_SETUP       (0x0800) /* EndPoint SETUP */

+#define EP_T_FIELD     (0x0600) /* EndPoint TYPE */

+#define EP_KIND        (0x0100) /* EndPoint KIND */

+#define EP_CTR_TX      (0x0080) /* EndPoint Correct TRansfer TX */

+#define EP_DTOG_TX     (0x0040) /* EndPoint Data TOGGLE TX */

+#define EPTX_STAT      (0x0030) /* EndPoint TX STATus bit field */

+#define EPADDR_FIELD   (0x000F) /* EndPoint ADDRess FIELD */

+

+/* EndPoint REGister MASK (no toggle fields) */

+#define EPREG_MASK     (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD)

+

+/* EP_TYPE[1:0] EndPoint TYPE */

+#define EP_TYPE_MASK   (0x0600) /* EndPoint TYPE Mask */

+#define EP_BULK        (0x0000) /* EndPoint BULK */

+#define EP_CONTROL     (0x0200) /* EndPoint CONTROL */

+#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */

+#define EP_INTERRUPT   (0x0600) /* EndPoint INTERRUPT */

+#define EP_T_MASK      (~EP_T_FIELD & EPREG_MASK)

+

+

+/* EP_KIND EndPoint KIND */

+#define EPKIND_MASK    (~EP_KIND & EPREG_MASK)

+

+/* STAT_TX[1:0] STATus for TX transfer */

+#define EP_TX_DIS      (0x0000) /* EndPoint TX DISabled */

+#define EP_TX_STALL    (0x0010) /* EndPoint TX STALLed */

+#define EP_TX_NAK      (0x0020) /* EndPoint TX NAKed */

+#define EP_TX_VALID    (0x0030) /* EndPoint TX VALID */

+#define EPTX_DTOG1     (0x0010) /* EndPoint TX Data TOGgle bit1 */

+#define EPTX_DTOG2     (0x0020) /* EndPoint TX Data TOGgle bit2 */

+#define EPTX_DTOGMASK  (EPTX_STAT|EPREG_MASK)

+

+/* STAT_RX[1:0] STATus for RX transfer */

+#define EP_RX_DIS      (0x0000) /* EndPoint RX DISabled */

+#define EP_RX_STALL    (0x1000) /* EndPoint RX STALLed */

+#define EP_RX_NAK      (0x2000) /* EndPoint RX NAKed */

+#define EP_RX_VALID    (0x3000) /* EndPoint RX VALID */

+#define EPRX_DTOG1     (0x1000) /* EndPoint RX Data TOGgle bit1 */

+#define EPRX_DTOG2     (0x2000) /* EndPoint RX Data TOGgle bit1 */

+#define EPRX_DTOGMASK  (EPRX_STAT|EPREG_MASK)

+/* Exported macro ------------------------------------------------------------*/

+/* SetCNTR */

+#define _SetCNTR(wRegValue)  (*CNTR   = (u16)wRegValue)

+

+/* SetISTR */

+#define _SetISTR(wRegValue)  (*ISTR   = (u16)wRegValue)

+

+/* SetDADDR */

+#define _SetDADDR(wRegValue) (*DADDR  = (u16)wRegValue)

+

+/* SetBTABLE */

+#define _SetBTABLE(wRegValue)(*BTABLE = (u16)(wRegValue & 0xFFF8))

+

+/* GetCNTR */

+#define _GetCNTR()   ((u16) *CNTR)

+

+/* GetISTR */

+#define _GetISTR()   ((u16) *ISTR)

+

+/* GetFNR */

+#define _GetFNR()    ((u16) *FNR)

+

+/* GetDADDR */

+#define _GetDADDR()  ((u16) *DADDR)

+

+/* GetBTABLE */

+#define _GetBTABLE() ((u16) *BTABLE)

+

+/* SetENDPOINT */

+#define _SetENDPOINT(bEpNum,wRegValue)  (*(EP0REG + bEpNum)= \

+    (u16)wRegValue)

+

+/* GetENDPOINT */

+#define _GetENDPOINT(bEpNum)        ((u16)(*(EP0REG + bEpNum)))

+

+/*******************************************************************************

+* Macro Name     : SetEPType

+* Description    : sets the type in the endpoint register(bits EP_TYPE[1:0])

+* Input          : bEpNum: Endpoint Number. 

+*                  wType

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\

+                                  ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType)))

+

+/*******************************************************************************

+* Macro Name     : GetEPType

+* Description    : gets the type in the endpoint register(bits EP_TYPE[1:0]) 

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : Endpoint Type

+*******************************************************************************/

+#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)

+

+/*******************************************************************************

+* Macro Name     : SetEPTxStatus

+* Description    : sets the status for tx transfer (bits STAT_TX[1:0]).

+* Input          : bEpNum: Endpoint Number. 

+*                  wState: new state

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPTxStatus(bEpNum,wState) {\

+    register u16 _wRegVal;       \

+    _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\

+    /* toggle first bit ? */     \

+    if((EPTX_DTOG1 & wState)!= 0)      \

+      _wRegVal ^= EPTX_DTOG1;        \

+    /* toggle second bit ?  */         \

+    if((EPTX_DTOG2 & wState)!= 0)      \

+      _wRegVal ^= EPTX_DTOG2;        \

+    _SetENDPOINT(bEpNum, _wRegVal);    \

+  } /* _SetEPTxStatus */

+

+/*******************************************************************************

+* Macro Name     : SetEPRxStatus

+* Description    : sets the status for rx transfer (bits STAT_TX[1:0])

+* Input          : bEpNum: Endpoint Number. 

+*                  wState: new state.

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPRxStatus(bEpNum,wState) {\

+    register u16 _wRegVal;   \

+    \

+    _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\

+    /* toggle first bit ? */  \

+    if((EPRX_DTOG1 & wState)!= 0) \

+      _wRegVal ^= EPRX_DTOG1;  \

+    /* toggle second bit ? */  \

+    if((EPRX_DTOG2 & wState)!= 0) \

+      _wRegVal ^= EPRX_DTOG2;  \

+    _SetENDPOINT(bEpNum, _wRegVal); \

+  } /* _SetEPRxStatus */

+/*******************************************************************************

+* Macro Name     : GetEPTxStatus / GetEPRxStatus 

+* Description    : gets the status for tx/rx transfer (bits STAT_TX[1:0]

+*                  /STAT_RX[1:0])

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : status .

+*******************************************************************************/

+#define _GetEPTxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPTX_STAT)

+

+#define _GetEPRxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPRX_STAT)

+

+/*******************************************************************************

+* Macro Name     : SetEPTxValid / SetEPRxValid 

+* Description    : sets directly the VALID tx/rx-status into the enpoint register

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPTxValid(bEpNum)     (_SetEPTxStatus(bEpNum, EP_TX_VALID))

+

+#define _SetEPRxValid(bEpNum)     (_SetEPRxStatus(bEpNum, EP_RX_VALID))

+

+/*******************************************************************************

+* Macro Name     : GetTxStallStatus / GetRxStallStatus.

+* Description    : checks stall condition in an endpoint.

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : TRUE = endpoint in stall condition.

+*******************************************************************************/

+#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \

+                                   == EP_TX_STALL)

+#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \

+                                   == EP_RX_STALL)

+

+/*******************************************************************************

+* Macro Name     : SetEP_KIND / ClearEP_KIND.

+* Description    : set & clear EP_KIND bit.

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEP_KIND(bEpNum)    (_SetENDPOINT(bEpNum, \

+                                (_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))

+#define _ClearEP_KIND(bEpNum)  (_SetENDPOINT(bEpNum, \

+                                (_GetENDPOINT(bEpNum) & EPKIND_MASK)))

+

+/*******************************************************************************

+* Macro Name     : Set_Status_Out / Clear_Status_Out.

+* Description    : Sets/clears directly STATUS_OUT bit in the endpoint register.

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _Set_Status_Out(bEpNum)    _SetEP_KIND(bEpNum)

+#define _Clear_Status_Out(bEpNum)  _ClearEP_KIND(bEpNum)

+

+/*******************************************************************************

+* Macro Name     : SetEPDoubleBuff / ClearEPDoubleBuff.

+* Description    : Sets/clears directly EP_KIND bit in the endpoint register.

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPDoubleBuff(bEpNum)   _SetEP_KIND(bEpNum)

+#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)

+

+/*******************************************************************************

+* Macro Name     : ClearEP_CTR_RX / ClearEP_CTR_TX.

+* Description    : Clears bit CTR_RX / CTR_TX in the endpoint register.

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _ClearEP_CTR_RX(bEpNum)   (_SetENDPOINT(bEpNum,\

+                                   _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))

+#define _ClearEP_CTR_TX(bEpNum)   (_SetENDPOINT(bEpNum,\

+                                   _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))

+

+/*******************************************************************************

+* Macro Name     : ToggleDTOG_RX / ToggleDTOG_TX .

+* Description    : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _ToggleDTOG_RX(bEpNum)    (_SetENDPOINT(bEpNum, \

+                                   EP_DTOG_RX | _GetENDPOINT(bEpNum) & EPREG_MASK))

+#define _ToggleDTOG_TX(bEpNum)    (_SetENDPOINT(bEpNum, \

+                                   EP_DTOG_TX | _GetENDPOINT(bEpNum) & EPREG_MASK))

+

+/*******************************************************************************

+* Macro Name     : ClearDTOG_RX / ClearDTOG_TX.

+* Description    : Clears DTOG_RX / DTOG_TX bit in the endpoint register.

+* Input          : bEpNum: Endpoint Number. 

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _ClearDTOG_RX(bEpNum)  if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\

+    _ToggleDTOG_RX(bEpNum)

+#define _ClearDTOG_TX(bEpNum)  if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\

+    _ToggleDTOG_TX(bEpNum)

+/*******************************************************************************

+* Macro Name     : SetEPAddress.

+* Description    : Sets address in an endpoint register.

+* Input          : bEpNum: Endpoint Number.

+*                  bAddr: Address. 

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\

+    _GetENDPOINT(bEpNum) & EPREG_MASK | bAddr)

+

+/*******************************************************************************

+* Macro Name     : GetEPAddress.

+* Description    : Gets address in an endpoint register.

+* Input          : bEpNum: Endpoint Number.

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _GetEPAddress(bEpNum) ((u8)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))

+

+#define _pEPTxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8  )*2 + PMAAddr))

+#define _pEPTxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr))

+#define _pEPRxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr))

+#define _pEPRxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr))

+

+/*******************************************************************************

+* Macro Name     : SetEPTxAddr / SetEPRxAddr.

+* Description    : sets address of the tx/rx buffer.

+* Input          : bEpNum: Endpoint Number.

+*                  wAddr: address to be set (must be word aligned).

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))

+#define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))

+

+/*******************************************************************************

+* Macro Name     : GetEPTxAddr / GetEPRxAddr.

+* Description    : Gets address of the tx/rx buffer.

+* Input          : bEpNum: Endpoint Number.

+* Output         : None.

+* Return         : address of the buffer.

+*******************************************************************************/

+#define _GetEPTxAddr(bEpNum) ((u16)*_pEPTxAddr(bEpNum))

+#define _GetEPRxAddr(bEpNum) ((u16)*_pEPRxAddr(bEpNum))

+

+/*******************************************************************************

+* Macro Name     : SetEPCountRxReg.

+* Description    : Sets counter of rx buffer with no. of blocks.

+* Input          : pdwReg: pointer to counter.

+*                  wCount: Counter.

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _BlocksOf32(dwReg,wCount,wNBlocks) {\

+    wNBlocks = wCount >> 5;\

+    if((wCount & 0x1f) == 0)\

+      wNBlocks--;\

+    *pdwReg = (u32)((wNBlocks << 10) | 0x8000);\

+  }/* _BlocksOf32 */

+

+#define _BlocksOf2(dwReg,wCount,wNBlocks) {\

+    wNBlocks = wCount >> 1;\

+    if((wCount & 0x1) != 0)\

+      wNBlocks++;\

+    *pdwReg = (u32)(wNBlocks << 10);\

+  }/* _BlocksOf2 */

+

+#define _SetEPCountRxReg(dwReg,wCount)  {\

+    u16 wNBlocks;\

+    if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\

+    else {_BlocksOf2(dwReg,wCount,wNBlocks);}\

+  }/* _SetEPCountRxReg */

+

+

+

+#define _SetEPRxDblBuf0Count(bEpNum,wCount) {\

+    u32 *pdwReg = _pEPTxCount(bEpNum); \

+    _SetEPCountRxReg(pdwReg, wCount);\

+  }

+/*******************************************************************************

+* Macro Name     : SetEPTxCount / SetEPRxCount.

+* Description    : sets counter for the tx/rx buffer.

+* Input          : bEpNum: endpoint number.

+*                  wCount: Counter value.

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount)

+#define _SetEPRxCount(bEpNum,wCount) {\

+    u32 *pdwReg = _pEPRxCount(bEpNum); \

+    _SetEPCountRxReg(pdwReg, wCount);\

+  }

+/*******************************************************************************

+* Macro Name     : GetEPTxCount / GetEPRxCount.

+* Description    : gets counter of the tx buffer.

+* Input          : bEpNum: endpoint number.

+* Output         : None.

+* Return         : Counter value.

+*******************************************************************************/

+#define _GetEPTxCount(bEpNum)((u16)(*_pEPTxCount(bEpNum)) & 0x3ff)

+#define _GetEPRxCount(bEpNum)((u16)(*_pEPRxCount(bEpNum)) & 0x3ff)

+

+/*******************************************************************************

+* Macro Name     : SetEPDblBuf0Addr / SetEPDblBuf1Addr.

+* Description    : Sets buffer 0/1 address in a double buffer endpoint.

+* Input          : bEpNum: endpoint number.

+*                : wBuf0Addr: buffer 0 address.

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);}

+#define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);}

+

+/*******************************************************************************

+* Macro Name     : SetEPDblBuffAddr.

+* Description    : Sets addresses in a double buffer endpoint.

+* Input          : bEpNum: endpoint number.

+*                : wBuf0Addr: buffer 0 address.

+*                : wBuf1Addr = buffer 1 address.

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \

+    _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\

+    _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\

+  } /* _SetEPDblBuffAddr */

+

+/*******************************************************************************

+* Macro Name     : GetEPDblBuf0Addr / GetEPDblBuf1Addr.

+* Description    : Gets buffer 0/1 address of a double buffer endpoint.

+* Input          : bEpNum: endpoint number.

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))

+#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))

+

+/*******************************************************************************

+* Macro Name     : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count.

+* Description    : Gets buffer 0/1 address of a double buffer endpoint.

+* Input          : bEpNum: endpoint number.

+*                : bDir: endpoint dir  EP_DBUF_OUT = OUT 

+*                                      EP_DBUF_IN  = IN 

+*                : wCount: Counter value    

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _SetEPDblBuf0Count(bEpNum, bDir, wCount)  { \

+    if(bDir == EP_DBUF_OUT)\

+      /* OUT endpoint */ \

+    {_SetEPRxDblBuf0Count(bEpNum,wCount);} \

+    else if(bDir == EP_DBUF_IN)\

+      /* IN endpoint */ \

+      *_pEPTxCount(bEpNum) = (u32)wCount;  \

+  } /* SetEPDblBuf0Count*/

+

+#define _SetEPDblBuf1Count(bEpNum, bDir, wCount)  { \

+    if(bDir == EP_DBUF_OUT)\

+      /* OUT endpoint */ \

+    {_SetEPRxCount(bEpNum,wCount);}\

+    else if(bDir == EP_DBUF_IN)\

+      /* IN endpoint */\

+      *_pEPRxCount(bEpNum) = (u32)wCount; \

+  } /* SetEPDblBuf1Count */

+

+#define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\

+    _SetEPDblBuf0Count(bEpNum, bDir, wCount); \

+    _SetEPDblBuf1Count(bEpNum, bDir, wCount); \

+  } /* _SetEPDblBuffCount  */

+

+/*******************************************************************************

+* Macro Name     : GetEPDblBuf0Count / GetEPDblBuf1Count.

+* Description    : Gets buffer 0/1 rx/tx counter for double buffering.

+* Input          : bEpNum: endpoint number.

+* Output         : None.

+* Return         : None.

+*******************************************************************************/

+#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))

+#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))

+

+#endif

+/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/

diff --git a/src/main.cxx b/src/main.cxx
new file mode 100644
index 0000000..7734d6e
--- /dev/null
+++ b/src/main.cxx
@@ -0,0 +1,21 @@
+int main(void)

+{

+    init();

+    setup();

+

+    while (1) {

+        loop();

+    }

+    return 0;

+}

+

+

+/* Implemented:

+ * void pinMode(pin, mode) 

+ * void digitalWrite(pin, value)

+ * uint32_t digitalRead(pin)

+ * uint32_t analogRead(pin)

+ * void randomSeed(seed)

+ * long random(max)

+ * long random(min, max)

+ * */

diff --git a/src/wiring/WProgram.h b/src/wiring/WProgram.h
new file mode 100644
index 0000000..111c7dc
--- /dev/null
+++ b/src/wiring/WProgram.h
@@ -0,0 +1,18 @@
+#include "stm32f10x_map.h"
+#include "stm32f10x_lib.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_usart.h"
+#include "Serial.h"
+#include "timers.h"
+#include "wiring.h"
+#include "util.h"
+#include "systick.h"
+#include "adc.h"
+#include "gpio.h"
+#include "pwm.h"
+#include "ext_interrupts.h"
+#include "usart.h"
+#include "usb.h"
+
+void setup();
+void loop();
diff --git a/src/wiring/wiring.c b/src/wiring/wiring.c
index 83679c7..bedce55 100644
--- a/src/wiring/wiring.c
+++ b/src/wiring/wiring.c
@@ -33,8 +33,14 @@ void init(void) {
 }
 
 void NVIC_Configuration(void) {
+#ifdef VECT_TAB_ROM
+  NVIC_SetVectorTable(USER_ADDR_ROM, 0x0);
+#elifdef VECT_TAB_RAM
+  NVIC_SetVectorTable(USER_ADDR_RAM, 0x0);
+#else // VECT_TAB_BASE
    /* Set the Vector Table base location at 0x08000000 */
-   NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+  NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
 }
 
 
diff --git a/src/wiring/wiring.h b/src/wiring/wiring.h
index 789e697..4bf93bc 100644
--- a/src/wiring/wiring.h
+++ b/src/wiring/wiring.h
@@ -26,6 +26,9 @@ extern "C"{
 #define LSBFIRST 0
 #define MSBFIRST 1
 
+#define USER_ADDR_ROM 0x08005000
+#define USER_ADDR_RAM 0x20000C00
+
 #define lowByte(w) ((w) & 0xff)
 #define highByte(w) ((w) >> 8)
 #define bitRead(value, bit) (((value) >> (bit)) & 0x01)
diff --git a/stm32conf/lanchon-stm32-user-ram.ld b/stm32conf/lanchon-stm32-user-ram.ld
new file mode 100644
index 0000000..297de5c
--- /dev/null
+++ b/stm32conf/lanchon-stm32-user-ram.ld
@@ -0,0 +1,220 @@
+/* Linker script for STM32 (by Lanchon with Mods by LeafLabs)

+ *

+ * Version:Sourcery G++ 4.2-84

+ * BugURL:https://support.codesourcery.com/GNUToolchain/

+ *

+ *  Copyright 2007 CodeSourcery.

+ *

+ * The authors hereby grant permission to use, copy, modify, distribute,

+ * and license this software and its documentation for any purpose, provided

+ * that existing copyright notices are retained in all copies and that this

+ * notice is included verbatim in any distributions. No written agreement,

+ * license, or royalty fee is required for any of the authorized uses.

+ * Modifications to this software may be copyrighted by their authors

+ * and need not follow the licensing terms described here, provided that

+ * the new terms are clearly indicated on the first page of each file where

+ * they apply. */

+

+/* Linker script for STM32 (by Lanchon),

+ * ROM and RAM relocated to their positions 

+ * as placed by Maple bootloader

+ *

+ * Configure target memory and included script

+ * according to your application requirements. */

+

+/* Define memory spaces. */

+MEMORY

+{

+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K

+  rom (rx) : ORIGIN = 0x00000000, LENGTH = 0K

+}

+

+

+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

+ENTRY(_start)

+SEARCH_DIR(.)

+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */

+GROUP(libgcc.a libc.a libcs3.a libcs3unhosted.a libcs3-lanchon-stm32.a)

+

+/* These force the linker to search for particular symbols from

+ * the start of the link process and thus ensure the user's

+ * overrides are picked up

+ */

+EXTERN(__cs3_reset_lanchon_stm32)

+INCLUDE lanchon-stm32-names.inc

+EXTERN(__cs3_interrupt_vector_lanchon_stm32)

+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)

+EXTERN(_start)

+

+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);

+PROVIDE(__cs3_heap_start = _end);

+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);

+

+SECTIONS

+{

+  .text :

+  {

+    CREATE_OBJECT_SYMBOLS

+    __cs3_region_start_ram = .;

+    *(.cs3.region-head.ram)

+    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;

+    *(.cs3.interrupt_vector)

+    /* Make sure we pulled in an interrupt vector.  */

+    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");

+

+    PROVIDE(__cs3_reset_lanchon_stm32 = _start);

+    __cs3_reset = __cs3_reset_lanchon_stm32;

+    *(.cs3.reset)

+

+    *(.text .text.* .gnu.linkonce.t.*)

+    *(.plt)

+    *(.gnu.warning)

+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)

+

+    *(.rodata .rodata.* .gnu.linkonce.r.*)

+

+    *(.ARM.extab* .gnu.linkonce.armextab.*)

+    *(.gcc_except_table)

+    *(.eh_frame_hdr)

+    *(.eh_frame)

+

+    . = ALIGN(4);

+    KEEP(*(.init))

+

+    . = ALIGN(4);

+    __preinit_array_start = .;

+    KEEP (*(.preinit_array))

+    __preinit_array_end = .;

+

+    . = ALIGN(4);

+    __init_array_start = .;

+    KEEP (*(SORT(.init_array.*)))

+    KEEP (*(.init_array))

+    __init_array_end = .;

+

+    . = ALIGN(0x4);

+    KEEP (*crtbegin.o(.ctors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))

+    KEEP (*(SORT(.ctors.*)))

+    KEEP (*crtend.o(.ctors))

+

+    . = ALIGN(4);

+    KEEP(*(.fini))

+

+    . = ALIGN(4);

+    __fini_array_start = .;

+    KEEP (*(.fini_array))

+    KEEP (*(SORT(.fini_array.*)))

+    __fini_array_end = .;

+

+    KEEP (*crtbegin.o(.dtors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))

+    KEEP (*(SORT(.dtors.*)))

+    KEEP (*crtend.o(.dtors))

+

+    . = ALIGN(4);

+    __cs3_regions = .;

+    LONG (0)

+    LONG (__cs3_region_init_ram)

+    LONG (__cs3_region_start_ram)

+    LONG (__cs3_region_init_size_ram)

+    LONG (__cs3_region_zero_size_ram)

+  } >ram

+

+  /* .ARM.exidx is sorted, so has to go in its own output section.  */

+  /* even cs3.rom is in ram since its running as user code under the Maple

+     bootloader */

+  __exidx_start = .;

+  .ARM.exidx :

+  {

+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+  } >ram

+  __exidx_end = .;

+  .text.align :

+  {

+    . = ALIGN(8);

+    _etext = .;

+  } >ram

+

+  .cs3.rom :

+  {

+    __cs3_region_start_rom = .;

+    *(.cs3.region-head.rom)

+    *(.rom)

+    . = ALIGN (8);

+  } >ram

+

+  .cs3.rom.bss :

+  {

+    *(.rom.b)

+    . = ALIGN (8);

+  } >ram

+  /* __cs3_region_end_rom is deprecated */

+  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(ram);

+  __cs3_region_size_rom = LENGTH(ram);

+  __cs3_region_init_rom = LOADADDR (.cs3.rom);

+  __cs3_region_init_size_rom = SIZEOF(.cs3.rom);

+  __cs3_region_zero_size_rom = SIZEOF(.cs3.rom.bss);

+

+  .data :

+  {

+

+    KEEP(*(.jcr))

+    *(.got.plt) *(.got)

+    *(.shdata)

+    *(.data .data.* .gnu.linkonce.d.*)

+    *(.ram)

+    . = ALIGN (8);

+    _edata = .;

+  } >ram

+  .bss :

+  {

+    *(.shbss)

+    *(.bss .bss.* .gnu.linkonce.b.*)

+    *(COMMON)

+    *(.ram.b)

+    . = ALIGN (8);

+    _end = .;

+    __end = .;

+  } >ram

+  /* __cs3_region_end_ram is deprecated */

+  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);

+  __cs3_region_size_ram = LENGTH(ram);

+  __cs3_region_init_ram = LOADADDR (.text);

+  __cs3_region_init_size_ram = _edata - ADDR (.text);

+  __cs3_region_zero_size_ram = _end - _edata;

+  __cs3_region_num = 1;

+

+  .stab 0 (NOLOAD) : { *(.stab) }

+  .stabstr 0 (NOLOAD) : { *(.stabstr) }

+  /* DWARF debug sections.

+   * Symbols in the DWARF debugging sections are relative to the beginning

+   * of the section so we begin them at 0.  */

+  /* DWARF 1 */

+  .debug          0 : { *(.debug) }

+  .line           0 : { *(.line) }

+  /* GNU DWARF 1 extensions */

+  .debug_srcinfo  0 : { *(.debug_srcinfo) }

+  .debug_sfnames  0 : { *(.debug_sfnames) }

+  /* DWARF 1.1 and DWARF 2 */

+  .debug_aranges  0 : { *(.debug_aranges) }

+  .debug_pubnames 0 : { *(.debug_pubnames) }

+  /* DWARF 2 */

+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }

+  .debug_abbrev   0 : { *(.debug_abbrev) }

+  .debug_line     0 : { *(.debug_line) }

+  .debug_frame    0 : { *(.debug_frame) }

+  .debug_str      0 : { *(.debug_str) }

+  .debug_loc      0 : { *(.debug_loc) }

+  .debug_macinfo  0 : { *(.debug_macinfo) }

+  /* SGI/MIPS DWARF 2 extensions */

+  .debug_weaknames 0 : { *(.debug_weaknames) }

+  .debug_funcnames 0 : { *(.debug_funcnames) }

+  .debug_typenames 0 : { *(.debug_typenames) }

+  .debug_varnames  0 : { *(.debug_varnames) }

+

+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }

+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }

+  /DISCARD/ : { *(.note.GNU-stack) }

+}

+

diff --git a/stm32conf/lanchon-stm32-user-rom.ld b/stm32conf/lanchon-stm32-user-rom.ld
new file mode 100644
index 0000000..e6825e5
--- /dev/null
+++ b/stm32conf/lanchon-stm32-user-rom.ld
@@ -0,0 +1,203 @@
+/* Linker script for STM32 (by Lanchon with Mods by LeafLabs)

+ *

+ * Version:Sourcery G++ 4.2-84

+ * BugURL:https://support.codesourcery.com/GNUToolchain/

+ *

+ *  Copyright 2007 CodeSourcery.

+ *

+ * The authors hereby grant permission to use, copy, modify, distribute,

+ * and license this software and its documentation for any purpose, provided

+ * that existing copyright notices are retained in all copies and that this

+ * notice is included verbatim in any distributions. No written agreement,

+ * license, or royalty fee is required for any of the authorized uses.

+ * Modifications to this software may be copyrighted by their authors

+ * and need not follow the licensing terms described here, provided that

+ * the new terms are clearly indicated on the first page of each file where

+ * they apply. */

+

+/* Linker script for STM32 (by Lanchon),

+ * ROM and RAM relocated to their positions 

+ * as placed by Maple bootloader

+ *

+ * Configure target memory and included script

+ * according to your application requirements. */

+

+/* Define memory spaces. */

+MEMORY

+{

+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K

+  rom (rx) : ORIGIN = 0x08005000, LENGTH = 108K

+}

+

+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

+ENTRY(_start)

+SEARCH_DIR(.)

+/* GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3-lanchon-stm32) */

+GROUP(libgcc.a libc.a libcs3.a libcs3unhosted.a libcs3-lanchon-stm32.a)

+

+/* These force the linker to search for particular symbols from

+ * the start of the link process and thus ensure the user's

+ * overrides are picked up

+ */

+EXTERN(__cs3_reset_lanchon_stm32)

+INCLUDE lanchon-stm32-names.inc

+EXTERN(__cs3_interrupt_vector_lanchon_stm32)

+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)

+EXTERN(_start)

+

+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);

+PROVIDE(__cs3_heap_start = _end);

+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);

+

+SECTIONS

+{

+  .text :

+  {

+    CREATE_OBJECT_SYMBOLS

+    __cs3_region_start_rom = .;

+    *(.cs3.region-head.rom)

+    __cs3_interrupt_vector = __cs3_interrupt_vector_lanchon_stm32;

+    *(.cs3.interrupt_vector)

+    /* Make sure we pulled in an interrupt vector.  */

+    ASSERT (. != __cs3_interrupt_vector_lanchon_stm32, "No interrupt vector");

+    *(.rom)

+    *(.rom.b)

+

+    PROVIDE(__cs3_reset_lanchon_stm32 = _start);

+    __cs3_reset = __cs3_reset_lanchon_stm32;

+    *(.cs3.reset)

+

+    *(.text .text.* .gnu.linkonce.t.*)

+    *(.plt)

+    *(.gnu.warning)

+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)

+

+    *(.rodata .rodata.* .gnu.linkonce.r.*)

+

+    *(.ARM.extab* .gnu.linkonce.armextab.*)

+    *(.gcc_except_table)

+    *(.eh_frame_hdr)

+    *(.eh_frame)

+

+    . = ALIGN(4);

+    KEEP(*(.init))

+

+    . = ALIGN(4);

+    __preinit_array_start = .;

+    KEEP (*(.preinit_array))

+    __preinit_array_end = .;

+

+    . = ALIGN(4);

+    __init_array_start = .;

+    KEEP (*(SORT(.init_array.*)))

+    KEEP (*(.init_array))

+    __init_array_end = .;

+

+    . = ALIGN(0x4);

+    KEEP (*crtbegin.o(.ctors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))

+    KEEP (*(SORT(.ctors.*)))

+    KEEP (*crtend.o(.ctors))

+

+    . = ALIGN(4);

+    KEEP(*(.fini))

+

+    . = ALIGN(4);

+    __fini_array_start = .;

+    KEEP (*(.fini_array))

+    KEEP (*(SORT(.fini_array.*)))

+    __fini_array_end = .;

+

+    KEEP (*crtbegin.o(.dtors))

+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))

+    KEEP (*(SORT(.dtors.*)))

+    KEEP (*crtend.o(.dtors))

+

+    . = ALIGN(4);

+    __cs3_regions = .;

+    LONG (0)

+    LONG (__cs3_region_init_ram)

+    LONG (__cs3_region_start_ram)

+    LONG (__cs3_region_init_size_ram)

+    LONG (__cs3_region_zero_size_ram)

+  } >rom

+

+  /* .ARM.exidx is sorted, so has to go in its own output section.  */

+  __exidx_start = .;

+  .ARM.exidx :

+  {

+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+  } >rom

+  __exidx_end = .;

+  .text.align :

+  {

+    . = ALIGN(8);

+    _etext = .;

+  } >rom

+  /* __cs3_region_end_rom is deprecated */

+  __cs3_region_end_rom = __cs3_region_start_rom + LENGTH(rom);

+  __cs3_region_size_rom = LENGTH(rom);

+  __cs3_region_num = 1;

+

+  .data :

+  {

+    __cs3_region_start_ram = .;

+    *(.cs3.region-head.ram)

+    KEEP(*(.jcr))

+    *(.got.plt) *(.got)

+    *(.shdata)

+    *(.data .data.* .gnu.linkonce.d.*)

+    *(.ram)

+    . = ALIGN (8);

+    _edata = .;

+  } >ram AT>rom

+  .bss :

+  {

+    *(.shbss)

+    *(.bss .bss.* .gnu.linkonce.b.*)

+    *(COMMON)

+    *(.ram.b)

+    . = ALIGN (8);

+    _end = .;

+    __end = .;

+  } >ram AT>rom

+  /* __cs3_region_end_ram is deprecated */

+  __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);

+  __cs3_region_size_ram = LENGTH(ram);

+  __cs3_region_init_ram = LOADADDR (.data);

+  __cs3_region_init_size_ram = _edata - ADDR (.data);

+  __cs3_region_zero_size_ram = _end - _edata;

+  __cs3_region_num = 1;

+

+  .stab 0 (NOLOAD) : { *(.stab) }

+  .stabstr 0 (NOLOAD) : { *(.stabstr) }

+  /* DWARF debug sections.

+   * Symbols in the DWARF debugging sections are relative to the beginning

+   * of the section so we begin them at 0.  */

+  /* DWARF 1 */

+  .debug          0 : { *(.debug) }

+  .line           0 : { *(.line) }

+  /* GNU DWARF 1 extensions */

+  .debug_srcinfo  0 : { *(.debug_srcinfo) }

+  .debug_sfnames  0 : { *(.debug_sfnames) }

+  /* DWARF 1.1 and DWARF 2 */

+  .debug_aranges  0 : { *(.debug_aranges) }

+  .debug_pubnames 0 : { *(.debug_pubnames) }

+  /* DWARF 2 */

+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }

+  .debug_abbrev   0 : { *(.debug_abbrev) }

+  .debug_line     0 : { *(.debug_line) }

+  .debug_frame    0 : { *(.debug_frame) }

+  .debug_str      0 : { *(.debug_str) }

+  .debug_loc      0 : { *(.debug_loc) }

+  .debug_macinfo  0 : { *(.debug_macinfo) }

+  /* SGI/MIPS DWARF 2 extensions */

+  .debug_weaknames 0 : { *(.debug_weaknames) }

+  .debug_funcnames 0 : { *(.debug_funcnames) }

+  .debug_typenames 0 : { *(.debug_typenames) }

+  .debug_varnames  0 : { *(.debug_varnames) }

+

+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }

+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }

+  /DISCARD/ : { *(.note.GNU-stack) }

+}

diff --git a/stm32conf/lanchon-stm32-user.ld b/stm32conf/lanchon-stm32-user.ld
new file mode 100644
index 0000000..32866a2
--- /dev/null
+++ b/stm32conf/lanchon-stm32-user.ld
@@ -0,0 +1,22 @@
+/* Linker script for STM32 (by Lanchon),

+ * ROM and RAM relocated to their positions 

+ * as placed by Maple bootloader

+ *

+ * Configure target memory and included script

+ * according to your application requirements. */

+

+/* Define memory spaces. */

+MEMORY

+{

+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K

+  rom (rx) : ORIGIN = 0x08005000, LENGTH = 108K

+}

+

+/* Include the appropriate script.

+ * Options:

+ *   lanchon-stm32-rom.ld

+ *   lanchon-stm32-rom-hosted.ld

+ *   lanchon-stm32-ram.ld

+ *   lanchon-stm32-ram-hosted.ld

+ */

+INCLUDE "lanchon-stm32-ram.ld"

diff --git a/stm32conf/lanchon-stm32/libcs3-lanchon-stm32.a b/stm32conf/lanchon-stm32/libcs3-lanchon-stm32.a
new file mode 100644
index 0000000..12a2c6e
--- /dev/null
+++ b/stm32conf/lanchon-stm32/libcs3-lanchon-stm32.a
diff --git a/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-isrs.S b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-isrs.S
index b68af59..cda2d73 100644
--- a/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-isrs.S
+++ b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-isrs.S
@@ -114,9 +114,9 @@ __STM32DefaultExceptionHandler:
 	.weak	USB_HP_CAN_TX_IRQHandler

 	.globl	USB_HP_CAN_TX_IRQHandler

 	.set	USB_HP_CAN_TX_IRQHandler, __STM32DefaultExceptionHandler

-	.weak	USB_LP_CAN_RX0_IRQHandler

-	.globl	USB_LP_CAN_RX0_IRQHandler

-	.set	USB_LP_CAN_RX0_IRQHandler, __STM32DefaultExceptionHandler

+	.weak	usb_lpIRQHandler

+	.globl	usb_lpIRQHandler

+	.set	usb_lpIRQHandler, __STM32DefaultExceptionHandler

 	.weak	CAN_RX1_IRQHandler

 	.globl	CAN_RX1_IRQHandler

 	.set	CAN_RX1_IRQHandler, __STM32DefaultExceptionHandler

diff --git a/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-vector.S b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-vector.S
index 17a9c01..a8e1d68 100644
--- a/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-vector.S
+++ b/stm32conf/lanchon-stm32/src/libcs3-lanchon-stm32/lanchon-stm32-vector.S
@@ -42,7 +42,7 @@ __cs3_interrupt_vector_lanchon_stm32:
 	.long	DMAChannel7_IRQHandler

 	.long	ADC_IRQHandler

 	.long	USB_HP_CAN_TX_IRQHandler

-	.long	USB_LP_CAN_RX0_IRQHandler

+	.long	usb_lpIRQHandler

 	.long	CAN_RX1_IRQHandler

 	.long	CAN_SCE_IRQHandler

 	.long	EXTI9_5_IRQHandler