diff options
author | Perry Hung <iperry@alum.mit.edu> | 2010-08-04 04:29:02 -0400 |
---|---|---|
committer | Perry Hung <iperry@alum.mit.edu> | 2010-08-04 04:29:02 -0400 |
commit | 57df5396fe83d0bb7aa55a9f4cd3a9eb2e4a6116 (patch) | |
tree | 0c01fa11eac9b0b57f11b443e279cd14acbd87a4 | |
parent | 2bb8c3fbe39ad12bc4669d499228961ad25e0ace (diff) | |
download | librambutan-57df5396fe83d0bb7aa55a9f4cd3a9eb2e4a6116.tar.gz librambutan-57df5396fe83d0bb7aa55a9f4cd3a9eb2e4a6116.zip |
New reset and clock control api
-rw-r--r-- | libmaple/adc.c | 6 | ||||
-rw-r--r-- | libmaple/gpio.c | 10 | ||||
-rw-r--r-- | libmaple/rcc.c | 235 | ||||
-rw-r--r-- | libmaple/rcc.h | 193 | ||||
-rw-r--r-- | libmaple/timers.c | 8 | ||||
-rw-r--r-- | libmaple/usart.c | 6 | ||||
-rw-r--r-- | wirish/wirish.c | 17 |
7 files changed, 273 insertions, 202 deletions
diff --git a/libmaple/adc.c b/libmaple/adc.c index 317a5ff..021758c 100644 --- a/libmaple/adc.c +++ b/libmaple/adc.c @@ -63,9 +63,9 @@ * At 55.5 cycles/sample, the external input impedance < 50kOhms*/ void adc_init(void) { - rcc_set_adc_prescaler(PCLK2_DIV_2); - rcc_enable_clk_adc1(); - rcc_reset_adc1(); + rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6); + rcc_clk_enable(RCC_ADC1); + rcc_reset_dev(RCC_ADC1); ADC_CR1 = 0; ADC_CR2 = CR2_EXTSEL_SWSTART | CR2_EXTTRIG; // Software triggers conversions diff --git a/libmaple/gpio.c b/libmaple/gpio.c index 9334c1e..3e05bd0 100644 --- a/libmaple/gpio.c +++ b/libmaple/gpio.c @@ -33,11 +33,11 @@ #include "gpio.h" void gpio_init(void) { - rcc_enable_clk_gpioa(); - rcc_enable_clk_gpiob(); - rcc_enable_clk_gpioc(); - rcc_enable_clk_gpiod(); - rcc_enable_clk_afio(); + rcc_clk_enable(RCC_GPIOA); + rcc_clk_enable(RCC_GPIOB); + rcc_clk_enable(RCC_GPIOC); + rcc_clk_enable(RCC_GPIOD); + rcc_clk_enable(RCC_AFIO); } void gpio_set_mode(GPIO_Port* port, uint8 gpio_pin, GPIOPinMode mode) { diff --git a/libmaple/rcc.c b/libmaple/rcc.c index bb423b9..4f13b0d 100644 --- a/libmaple/rcc.c +++ b/libmaple/rcc.c @@ -23,107 +23,176 @@ * ****************************************************************************/ /** - * @file rcc.c - * - * @brief Implements pretty much only the basic clock setup on the maple, - * exposes a handful of clock enable/disable and peripheral reset commands. + * @brief Implements pretty much only the basic clock setup on the stm32, + * clock enable/disable and peripheral reset commands. */ #include "libmaple.h" #include "flash.h" #include "rcc.h" -static void set_ahb_prescaler(uint32 divider) { - uint32 cfgr = __read(RCC_CFGR); - - cfgr &= ~HPRE; - - switch (divider) { - case SYSCLK_DIV_1: - cfgr |= SYSCLK_DIV_1; - break; - default: - ASSERT(0); - } +/* registers */ +#define RCC_BASE 0x40021000 +#define RCC_CR (RCC_BASE + 0x0) +#define RCC_CFGR (RCC_BASE + 0x4) +#define RCC_CIR (RCC_BASE + 0x8) +#define RCC_APB2RSTR (RCC_BASE + 0xC) +#define RCC_APB1RSTR (RCC_BASE + 0x10) +#define RCC_AHBENR (RCC_BASE + 0x14) +#define RCC_APB2ENR (RCC_BASE + 0x18) +#define RCC_APB1ENR (RCC_BASE + 0x1C) +#define RCC_BDCR (RCC_BASE + 0x20) +#define RCC_CSR (RCC_BASE + 0x24) +#define RCC_AHBSTR (RCC_BASE + 0x28) +#define RCC_CFGR2 (RCC_BASE + 0x2C) + +#define RCC_CFGR_USBPRE (0x1 << 22) +#define RCC_CFGR_ADCPRE (0x3 << 14) +#define RCC_CFGR_PPRE1 (0x7 << 8) +#define RCC_CFGR_PPRE2 (0x7 << 11) +#define RCC_CFGR_HPRE (0xF << 4) +#define RCC_CFGR_PLLSRC (0x1 << 16) + +#define RCC_CFGR_SWS (0x3 << 2) +#define RCC_CFGR_SWS_PLL (0x2 << 2) +#define RCC_CFGR_SWS_HSE (0x1 << 2) + +#define RCC_CFGR_SW (0x3 << 0) +#define RCC_CFGR_SW_PLL (0x2 << 0) +#define RCC_CFGR_SW_HSE (0x1 << 0) + +/* CR status bits */ +#define RCC_CR_HSEON (0x1 << 16) +#define RCC_CR_HSERDY (0x1 << 17) +#define RCC_CR_PLLON (0x1 << 24) +#define RCC_CR_PLLRDY (0x1 << 25) + +#define RCC_WRITE_CFGR(val) __write(RCC_CFGR, val) +#define RCC_READ_CFGR() __read(RCC_CFGR) + +#define RCC_WRITE_CR(val) __write(RCC_CR, val) +#define RCC_READ_CR() __read(RCC_CR) + +enum { + APB1, + APB2, + AHB +}; + +struct rcc_dev_info { + const uint8 clk_domain; + const uint8 line_num; +}; + +/* device descriptor tables */ +static const struct rcc_dev_info rcc_dev_table[] = { + [RCC_GPIOA] = { .clk_domain = APB2, .line_num = 2 }, + [RCC_GPIOB] = { .clk_domain = APB2, .line_num = 3 }, + [RCC_GPIOC] = { .clk_domain = APB2, .line_num = 4 }, + [RCC_GPIOD] = { .clk_domain = APB2, .line_num = 5 }, + [RCC_AFIO] = { .clk_domain = APB2, .line_num = 0 }, + [RCC_ADC1] = { .clk_domain = APB2, .line_num = 9 }, + [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 }, + [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 }, + [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 }, + [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 }, + [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 }, + [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 }, + [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 }, +}; - __write(RCC_CFGR, cfgr); +/** + * @brief Initialize the clock control system. Initializes the system + * clock source to use the PLL driven by an external oscillator + * @param sysclk_src system clock source, must be PLL + * @param pll_src pll clock source, must be HSE + * @param pll_mul pll multiplier + */ +void rcc_clk_init(uint32 sysclk_src, uint32 pll_src, uint32 pll_mul) { + /* Assume that we're going to clock the chip off the PLL, fed by + * the HSE */ + ASSERT(sysclk_src == RCC_CLKSRC_PLL && + pll_src == RCC_PLLSRC_HSE); + + uint32 cfgr = 0; + uint32 cr = RCC_READ_CR(); + + cfgr = (pll_src | pll_mul); + RCC_WRITE_CFGR(cfgr); + + /* Turn on the HSE */ + cr |= RCC_CR_HSEON; + RCC_WRITE_CR(cr); + while (!(RCC_READ_CR() & RCC_CR_HSERDY)) + ; + + /* Now the PLL */ + cr |= RCC_CR_PLLON; + RCC_WRITE_CR(cr); + while (!(RCC_READ_CR() & RCC_CR_PLLRDY)) + ; + + /* Finally, let's switch over to the PLL */ + cfgr &= ~RCC_CFGR_SW; + cfgr |= RCC_CFGR_SW_PLL; + RCC_WRITE_CFGR(cfgr); + while ((RCC_READ_CFGR() & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) + ; } -static void set_apb1_prescaler(uint32 divider) { - uint32 cfgr = __read(RCC_CFGR); - cfgr &= ~PPRE1; - switch (divider) { - case HCLK_DIV_2: - cfgr |= HCLK_DIV_2; - break; - default: - ASSERT(0); - } - - __write(RCC_CFGR, cfgr); -} - -static void set_apb2_prescaler(uint32 divider) { - uint32 cfgr = __read(RCC_CFGR); - - cfgr &= ~PPRE2; +/** + * @brief Turn on the clock line on a device + * @param dev_num device to turn on + */ +void rcc_clk_enable(uint32 dev_num) { + static const uint32 enable_regs[] = { + [APB1] = RCC_APB1ENR, + [APB2] = RCC_APB2ENR, + [AHB] = RCC_AHBENR, + }; - switch (divider) { - case HCLK_DIV_1: - cfgr |= HCLK_DIV_1; - break; - default: - ASSERT(0); - } + uint8 clk_domain = rcc_dev_table[dev_num].clk_domain; - __write(RCC_CFGR, cfgr); + __set_bits(enable_regs[clk_domain], BIT(rcc_dev_table[dev_num].line_num)); } -/* FIXME: magic numbers */ -static void pll_init(void) { - uint32 cfgr; - cfgr = __read(RCC_CFGR); - cfgr &= (~PLLMUL | PLL_INPUT_CLK_HSE); - - /* pll multiplier 9, input clock hse */ - __write(RCC_CFGR, cfgr | PLL_MUL_9 | PLL_INPUT_CLK_HSE); - - /* enable pll */ - __set_bits(RCC_CR, PLLON); - while(!__get_bits(RCC_CR, PLLRDY)) { - asm volatile("nop"); - } - - /* select pll for system clock source */ - cfgr = __read(RCC_CFGR); - cfgr &= ~RCC_CFGR_SW; - __write(RCC_CFGR, cfgr | RCC_CFGR_SW_PLL); - - while (__get_bits(RCC_CFGR, 0x00000008) != 0x8) { - asm volatile("nop"); - } +/** + * @brief Set the divider on a device prescaler + * @param prescaler prescaler to set + * @param divider prescaler divider + */ +void rcc_set_prescaler(uint32 prescaler, uint32 divider) { + static const uint32 masks[] = { + [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE, + [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1, + [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2, + [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE, + [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE, + }; + + uint32 cfgr = RCC_READ_CFGR(); + + cfgr &= ~masks[prescaler]; + cfgr |= divider; + RCC_WRITE_CFGR(cfgr); } -static void hse_init(void) { - __set_bits(RCC_CR, HSEON); - while (!HSERDY) { - asm volatile("nop"); - } -} -void rcc_init(void) { - hse_init(); - set_ahb_prescaler(SYSCLK_DIV_1); - set_apb1_prescaler(HCLK_DIV_2); - set_apb2_prescaler(HCLK_DIV_1); - pll_init(); -} +/** + * @brief reset a device + * @param dev_num device to reset + */ +void rcc_reset_dev(uint32 dev_num) { + static const uint32 reset_regs[] = { + [APB1] = RCC_APB1RSTR, + [APB2] = RCC_APB2RSTR, + }; + + uint8 clk_domain = rcc_dev_table[dev_num].clk_domain; -void rcc_set_adc_prescaler(uint32 divider) { - uint32 cfgr = __read(RCC_CFGR); - cfgr &= ~ADCPRE; - __write(RCC_CFGR, cfgr | PCLK2_DIV_2); + __set_bits(reset_regs[clk_domain], BIT(rcc_dev_table[dev_num].line_num)); + __clear_bits(reset_regs[clk_domain], BIT(rcc_dev_table[dev_num].line_num)); } diff --git a/libmaple/rcc.h b/libmaple/rcc.h index cb3c543..1bc63e6 100644 --- a/libmaple/rcc.h +++ b/libmaple/rcc.h @@ -23,112 +23,103 @@ * ****************************************************************************/ /** - * @file rcc.h - * - * @brief + * @brief reset and clock control definitions and prototypes */ #ifndef _RCC_H_ #define _RCC_H_ -#define RCC_BASE 0x40021000 -#define RCC_CR (RCC_BASE + 0x0) -#define RCC_CFGR (RCC_BASE + 0x4) -#define RCC_CIR (RCC_BASE + 0x8) -#define RCC_APB2RSTR (RCC_BASE + 0xC) -#define RCC_APB1RSTR (RCC_BASE + 0x10) -#define RCC_AHBENR (RCC_BASE + 0x14) -#define RCC_APB2ENR (RCC_BASE + 0x18) -#define RCC_APB1ENR (RCC_BASE + 0x1C) -#define RCC_BDCR (RCC_BASE + 0x20) -#define RCC_CSR (RCC_BASE + 0x24) -#define RCC_AHBSTR (RCC_BASE + 0x28) -#define RCC_CFGR2 (RCC_BASE + 0x2C)) - -#define HSEON BIT(16) -#define HSERDY *(volatile uint32*)(BITBAND_PERI(RCC_CR + 2, 0)) - -#define ADCPRE 0x0000C000 -#define HPRE 0x000000F0 -#define PPRE2 0x00003800 // apb2 high speed prescaler -#define PPRE1 0x00000700 // apb1 low-speed prescaler - -#define PLLMUL 0x002C0000 -#define PLL_MUL_9 0x001C0000 -#define PLLSRC BIT(16) -#define SYSCLK_DIV_1 (0x0 << 4) -#define HCLK_DIV_1 0 -#define HCLK_DIV_2 0x00000400 -#define PCLK2_DIV_2 0x00008000 - -#define PLLRDY BIT(25) -#define PLLON BIT(24) -#define PLL_INPUT_CLK_HSE BIT(16) - -#define RCC_CFGR_SW 0x00000003 -#define RCC_CFGR_SW_PLL 0x00000002 - -/* APB2 reset bits */ -#define RCC_APB2RSTR_USART1RST BIT(14) -#define RCC_APB2RSTR_SPI1RST BIT(12) -#define RCC_APB2RSTR_TIM1RST BIT(11) -#define RCC_APB2RSTR_ADC2RST BIT(10) -#define RCC_APB2RSTR_ADC1RST BIT(9) -#define RCC_APB2RSTR_IOERST BIT(6) -#define RCC_APB2RSTR_IODRST BIT(5) -#define RCC_APB2RSTR_IOCRST BIT(4) -#define RCC_APB2RSTR_IOBRST BIT(3) -#define RCC_APB2RSTR_IOARST BIT(2) -#define RCC_APB2RSTR_AFIORST BIT(0) - -/* APB2 peripheral clock enable bits */ -#define RCC_APB2ENR_USART1EN BIT(14) -#define RCC_APB2ENR_SPI1EN BIT(12) -#define RCC_APB2ENR_TIM1EN BIT(11) -#define RCC_APB2ENR_ADC2EN BIT(10) -#define RCC_APB2ENR_ADC1EN BIT(9) -#define RCC_APB2ENR_IOEEN BIT(6) -#define RCC_APB2ENR_IODEN BIT(5) -#define RCC_APB2ENR_IOCEN BIT(4) -#define RCC_APB2ENR_IOBEN BIT(3) -#define RCC_APB2ENR_IOAEN BIT(2) -#define RCC_APB2ENR_AFIOEN BIT(0) - -/* APB1 peripheral clock enable bits */ -#define RCC_APB1ENR_TIM2EN BIT(0) -#define RCC_APB1ENR_TIM3EN BIT(1) -#define RCC_APB1ENR_TIM4EN BIT(2) -#define RCC_APB1ENR_USART2EN BIT(17) -#define RCC_APB1ENR_USART3EN BIT(18) -#define RCC_APB1ENR_SPI2EN BIT(14) - -#define rcc_enable_clk_spi1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_SPI1EN) -#define rcc_enable_clk_spi2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_SPI2EN) - -#define rcc_enable_clk_timer1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_TIM1EN) -#define rcc_enable_clk_timer2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM2EN) -#define rcc_enable_clk_timer3() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM3EN) -#define rcc_enable_clk_timer4() __set_bits(RCC_APB1ENR, RCC_APB1ENR_TIM4EN) - -#define rcc_enable_clk_gpioa() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOAEN) -#define rcc_enable_clk_gpiob() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOBEN) -#define rcc_enable_clk_gpioc() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IOCEN) -#define rcc_enable_clk_gpiod() __set_bits(RCC_APB2ENR, RCC_APB2ENR_IODEN) -#define rcc_enable_clk_afio() __set_bits(RCC_APB2ENR, RCC_APB2ENR_AFIOEN) - -#define rcc_enable_clk_usart1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_USART1EN) -#define rcc_enable_clk_usart2() __set_bits(RCC_APB1ENR, RCC_APB1ENR_USART2EN) -#define rcc_enable_clk_usart3() __set_bits(RCC_APB1ENR, RCC_APB1ENR_USART3EN) - -#define rcc_enable_clk_adc1() __set_bits(RCC_APB2ENR, RCC_APB2ENR_ADC1EN) - -#define rcc_reset_adc1() { __set_bits(RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); \ - __clear_bits(RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); \ - } - - -void rcc_init(void); -void rcc_set_adc_prescaler(uint32 divider); +/* sysclk source */ +#define RCC_CLKSRC_HSI (0x0) +#define RCC_CLKSRC_HSE (0x1) +#define RCC_CLKSRC_PLL (0x2) + +/* pll entry clock source */ +#define RCC_PLLSRC_HSE (0x1 << 16) +#define RCC_PLLSRC_HSI_DIV_2 (0x0 << 16) + +/* adc prescaler dividers */ +#define RCC_ADCPRE_PCLK_DIV_2 (0x0 << 14) +#define RCC_ADCPRE_PCLK_DIV_4 (0x1 << 14) +#define RCC_ADCPRE_PCLK_DIV_6 (0x2 << 14) +#define RCC_ADCPRE_PCLK_DIV_8 (0x3 << 14) + +/* apb1 prescaler dividers */ +#define RCC_APB1_HCLK_DIV_1 (0x0 << 8) +#define RCC_APB1_HCLK_DIV_2 (0x4 << 8) +#define RCC_APB1_HCLK_DIV_4 (0x5 << 8) +#define RCC_APB1_HCLK_DIV_8 (0x6 << 8) +#define RCC_APB1_HCLK_DIV_16 (0x7 << 8) + +/* apb2 prescaler dividers */ +#define RCC_APB2_HCLK_DIV_1 (0x0 << 11) +#define RCC_APB2_HCLK_DIV_2 (0x4 << 11) +#define RCC_APB2_HCLK_DIV_4 (0x5 << 11) +#define RCC_APB2_HCLK_DIV_8 (0x6 << 11) +#define RCC_APB2_HCLK_DIV_16 (0x7 << 11) + +/* ahb prescaler dividers */ +#define RCC_AHB_SYSCLK_DIV_1 (0x0 << 4) +#define RCC_AHB_SYSCLK_DIV_2 (0x8 << 4) +#define RCC_AHB_SYSCLK_DIV_4 (0x9 << 4) +#define RCC_AHB_SYSCLK_DIV_8 (0xA << 4) +#define RCC_AHB_SYSCLK_DIV_16 (0xB << 4) +#define RCC_AHB_SYSCLK_DIV_32 (0xC << 4) +#define RCC_AHB_SYSCLK_DIV_64 (0xD << 4) +#define RCC_AHB_SYSCLK_DIV_128 (0xD << 4) +#define RCC_AHB_SYSCLK_DIV_256 (0xE << 4) +#define RCC_AHB_SYSCLK_DIV_512 (0xF << 4) + +/* pll multipliers */ +#define RCC_PLLMUL_2 (0x0 << 18) +#define RCC_PLLMUL_3 (0x1 << 18) +#define RCC_PLLMUL_4 (0x2 << 18) +#define RCC_PLLMUL_5 (0x3 << 18) +#define RCC_PLLMUL_6 (0x4 << 18) +#define RCC_PLLMUL_7 (0x5 << 18) +#define RCC_PLLMUL_8 (0x6 << 18) +#define RCC_PLLMUL_9 (0x7 << 18) +#define RCC_PLLMUL_10 (0x8 << 18) +#define RCC_PLLMUL_11 (0x9 << 18) +#define RCC_PLLMUL_12 (0xA << 18) +#define RCC_PLLMUL_13 (0xB << 18) +#define RCC_PLLMUL_14 (0xC << 18) +#define RCC_PLLMUL_15 (0xD << 18) +#define RCC_PLLMUL_16 (0xE << 18) + +/* device numbers */ +enum { + RCC_GPIOA, + RCC_GPIOB, + RCC_GPIOC, + RCC_GPIOD, + RCC_AFIO, + RCC_ADC1, + RCC_USART1, + RCC_USART2, + RCC_USART3, + RCC_USART4, + RCC_USART5, + RCC_TIMER1, + RCC_TIMER2, + RCC_TIMER3, + RCC_TIMER4, +}; + +/* prescalers */ +enum { + RCC_PRESCALER_AHB, + RCC_PRESCALER_APB1, + RCC_PRESCALER_APB2, + RCC_PRESCALER_USB, + RCC_PRESCALER_ADC +}; + + +void rcc_clk_init(uint32 sysclk_src, uint32 pll_src, uint32 pll_mul); +void rcc_clk_enable(uint32 dev); +void rcc_reset_dev(uint32 dev); +void rcc_set_prescaler(uint32 prescaler, uint32 divider); #endif diff --git a/libmaple/timers.c b/libmaple/timers.c index da85680..a3890d4 100644 --- a/libmaple/timers.c +++ b/libmaple/timers.c @@ -94,20 +94,20 @@ void timer_init(uint8 timer_num, uint16 prescale) { switch(timer_num) { case 1: timer = (Timer*)TIMER1_BASE; - rcc_enable_clk_timer1(); + rcc_clk_enable(RCC_TIMER1); is_advanced = 1; break; case 2: timer = (Timer*)TIMER2_BASE; - rcc_enable_clk_timer2(); + rcc_clk_enable(RCC_TIMER2); break; case 3: timer = (Timer*)TIMER3_BASE; - rcc_enable_clk_timer3(); + rcc_clk_enable(RCC_TIMER3); break; case 4: timer = (Timer*)TIMER4_BASE; - rcc_enable_clk_timer4(); + rcc_clk_enable(RCC_TIMER4); break; } diff --git a/libmaple/usart.c b/libmaple/usart.c index 282fc5d..2a587f3 100644 --- a/libmaple/usart.c +++ b/libmaple/usart.c @@ -128,21 +128,21 @@ void usart_init(uint8 usart_num, uint32 baud) { port = (usart_port*)USART1_BASE; ring_buf = &ring_buf1; clk_speed = USART1_CLK; - rcc_enable_clk_usart1(); + rcc_clk_enable(RCC_USART1); REG_SET(NVIC_ISER1, BIT(5)); break; case 2: port = (usart_port*)USART2_BASE; ring_buf = &ring_buf2; clk_speed = USART2_CLK; - rcc_enable_clk_usart2(); + rcc_clk_enable(RCC_USART2); REG_SET(NVIC_ISER1, BIT(6)); break; case 3: port = (usart_port*)USART3_BASE; ring_buf = &ring_buf3; clk_speed = USART3_CLK; - rcc_enable_clk_usart3(); + rcc_clk_enable(RCC_USART3); REG_SET(NVIC_ISER1, BIT(7)); break; default: diff --git a/wirish/wirish.c b/wirish/wirish.c index e166455..1938ec9 100644 --- a/wirish/wirish.c +++ b/wirish/wirish.c @@ -23,15 +23,22 @@ * ****************************************************************************/ /** - * @brief Maple board bring up + * @brief generic maple board bring up: + * + * By default, we bring up all maple boards running on the stm32 to 72mhz, + * clocked off the PLL, driven by the 8MHz external crystal. + * + * AHB and APB2 are clocked at 72MHz + * APB1 is clocked at 36MHz + * */ #include "wirish.h" -#include "rcc.h" #include "systick.h" #include "gpio.h" #include "nvic.h" #include "usb.h" +#include "rcc.h" #include "flash.h" void init(void) { @@ -39,7 +46,11 @@ void init(void) { flash_enable_prefetch(); flash_set_latency(FLASH_WAIT_STATE_2); - rcc_init(); + /* initialize clocks */ + rcc_clk_init(RCC_CLKSRC_PLL, RCC_PLLSRC_HSE, RCC_PLLMUL_9); + rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1); + rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2); + rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1); nvic_init(); systick_init(); |