aboutsummaryrefslogtreecommitdiffstats
path: root/synth_project
diff options
context:
space:
mode:
Diffstat (limited to 'synth_project')
-rwxr-xr-xsynth_project/make.sh9
-rwxr-xr-xsynth_project/project.lso1
-rw-r--r--synth_project/project.prj1
-rw-r--r--synth_project/project.srp32
-rwxr-xr-xsynth_project/project.ucf21
-rw-r--r--synth_project/project.xst53
6 files changed, 117 insertions, 0 deletions
diff --git a/synth_project/make.sh b/synth_project/make.sh
new file mode 100755
index 0000000..174a6ac
--- /dev/null
+++ b/synth_project/make.sh
@@ -0,0 +1,9 @@
+#!/bin/sh -e
+
+TOP_NAME=project
+xst -ifn $TOP_NAME.xst
+ngdbuild $TOP_NAME.ngc -verbose
+map -pr b -w -detail $TOP_NAME.ngd
+par -w $TOP_NAME $TOP_NAME.ncd
+bitgen -w $TOP_NAME.ncd
+
diff --git a/synth_project/project.lso b/synth_project/project.lso
new file mode 100755
index 0000000..a340c10
--- /dev/null
+++ b/synth_project/project.lso
@@ -0,0 +1 @@
+work \ No newline at end of file
diff --git a/synth_project/project.prj b/synth_project/project.prj
new file mode 100644
index 0000000..3262aa0
--- /dev/null
+++ b/synth_project/project.prj
@@ -0,0 +1 @@
+ verilog work ../hdl/project.v
diff --git a/synth_project/project.srp b/synth_project/project.srp
new file mode 100644
index 0000000..3a35165
--- /dev/null
+++ b/synth_project/project.srp
@@ -0,0 +1,32 @@
+Release 14.3 - xst P.40xd (lin64)
+Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+-->
+Parameter TMPDIR set to ./xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.06 secs
+
+-->
+Parameter xsthdpdir set to ./xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.06 secs
+
+-->
+ERROR:Xst:438 - Can not open file : proejct.prj
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.08 secs
+
+-->
+
+
+Total memory usage is 284024 kilobytes
+
+Number of errors : 1 ( 0 filtered)
+Number of warnings : 0 ( 0 filtered)
+Number of infos : 0 ( 0 filtered)
+
diff --git a/synth_project/project.ucf b/synth_project/project.ucf
new file mode 100755
index 0000000..322c05a
--- /dev/null
+++ b/synth_project/project.ucf
@@ -0,0 +1,21 @@
+NET "PUSH_BUTTON_RESET_RAW" LOC = F3;
+
+#100MHz clock
+NET "SYSTEMCLOCK" LOC = K21;
+
+NET "Switch_input_0" LOC = C18;
+NET "Switch_input_1" LOC = Y6;
+NET "Switch_input_2" LOC = W6;
+NET "Switch_input_3" LOC = E4;
+
+NET "LED_output_1" LOC = D17;
+NET "LED_output_2" LOC = AB4;
+NET "LED_output_4" LOC = D21;
+NET "LED_output_5" LOC = W15;
+
+# Defines the external differential clock to be 150 MHz with 50% duty
+# cycle.
+
+NET "SYSTEMCLOCK" TNM_NET = "SYSTEMCLOCK";
+TIMESPEC TS__SYSTEMCLOCK = PERIOD "SYSTEMCLOCK" 5 ns HIGH 50 % PRIORITY 2;
+
diff --git a/synth_project/project.xst b/synth_project/project.xst
new file mode 100644
index 0000000..9a29456
--- /dev/null
+++ b/synth_project/project.xst
@@ -0,0 +1,53 @@
+set -tmpdir "./xst/projnav.tmp"
+set -xsthdpdir "./xst"
+run
+-ifn project.prj
+-ifmt mixed
+-ofn project
+-ofmt NGC
+-p xc6slx45t-3-fgg484
+-top project
+-lso project.lso
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-netlist_hierarchy rebuilt
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints YES
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc auto
+-reduce_control_sets auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 auto
+# use NO for making NGC's and YES for making bitstreams
+-iobuf YES
+-max_fanout 100000
+-bufg 32
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5 \ No newline at end of file