diff options
| -rw-r--r-- | hdl/project.v | 26 | ||||
| -rwxr-xr-x | synth_project/make.sh | 9 | ||||
| -rwxr-xr-x | synth_project/project.lso | 1 | ||||
| -rw-r--r-- | synth_project/project.prj | 1 | ||||
| -rw-r--r-- | synth_project/project.srp | 32 | ||||
| -rwxr-xr-x | synth_project/project.ucf | 21 | ||||
| -rw-r--r-- | synth_project/project.xst | 53 | ||||
| -rwxr-xr-x | testbench/fuse.sh | 2 | ||||
| -rw-r--r-- | testbench/signals.wcfg | 42 | ||||
| -rwxr-xr-x | testbench/simulate_isim.exe | bin | 0 -> 21792 bytes | |||
| -rw-r--r-- | testbench/simulate_isim.prj | 3 | ||||
| -rwxr-xr-x | testbench/tb.v | 45 |
12 files changed, 235 insertions, 0 deletions
diff --git a/hdl/project.v b/hdl/project.v new file mode 100644 index 0000000..753597b --- /dev/null +++ b/hdl/project.v @@ -0,0 +1,26 @@ +module project + ( + output wire LED_output_0, + output wire LED_output_1, + output wire LED_output_2, + output wire LED_output_3, + output wire LED_output_4, + output wire LED_output_5, + output wire LED_output_6, + input wire Switch_input_0, + input wire Switch_input_1, + input wire Switch_input_2, + input wire Switch_input_3, + input wire SYSTEMCLOCK, + input wire PUSH_BUTTON_RESET_RAW //Xilinx GTP - this is active low- + ); + + assign LED_output_0 = 1'b0; + assign LED_output_1 = 1'b0; + assign LED_output_2 = 1'b0; + assign LED_output_3 = 1'b0; + assign LED_output_4 = 1'b0; + assign LED_output_5 = 1'b0; + assign LED_output_6 = 1'b0; + +endmodule
\ No newline at end of file diff --git a/synth_project/make.sh b/synth_project/make.sh new file mode 100755 index 0000000..174a6ac --- /dev/null +++ b/synth_project/make.sh @@ -0,0 +1,9 @@ +#!/bin/sh -e + +TOP_NAME=project +xst -ifn $TOP_NAME.xst +ngdbuild $TOP_NAME.ngc -verbose +map -pr b -w -detail $TOP_NAME.ngd +par -w $TOP_NAME $TOP_NAME.ncd +bitgen -w $TOP_NAME.ncd + diff --git a/synth_project/project.lso b/synth_project/project.lso new file mode 100755 index 0000000..a340c10 --- /dev/null +++ b/synth_project/project.lso @@ -0,0 +1 @@ +work
\ No newline at end of file diff --git a/synth_project/project.prj b/synth_project/project.prj new file mode 100644 index 0000000..3262aa0 --- /dev/null +++ b/synth_project/project.prj @@ -0,0 +1 @@ + verilog work ../hdl/project.v diff --git a/synth_project/project.srp b/synth_project/project.srp new file mode 100644 index 0000000..3a35165 --- /dev/null +++ b/synth_project/project.srp @@ -0,0 +1,32 @@ +Release 14.3 - xst P.40xd (lin64) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to ./xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.06 secs + +--> +Parameter xsthdpdir set to ./xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.06 secs + +--> +ERROR:Xst:438 - Can not open file : proejct.prj + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.08 secs + +--> + + +Total memory usage is 284024 kilobytes + +Number of errors : 1 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/synth_project/project.ucf b/synth_project/project.ucf new file mode 100755 index 0000000..322c05a --- /dev/null +++ b/synth_project/project.ucf @@ -0,0 +1,21 @@ +NET "PUSH_BUTTON_RESET_RAW" LOC = F3; + +#100MHz clock +NET "SYSTEMCLOCK" LOC = K21; + +NET "Switch_input_0" LOC = C18; +NET "Switch_input_1" LOC = Y6; +NET "Switch_input_2" LOC = W6; +NET "Switch_input_3" LOC = E4; + +NET "LED_output_1" LOC = D17; +NET "LED_output_2" LOC = AB4; +NET "LED_output_4" LOC = D21; +NET "LED_output_5" LOC = W15; + +# Defines the external differential clock to be 150 MHz with 50% duty +# cycle. + +NET "SYSTEMCLOCK" TNM_NET = "SYSTEMCLOCK"; +TIMESPEC TS__SYSTEMCLOCK = PERIOD "SYSTEMCLOCK" 5 ns HIGH 50 % PRIORITY 2; + diff --git a/synth_project/project.xst b/synth_project/project.xst new file mode 100644 index 0000000..9a29456 --- /dev/null +++ b/synth_project/project.xst @@ -0,0 +1,53 @@ +set -tmpdir "./xst/projnav.tmp" +set -xsthdpdir "./xst" +run +-ifn project.prj +-ifmt mixed +-ofn project +-ofmt NGC +-p xc6slx45t-3-fgg484 +-top project +-lso project.lso +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-netlist_hierarchy rebuilt +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints YES +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc auto +-reduce_control_sets auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-use_dsp48 auto +# use NO for making NGC's and YES for making bitstreams +-iobuf YES +-max_fanout 100000 +-bufg 32 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5
\ No newline at end of file diff --git a/testbench/fuse.sh b/testbench/fuse.sh new file mode 100755 index 0000000..ad08c93 --- /dev/null +++ b/testbench/fuse.sh @@ -0,0 +1,2 @@ +vlogcomp -prj simulate_isim.prj +fuse -lib unisims_ver -lib secureip -lib xilinxcorelib_ver -lib unimacro_ver -lib iplib=./iplib -lib unenclib -o simulate_isim.exe unenclib.tb unenclib.glbl diff --git a/testbench/signals.wcfg b/testbench/signals.wcfg new file mode 100644 index 0000000..dbb5e1a --- /dev/null +++ b/testbench/signals.wcfg @@ -0,0 +1,42 @@ +<?xml version="1.0" encoding="UTF-8"?> +<wave_config> + <wave_state> + </wave_state> + <db_ref_list> + <db_ref path="./isim.wdb" id="1" type="auto"> + <top_modules> + <top_module name="glbl" /> + <top_module name="tb" /> + </top_modules> + </db_ref> + </db_ref_list> + <WVObjectSize size="7" /> + <wvobject fp_name="/tb/project_i/LED_output_2" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">LED_output_2</obj_property> + <obj_property name="ObjectShortName">LED_output_2</obj_property> + </wvobject> + <wvobject fp_name="/tb/project_i/Switch_input_0" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">Switch_input_0</obj_property> + <obj_property name="ObjectShortName">Switch_input_0</obj_property> + </wvobject> + <wvobject fp_name="/tb/project_i/Switch_input_1" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">Switch_input_1</obj_property> + <obj_property name="ObjectShortName">Switch_input_1</obj_property> + </wvobject> + <wvobject fp_name="/tb/project_i/Switch_input_2" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">Switch_input_2</obj_property> + <obj_property name="ObjectShortName">Switch_input_2</obj_property> + </wvobject> + <wvobject fp_name="/tb/project_i/Switch_input_3" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">Switch_input_3</obj_property> + <obj_property name="ObjectShortName">Switch_input_3</obj_property> + </wvobject> + <wvobject fp_name="/tb/project_i/SYSTEMCLOCK" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">SYSTEMCLOCK</obj_property> + <obj_property name="ObjectShortName">SYSTEMCLOCK</obj_property> + </wvobject> + <wvobject fp_name="/tb/project_i/PUSH_BUTTON_RESET_RAW" type="logic" db_ref_id="1"> + <obj_property name="ElementShortName">PUSH_BUTTON_RESET_RAW</obj_property> + <obj_property name="ObjectShortName">PUSH_BUTTON_RESET_RAW</obj_property> + </wvobject> +</wave_config> diff --git a/testbench/simulate_isim.exe b/testbench/simulate_isim.exe Binary files differnew file mode 100755 index 0000000..5e50691 --- /dev/null +++ b/testbench/simulate_isim.exe diff --git a/testbench/simulate_isim.prj b/testbench/simulate_isim.prj new file mode 100644 index 0000000..e610cc5 --- /dev/null +++ b/testbench/simulate_isim.prj @@ -0,0 +1,3 @@ +verilog unenclib ../hdl/project.v
+verilog unenclib tb.v
+verilog unenclib /opt/Xilinx/14.3/ISE_DS/ISE/verilog/src/glbl.v
diff --git a/testbench/tb.v b/testbench/tb.v new file mode 100755 index 0000000..19e07bf --- /dev/null +++ b/testbench/tb.v @@ -0,0 +1,45 @@ +`timescale 1ps/1ps +module tb; + + reg CLK100; +always @(CLK100) begin + #4980.00 CLK100 <= ~CLK100; +end + +initial begin + #0 CLK100 <= 1'b0; // the first event that sets the clock in motion +end + + +reg [7:0] Switch_input; +wire [7:0] LED_output; +wire FPGA_RESET; + +project project_i ( + .PUSH_BUTTON_RESET_RAW(FPGA_RESET), + .LED_output_0(LED_output[0]), + .LED_output_1(LED_output[1]), + .LED_output_2(LED_output[2]), + .LED_output_3(LED_output[3]), + .LED_output_4(LED_output[4]), + .LED_output_5(LED_output[5]), + .LED_output_6(LED_output[6]), + .SYSTEMCLOCK(CLK100), + .Switch_input_0(Switch_input[0]), + .Switch_input_1(Switch_input[1]), + .Switch_input_2(Switch_input[2]), + .Switch_input_3(Switch_input[3]) + ); + + +initial begin + #0 Switch_input <= 8'h00; + $display("Switch set to zero"); + #1000000 Switch_input <= 8'h01; + $display("Switch set to one"); + #2000000 + $display("TEST COMPLETE"); + $finish(); +end + +endmodule |