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| author | Andrew J Meyer <ajm@leaflabs.com> | 2013-03-06 18:47:43 -0500 |
|---|---|---|
| committer | Andrew J Meyer <ajm@leaflabs.com> | 2013-03-06 18:47:43 -0500 |
| commit | 0754c0f771c51d48107c5c96d79a512ce56cce0a (patch) | |
| tree | d444913b56cc430f6c4b6050af6226e669919438 /synth_project/project.xst | |
| parent | 25e9b58c4a438292e9d07151c0f2ce73d1ed64f8 (diff) | |
| download | fpga-lube-0754c0f771c51d48107c5c96d79a512ce56cce0a.tar.gz fpga-lube-0754c0f771c51d48107c5c96d79a512ce56cce0a.zip | |
added the base files
Diffstat (limited to 'synth_project/project.xst')
| -rw-r--r-- | synth_project/project.xst | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/synth_project/project.xst b/synth_project/project.xst new file mode 100644 index 0000000..9a29456 --- /dev/null +++ b/synth_project/project.xst @@ -0,0 +1,53 @@ +set -tmpdir "./xst/projnav.tmp" +set -xsthdpdir "./xst" +run +-ifn project.prj +-ifmt mixed +-ofn project +-ofmt NGC +-p xc6slx45t-3-fgg484 +-top project +-lso project.lso +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-netlist_hierarchy rebuilt +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints YES +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc auto +-reduce_control_sets auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-use_dsp48 auto +# use NO for making NGC's and YES for making bitstreams +-iobuf YES +-max_fanout 100000 +-bufg 32 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5
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