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authorAndrew J Meyer <ajm@leaflabs.com>2013-03-06 18:47:43 -0500
committerAndrew J Meyer <ajm@leaflabs.com>2013-03-06 18:47:43 -0500
commit0754c0f771c51d48107c5c96d79a512ce56cce0a (patch)
treed444913b56cc430f6c4b6050af6226e669919438 /hdl
parent25e9b58c4a438292e9d07151c0f2ce73d1ed64f8 (diff)
downloadfpga-lube-0754c0f771c51d48107c5c96d79a512ce56cce0a.tar.gz
fpga-lube-0754c0f771c51d48107c5c96d79a512ce56cce0a.zip
added the base files
Diffstat (limited to 'hdl')
-rw-r--r--hdl/project.v26
1 files changed, 26 insertions, 0 deletions
diff --git a/hdl/project.v b/hdl/project.v
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index 0000000..753597b
--- /dev/null
+++ b/hdl/project.v
@@ -0,0 +1,26 @@
+module project
+ (
+ output wire LED_output_0,
+ output wire LED_output_1,
+ output wire LED_output_2,
+ output wire LED_output_3,
+ output wire LED_output_4,
+ output wire LED_output_5,
+ output wire LED_output_6,
+ input wire Switch_input_0,
+ input wire Switch_input_1,
+ input wire Switch_input_2,
+ input wire Switch_input_3,
+ input wire SYSTEMCLOCK,
+ input wire PUSH_BUTTON_RESET_RAW //Xilinx GTP - this is active low-
+ );
+
+ assign LED_output_0 = 1'b0;
+ assign LED_output_1 = 1'b0;
+ assign LED_output_2 = 1'b0;
+ assign LED_output_3 = 1'b0;
+ assign LED_output_4 = 1'b0;
+ assign LED_output_5 = 1'b0;
+ assign LED_output_6 = 1'b0;
+
+endmodule \ No newline at end of file