pull xilinx notes into sphinx docs

3 files changed, 98 insertions, 1 deletions

diff --git a/docs/index.rst b/docs/index.rst
index 35412a1..d53e14b 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -8,7 +8,9 @@ FPGA LUBE
 Contents:
 
 .. toctree::
-   :maxdepth: 2
+    :maxdepth: 2
+
+    xilinx_toolchain.rst
 
 About This Document
 ---------------------
diff --git a/docs/xilinx_filetypes_table.txt b/docs/xilinx_filetypes_table.txt
new file mode 100644
index 0000000..5f68a19
--- /dev/null
+++ b/docs/xilinx_filetypes_table.txt
@@ -0,0 +1,59 @@
+
+=========== ==============================================================================
+Extension   Description
+=========== ==============================================================================
+.par        "place and route" output
+.vhd        VHDL source code
+.v          Verilog source code
+.ucf        "constraints file": hardware pinouts, timing, etc
+.prj        [list of files in the project?]
+.wcfg       [waveform configuration (saved from gtkwave?]
+.srp        "Synthesis Report File"
+.xst        [xst settings?]
+.lso
+.vcf
+
+.bgn        bitgen report file
+.bit        Final FPGA bitstream file (binary)
+.xwbt
+.bld        Build report from NGDBuild
+.blc        NGDBuild report file
+.cmd_log
+.drc        Design rule check output
+.ncd
+.wdb
+.exe
+.map        [intermediate step]
+.mrp
+.ncd        [intermediate step? netlist?]
+.ngm
+.xrpt
+.par        [place and route output?]
+.pcf
+.ptwx
+.stx
+.syr
+.twr
+.twx
+.unroutes   unrouted traces; if routing was successful, there should be none
+.ut
+.xpi
+.log
+.xmsgs
+.gise
+.xise       ISE project/workplace
+
+.cgc        [coregen? used to programatically re-gen core?]
+.cgp        Coregen Project
+.ngc        Pre-compiled netlist
+.sym
+.asy        "Symbol file"
+_flist.txt  File list (?)
+.gise
+.ncf
+.sym
+.veo
+.vho
+.xco        [intermediate file?]
+=========== ==============================================================================
+
diff --git a/docs/xilinx_toolchain.rst b/docs/xilinx_toolchain.rst
new file mode 100644
index 0000000..ee49621
--- /dev/null
+++ b/docs/xilinx_toolchain.rst
@@ -0,0 +1,36 @@
+
+Xilinx Toolchain
+===================
+
+Chapter Two of "FPGAs!? Now What?" gives a good overview of the full
+compilation process. The basic layers are:
+
+**Synthesis**
+    The "logic synthesizer" compiles from HDL to a netlist
+
+**Implementation**
+    The "translator" takes a set of netlists and design constraints and generates
+    a merged netlist.
+
+    Then a "mapper" regroups the netlist so that place and route will be easier
+
+    Then a "place and route" tool decides exactly how the FPGA logic will be
+    configured
+
+**Bitstream**
+    The "bitstream generator" translates the configuration into the binary
+    format that the FPGA uses to re-flash itself
+
+File Extensions
+-------------------
+
+.. include:: xilinx_filetypes_table.txt
+
+
+See also:
+
+- https://github.com/JPNaude/X-MimeTypes/blob/master/eda_mime_types.xml
+- http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/cgn_r_core_generator_output_files.htm
+- http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ise_r_source_types.htm
+- devref.pdf (UG628)
+