blob: 8c1a519b452de398e340b3ba82266cbdc7bf9fc6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
|
### Notes
By default, re-synthesis of a project (eg, after making a change to any HDL
files) will attempt to use the previous place-and-route netlist as a starting
point via the "smartguide" mechanism. 'make mostlyclean' will prevent this.
By default, a git checkout will update timestamps on all files under version
control. There are good reasons for this, but it can be particularly
frustrating when there are large coregen cores in a project which must be
rebuilt from scratch, even is the .xco files were not touched. The
'untouchcores' target will try to cleverly reset timestamps to prevent this;
run it after a git pull or checkout.
Changes to Makefiles will *not* necessarily result in a full rebuild; the
makefiles themselves are not a prerequisite of any targets. It is *strongly*
recommended that you 'make clean' (not just 'mostlyclean') after any
significant modifications to project settings, particularly changes to the
target part number.
### Make Targets
make bitfiles - synths bitfiles and copies to ./bitfiles/ (DEFAULT)
make synth - compiles and synthesizes bitfiles (no copying)
make tests - runs all unittests
make lint - runs lint program on synthesizable Verilog files
make mostlyclean - cleans most sim and synth files
make clean - cleans all sim and synth files, incl. coregen'd
make untouchcores - reset timestamps on .xco files to last change
make isim/<name>_tb - compiles sim files, then launches simulator GUI
make isimcli/<name>_tb - compiles sim files, then launches simulator CLI
make resim/<name>_tb - recompiles sim files w/o launching GUI
make test/<name>_tb - runs a single unit test
make par_timingan - launches timing GUI with most recent build results
make par_fpga_editor - launches FPGA visualizer GUI for last build (slow!)
make coregen - launches Xilinx Coregen tool
make isim - launches Xilinx simulator GUI (no testbench loaded)
make ise - launches Xilinx IDE GUI (no project selected)
make impact - launches Xilinx JTAG program GUI (no bitfile)
make ldimpact - launches JTAG GUI with libusb libraries selected (Linux)
make timingan - launches Xilinx timing analysis GUI
make xreport - launches Xilinx log/warning browser
|
