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make bitfiles - synths bitfiles and copies to ./bitfiles/ (DEFAULT)
make synth - compiles and synthesizes bitfiles (no copying)
make tests - runs all unittests
make lint - runs lint program on synthesizable Verilog files
make mostlyclean - cleans most sim and synth files
make clean - cleans all sim and synth files, incl. coregen'd
make isim/<name>_tb - compiles sim files, then launches simulator GUI
make resim/<name>_tb - recompiles sim files w/o launching GUI
make test/<name>_tb - runs a single unit test
make par_timingan - launches timing GUI with most recent build results
make par_fpga_editor - launches FPGA visualizer GUI for last build (slow!)
make coregen - launches Xilinx Coregen tool
make isim - launches Xilinx simulator GUI (no testbench loaded)
make ise - launches new Xilinx IDE GUI (no project selected)
make ise - launches Xilinx IDE GUI (no project selected)
make impact - launches Xilinx JTAG program GUI (no bitfile)
make ldimpact - launches JTAG GUI with libusb libraries selected (Linux)
make timingan - launches Xilinx timing analysis GUI
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