blob: 826715e401f03b14e4ccf3c54dd520514d2635d4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
|
A very basic project template for Verilog simulation and synthesis using Isim
and Xilinx tools.
Contents:
hdl/
Verilog Code
tb/
"testbench" simulation code
docs/
documentation
contrib/
Project-independent build scripts are set here
backup/
A handful of old "known-good" bitfiles can get archived here.
sngdaq.ucf
Wired Leaf pinout definition file
Makefile
Project-specific build variables are set here
== HOWTO Build a Bitfile =====================================================
The Xilinx ISE development must be installed and licensed on the local machine.
A set of command-line build scripts are usually used to build the project
instead of the ISE IDE, but the later could be configured and used as well.
Python and GNU make must be on the $PATH.
Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in
Makefile) via:
make
The toplevel ucf (constraints mapping netlist objects from the verilog
compilation to hardware resources, and place and routing and timing
constraints) is:
./sngdaq.ucf
The toplevel verilog module, which does nothing (just sets some pins to zero)
lives in:
./hdl/sngdaq.v
To edit the project with the ISE GUI, try:
make ise
WARNING: the ISE configuration options may or may not be synchronized with the
command line build options. Edit the options in project.opt and build only from
the command line to be safe.
Simulate with isim via:
make simulate
View the results using the isim GUI with:
make isim
In isim, you can open the "signals.wcfg" in the file menu to reload a the logic
analyzer configuration. This cfg file will not be valid if you delete any
signals from your design that are saves in the wcfg.
./testbench/tb.v is the toplevel testbench file for simulation.
Please improve and push!
== HOWTO Coregen =============================================================
Run `make coregen` and use the GUI to generate a core.
Depending on the output, copy .v files to hdl/ and/or .xco files to cores/.
update the Makefile.
For any .xco files, strip the "Project Options" section and the final CRC line.
After making any changes to the target chipset (eg, by modifying Makefile),
you'll need to do a 'make clean' to ensure that the coregen logic is
resynthesized correctly.
|
