basic-hdl-template - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	typo: pre-par .ncd file for partial_timing analysis	bryan newbold	2013-06-27	1	-1/+1
*	parameterize unconstrained timing analysis	bryan newbold	2013-06-27	1	-2/+3
*	fix bugs with trce and par	bryan newbold	2013-06-27	1	-4/+4
*	break out synth_effort as a variable	bryan newbold	2013-06-27	1	-2/+3
*	fix potential problem with old etwr target	bryan newbold	2013-06-27	1	-1/+1
*	add planahead, fpga_editor, and timing targets	bryan newbold	2013-06-27	1	-13/+31
*	don't re-coregen after every little Makefile tweak	bryan newbold	2013-06-19	1	-1/+1
*	proper Makefile syntax; device-specific; mcs bitwidth	bryan newbold	2013-06-19	2	-2/+10
*	add 'make lint' verilog-build command; requires verilator	bryan newbold	2013-06-05	1	-1/+4
*	update with bnewbold's changes	bryan newbold	2013-03-27	1	-74/+63
*	initial colorization stuff	bryan newbold	2013-03-27	2	-1/+105
*	compile in multiple tb-modules (this might slow things down for you)	bryan newbold	2013-03-21	1	-2/+6
*	add .ucf file reference	bryan newbold	2013-03-21	1	-1/+1
*	isim in the background; hackisly fix deps	bryan newbold	2013-03-20	1	-4/+4
*	fixes to simulate	bryan newbold	2013-03-20	1	-8/+6
*	fix ise project pointers	bryan newbold	2013-03-14	1	-1/+1
*	improvements	bryan newbold	2013-03-14	2	-12/+32
*	some simulation stuff	bryan newbold	2013-03-13	1	-2/+38
*	move stuff around; backup	bryan newbold	2013-03-13	2	-48/+17
*	basic synthesis version of makefile	bryan newbold	2013-03-13	2	-0/+223