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* added build commits scriptAndrew J Meyer2013-08-191-0/+31
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* typo: pre-par .ncd file for partial_timing analysisbryan newbold2013-06-271-1/+1
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* parameterize unconstrained timing analysisbryan newbold2013-06-271-2/+3
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* fix bugs with trce and parbryan newbold2013-06-271-4/+4
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* break out synth_effort as a variablebryan newbold2013-06-271-2/+3
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* fix potential problem with old etwr targetbryan newbold2013-06-271-1/+1
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* add planahead, fpga_editor, and timing targetsbryan newbold2013-06-271-13/+31
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* don't re-coregen after every little Makefile tweakbryan newbold2013-06-191-1/+1
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* proper Makefile syntax; device-specific; mcs bitwidthbryan newbold2013-06-192-2/+10
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* add 'make lint' verilog-build command; requires verilatorbryan newbold2013-06-051-1/+4
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* update with bnewbold's changesbryan newbold2013-03-271-74/+63
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* initial colorization stuffbryan newbold2013-03-272-1/+105
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* compile in multiple tb-modules (this might slow things down for you)bryan newbold2013-03-211-2/+6
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* add .ucf file referencebryan newbold2013-03-211-1/+1
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* isim in the background; hackisly fix depsbryan newbold2013-03-201-4/+4
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* fixes to simulatebryan newbold2013-03-201-8/+6
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* fix ise project pointersbryan newbold2013-03-141-1/+1
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* improvementsbryan newbold2013-03-142-12/+32
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* some simulation stuffbryan newbold2013-03-131-2/+38
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* move stuff around; backupbryan newbold2013-03-132-48/+17
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* basic synthesis version of makefilebryan newbold2013-03-132-0/+223