basic-hdl-template - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	rename some targets	bryan newbold	2013-11-12	1	-8/+8
\| \| \| \| \| \| \| \|	"partial_" -> "map_" "final_" -> "par_" "clean" -> "mostlyclean" "cleanall" -> "clean" fix typos
*	hack fix for bug with include ordering	bryan newbold	2013-11-12	1	-2/+3
\| \| \| \| \| \|	There seems to be a problem with the default target being overriden when a board-specific file is included before xilinx.mk. Workaround is to include targets last.
*	reorder contrib/xilinx.mk; re-instate ./bitfile/	bryan newbold	2013-11-12	1	-16/+25
\| \| \| \| \|	Bitfiles, timing reports, and par netlists now get saved in ./bitfiles/ for every rebuild (determined by bitfile rebuild).
*	clean up cleaning (heh)	bryan newbold	2013-11-12	1	-3/+13
\| \| \| \| \|	This commit fixes an old problem where coregen files get wiped by a 'clean'. To completely clear out coregen'd stuff, now use 'cleanall'
*	Part 1 of refactoring template files into ./contrib	bryan newbold	2013-11-12	1	-76/+137
\| \| \| \| \| \| \| \|	BROKEN without later parts (documentation and Makefile updates) This commit moves and deletes a lot of Xula2 and SP605 files around. It also includes a large cleanup of xilinx.mk
*	minor cleanup of lint target	bryan newbold	2013-11-12	1	-1/+1
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*	initial VHDL support	bryan newbold	2013-11-12	1	-4/+16
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*	need to specify .pcf file to bitgen for some cases	bryan newbold	2013-10-21	1	-1/+1
\| \| \| \|	This was related to an "ERROR:PhysDesignRules:2199"
*	partially fix bug where synthesis continues after .ngc failure	bryan newbold	2013-10-09	1	-0/+2
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*	clean up test stuff	bryan newbold	2013-10-08	1	-0/+3
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*	working xula2 sim/syn/prog system	bryan newbold	2013-10-08	1	-2/+2
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*	don't have outputs depend on makefiles	bryan newbold	2013-10-08	1	-3/+3
\| \| \| \| \| \| \| \|	If the Makefiles are tweaked, it's up to the user to 'make clean' if necessary. The way things were previously, the entire project would get rebuilt after any trivial tweak or fix.
*	linting: ignore module/filename equivalence	bryan newbold	2013-10-06	1	-1/+1
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*	add test/ and isim/ system	bryan newbold	2013-10-06	1	-12/+34
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*	add concept of 'board' for seperate ucfs and top level modules	bryan newbold	2013-10-04	1	-22/+23
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*	add autoimpact target (pre-select bitfile)	bryan newbold	2013-10-04	1	-0/+3
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*	generic timingan target	bryan newbold	2013-10-04	1	-0/+3
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*	backport improvements from SNG project	bryan newbold	2013-10-04	1	-3/+7
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*	typo: pre-par .ncd file for partial_timing analysis	bryan newbold	2013-06-27	1	-1/+1
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*	parameterize unconstrained timing analysis	bryan newbold	2013-06-27	1	-2/+3
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*	fix bugs with trce and par	bryan newbold	2013-06-27	1	-4/+4
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*	break out synth_effort as a variable	bryan newbold	2013-06-27	1	-2/+3
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*	fix potential problem with old etwr target	bryan newbold	2013-06-27	1	-1/+1
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*	add planahead, fpga_editor, and timing targets	bryan newbold	2013-06-27	1	-13/+31
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*	don't re-coregen after every little Makefile tweak	bryan newbold	2013-06-19	1	-1/+1
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*	proper Makefile syntax; device-specific; mcs bitwidth	bryan newbold	2013-06-19	1	-2/+3
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*	add 'make lint' verilog-build command; requires verilator	bryan newbold	2013-06-05	1	-1/+4
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*	update with bnewbold's changes	bryan newbold	2013-03-27	1	-74/+63
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*	initial colorization stuff	bryan newbold	2013-03-27	1	-1/+1
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*	compile in multiple tb-modules (this might slow things down for you)	bryan newbold	2013-03-21	1	-2/+6
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*	add .ucf file reference	bryan newbold	2013-03-21	1	-1/+1
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*	isim in the background; hackisly fix deps	bryan newbold	2013-03-20	1	-4/+4
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*	fixes to simulate	bryan newbold	2013-03-20	1	-8/+6
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*	fix ise project pointers	bryan newbold	2013-03-14	1	-1/+1
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*	improvements	bryan newbold	2013-03-14	1	-12/+20
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*	some simulation stuff	bryan newbold	2013-03-13	1	-2/+38
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*	move stuff around; backup	bryan newbold	2013-03-13	1	-6/+17
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*	basic synthesis version of makefile	bryan newbold	2013-03-13	1	-0/+181