5 files changed, 0 insertions, 89 deletions
diff --git a/synth_project/make.sh b/synth_project/make.sh
deleted file mode 100755
index 807eba5..0000000
--- a/synth_project/make.sh
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh -e
-
-TOP_NAME=project
-
-# ensure directory is created
-./xst/projnav.tmp/
-
-xst -ifn $TOP_NAME.xst
-ngdbuild $TOP_NAME.ngc -verbose
-map -pr b -w -detail $TOP_NAME.ngd
-par -w $TOP_NAME $TOP_NAME.ncd
-bitgen -w $TOP_NAME.ncd
-
diff --git a/synth_project/project.lso b/synth_project/project.lso
deleted file mode 100755
index a340c10..0000000
--- a/synth_project/project.lso
+++ /dev/null
@@ -1 +0,0 @@
-work
-\ No newline at end of file
diff --git a/synth_project/project.prj b/synth_project/project.prj
deleted file mode 100644
index 3262aa0..0000000
--- a/synth_project/project.prj
+++ /dev/null
@@ -1 +0,0 @@
- verilog work ../hdl/project.v
diff --git a/synth_project/project.ucf b/synth_project/project.ucf
deleted file mode 100755
index 322c05a..0000000
--- a/synth_project/project.ucf
+++ /dev/null
@@ -1,21 +0,0 @@
-NET "PUSH_BUTTON_RESET_RAW" LOC = F3;
-
-#100MHz clock
-NET "SYSTEMCLOCK" LOC = K21;
-
-NET "Switch_input_0" LOC = C18;
-NET "Switch_input_1" LOC = Y6;
-NET "Switch_input_2" LOC = W6;
-NET "Switch_input_3" LOC = E4;
-
-NET "LED_output_1" LOC = D17;
-NET "LED_output_2" LOC = AB4;
-NET "LED_output_4" LOC = D21;
-NET "LED_output_5" LOC = W15;
-
-# Defines the external differential clock to be 150 MHz with 50% duty
-# cycle.
-
-NET "SYSTEMCLOCK" TNM_NET = "SYSTEMCLOCK";
-TIMESPEC TS__SYSTEMCLOCK = PERIOD "SYSTEMCLOCK" 5 ns HIGH 50 % PRIORITY 2;
-
diff --git a/synth_project/project.xst b/synth_project/project.xst
deleted file mode 100644
index 9a29456..0000000
--- a/synth_project/project.xst
+++ /dev/null
@@ -1,53 +0,0 @@
-set -tmpdir "./xst/projnav.tmp"
-set -xsthdpdir "./xst"
-run
--ifn project.prj
--ifmt mixed
--ofn project
--ofmt NGC
--p xc6slx45t-3-fgg484
--top project
--lso project.lso
--opt_mode Speed
--opt_level 1
--power NO
--iuc NO
--netlist_hierarchy rebuilt
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints YES
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--dsp_utilization_ratio 100
--lc auto
--reduce_control_sets auto
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style lut
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--shreg_extract YES
--rom_style Auto
--auto_bram_packing NO
--resource_sharing YES
--async_to_sync NO
--use_dsp48 auto
-# use NO for making NGC's and YES for making bitstreams
--iobuf YES
--max_fanout 100000
--bufg 32
--register_duplication YES
--register_balancing No
--optimize_primitives NO
--use_clock_enable Auto
--use_sync_set Auto
--use_sync_reset Auto
--iob auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
-\ No newline at end of file