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-rw-r--r--Makefile1
-rw-r--r--hdl/main_xula2.v2
2 files changed, 1 insertions, 2 deletions
diff --git a/Makefile b/Makefile
index b0de5d6..2b93161 100644
--- a/Makefile
+++ b/Makefile
@@ -19,7 +19,6 @@ device := XC6SLX25
speedgrade := -2
device_package := ftg256
extra_includes = ./contrib/xula2.mk
-include ./contrib/xula2.mk
part := $(device)$(speedgrade)-$(device_package)
diff --git a/hdl/main_xula2.v b/hdl/main_xula2.v
index 49581e1..4436665 100644
--- a/hdl/main_xula2.v
+++ b/hdl/main_xula2.v
@@ -36,7 +36,7 @@ module main (
wire [7:0] rx_byte;
wire [7:0] tx_byte;
wire uart_flag;
- simple_uart (
+ simple_uart #(
.CLOCK_DIVIDE(313) // for 12MHz clock
) simple_uart_inst (
.clk(clock_12mhz),