diff options
| -rw-r--r-- | .gitignore | 47 | ||||
| -rw-r--r-- | README | 4 | ||||
| -rwxr-xr-x | synth_project/make.sh | 4 | ||||
| -rw-r--r-- | synth_project/project.srp | 32 |
4 files changed, 53 insertions, 34 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..86a0f82 --- /dev/null +++ b/.gitignore @@ -0,0 +1,47 @@ +*.o +*.a +*.pyc +*~ +*.swp +.* +*.tmp +*.old +_xmsgs/ +par_usage_statistics.html +*.bgn +*.bit +*.bld +*.drc +*.map +*.mrp +*.ncd +*.ngc +*.ngd +*.pad +*.par +*.pcf +*.ptwx +*.unroutes +*.xpi +*.xwbt +*.xrpt +synth_project/netlist.lst +synth_project/*_pad.csv +synth_project/*_pad.txt +synth_project/*_summary.xml +synth_project/*_usage.xml +synth_project/*_xst.xrpt +synth_project/*.ngm +synth_project/*.ngr +synth_project/usage_statistics_webtalk.html +synth_project/xst/ +usage_statistics_webtalk.html +webtalk.log +xlnx_auto_0_xdb +testbench/fuse.log +testbench/isim.log +testbench/isim.wdb +testbench/fuse.xmsgs +testbench/fuseRelaunch.cmd +testbench/isim.wdb +testbench/isim/ @@ -6,7 +6,7 @@ everything a can where things will still build. Build a bitstream (to upload to an FPGA, preconfigured as Spartan 6 chip in one of the conf files) via: -.synth_project/make.sh +./synth_project/make.sh the toplevel ucf (constraints mapping netlist objects from the verilog compilation to hardware resources, and place and routing and timing constraints) @@ -31,4 +31,4 @@ signals from your design that are saves in the wcfg. ./testbench/tb.v is the toplevel testbench file for simulation. -Please improve and push!
\ No newline at end of file +Please improve and push! diff --git a/synth_project/make.sh b/synth_project/make.sh index 174a6ac..807eba5 100755 --- a/synth_project/make.sh +++ b/synth_project/make.sh @@ -1,6 +1,10 @@ #!/bin/sh -e TOP_NAME=project + +# ensure directory is created +./xst/projnav.tmp/ + xst -ifn $TOP_NAME.xst ngdbuild $TOP_NAME.ngc -verbose map -pr b -w -detail $TOP_NAME.ngd diff --git a/synth_project/project.srp b/synth_project/project.srp deleted file mode 100644 index 3a35165..0000000 --- a/synth_project/project.srp +++ /dev/null @@ -1,32 +0,0 @@ -Release 14.3 - xst P.40xd (lin64) -Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ---> -Parameter TMPDIR set to ./xst/projnav.tmp - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.06 secs - ---> -Parameter xsthdpdir set to ./xst - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.06 secs - ---> -ERROR:Xst:438 - Can not open file : proejct.prj - - -Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.08 secs - ---> - - -Total memory usage is 284024 kilobytes - -Number of errors : 1 ( 0 filtered) -Number of warnings : 0 ( 0 filtered) -Number of infos : 0 ( 0 filtered) - |