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authorbryan newbold <bnewbold@leaflabs.com>2013-10-08 23:33:18 -0400
committerbryan newbold <bnewbold@leaflabs.com>2013-10-08 23:48:05 -0400
commit3b13cb7d690ba1891f008d2905fcfb36049c71ff (patch)
tree12ddf94a955c2f8611c43c269d4620629fa3d31c /hdl
parentb31c07157b7b8ca7e8823749e140fcab24b787d2 (diff)
downloadbasic-hdl-template-3b13cb7d690ba1891f008d2905fcfb36049c71ff.tar.gz
basic-hdl-template-3b13cb7d690ba1891f008d2905fcfb36049c71ff.zip
clean up test stuff
Diffstat (limited to 'hdl')
-rw-r--r--hdl/rot13.v46
1 files changed, 46 insertions, 0 deletions
diff --git a/hdl/rot13.v b/hdl/rot13.v
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+/*
+ * rot13.v
+ *
+ * Copyright: (C) 2013 LeafLabs, LLC
+ * License: MIT License (See LICENSE file)
+ * Author: Bryan Newbold <bnewbold@leaflabs.com>
+ * Date: October 2013
+ *
+ * This is a very simple ASCII ROT13 implementation.
+ *
+ * Data on in_char is sampled on the rising edge of clock and updated on
+ * out_char one clock cycle later.
+ *
+ */
+
+module rot13 (
+ input wire clock,
+ input wire reset,
+ input wire [7:0] in_char,
+ output reg [7:0] out_char = 8'd0
+ );
+
+ always @(posedge clock) begin
+ if (reset) begin
+ out_char <= 8'd0;
+ end else begin
+ if (in_char >= 8'd97 && in_char < 8'd110) begin
+ // 'a' through 'm'
+ out_char <= in_char + 8'd13;
+ end else if (in_char >= 8'd110 && in_char < 8'd123) begin
+ // 'n' through 'z'
+ out_char <= in_char - 8'd13;
+ end else if (in_char >= 8'd65 && in_char < 8'd78) begin
+ // 'A' through 'M'
+ out_char <= in_char + 8'd13;
+ end else if (in_char >= 8'd78 && in_char < 8'd91) begin
+ // 'N' through 'Z'
+ out_char <= in_char - 8'd13;
+ end else begin
+ // all other characters
+ out_char <= in_char;
+ end
+ end
+ end
+
+endmodule