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authorbryan newbold <bnewbold@leaflabs.com>2013-06-27 18:44:54 -0400
committerbryan newbold <bnewbold@leaflabs.com>2013-06-27 18:44:54 -0400
commit05339331c99cf830abae0985237437e06b9bcc3a (patch)
tree4d53f9309c4ae85c21aa01cba408c4999b5823f0 /hdl
parent73ba50aad4cd83e45dd710e4a6d8f660876b4f50 (diff)
downloadbasic-hdl-template-05339331c99cf830abae0985237437e06b9bcc3a.tar.gz
basic-hdl-template-05339331c99cf830abae0985237437e06b9bcc3a.zip
a better minimalist project, including a timing constraint
Diffstat (limited to 'hdl')
-rw-r--r--hdl/project.v49
1 files changed, 27 insertions, 22 deletions
diff --git a/hdl/project.v b/hdl/project.v
index 9e382a5..1b4f9f2 100644
--- a/hdl/project.v
+++ b/hdl/project.v
@@ -1,26 +1,31 @@
-module main
- (
- output wire LED_output_0,
- output wire LED_output_1,
- output wire LED_output_2,
- output wire LED_output_3,
- output wire LED_output_4,
- output wire LED_output_5,
- output wire LED_output_6,
- input wire Switch_input_0,
- input wire Switch_input_1,
- input wire Switch_input_2,
- input wire Switch_input_3,
- input wire SYSTEMCLOCK,
- input wire PUSH_BUTTON_RESET_RAW //Xilinx GTP - this is active low-
+// very minimal example top-level module
+
+module main (
+ output reg [3:0] gpio_led,
+ input wire [3:0] gpio_switch,
+ input wire SYSTEMCLOCK,
+ input wire PUSH_BUTTON_RESET_RAW // this is active low
);
- assign LED_output_0 = 1'b0;
- assign LED_output_1 = 1'b0;
- assign LED_output_2 = 1'b0;
- assign LED_output_3 = 1'b0;
- assign LED_output_4 = 1'b0;
- assign LED_output_5 = 1'b0;
- assign LED_output_6 = 1'b0;
+ wire reset;
+ assign reset = !PUSH_BUTTON_RESET_RAW;
+
+ reg [25:0] throb_counter = 0;
+
+ always @(posedge SYSTEMCLOCK) begin
+ if (reset) begin
+ gpio_led <= 7'b1111;
+ throb_counter <= 26'd0;
+ end else begin
+ gpio_led[1:0] <= gpio_switch[1:0];
+ gpio_led[2] <= gpio_switch[2] || gpio_switch[3];
+ if (throb_counter >= 26'd50_000_000) begin
+ gpio_led[3] <= !gpio_led[3];
+ throb_counter <= 26'd0;
+ end else begin
+ throb_counter <= throb_counter + 26'd1;
+ end
+ end
+ end
endmodule