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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-06-27 18:45:22 -0400 |
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| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-06-27 18:45:22 -0400 |
| commit | 1a79feb965430e8d523b4e9cf5a48fe89feeb441 (patch) | |
| tree | 449bf46b19e8c5248d54450afde4fc8442ecc973 /cores | |
| parent | 05339331c99cf830abae0985237437e06b9bcc3a (diff) | |
| download | basic-hdl-template-1a79feb965430e8d523b4e9cf5a48fe89feeb441.tar.gz basic-hdl-template-1a79feb965430e8d523b4e9cf5a48fe89feeb441.zip | |
commit an .xco as an example of stripped project metadata
Diffstat (limited to 'cores')
| -rw-r--r-- | cores/bram.xco | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/cores/bram.xco b/cores/bram.xco new file mode 100644 index 0000000..add7f6a --- /dev/null +++ b/cores/bram.xco @@ -0,0 +1,76 @@ +############################################################## +# +# Xilinx Core Generator version 14.3 +# Date: Wed Mar 13 21:43:25 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:4.1 +# +############################################################## +# +# BEGIN Select +SELECT Block_Memory_Generator family Xilinx,_Inc. 4.1 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=false +CSET byte_size=8 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=bram +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET enable_a=Use_ENA_Pin +CSET enable_b=Use_ENB_Pin +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET load_init_file=false +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=READ_FIRST +CSET operating_mode_b=READ_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=512 +CSET read_width_b=512 +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET use_byte_write_enable=true +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=true +CSET write_depth_a=32 +CSET write_width_a=512 +CSET write_width_b=512 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-03-06T04:24:23Z +# END Extra information +GENERATE |