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author | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 20:04:08 -0500 |
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committer | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 20:04:13 -0500 |
commit | 8e55b5eee512c3088ff01719875249640cf1efca (patch) | |
tree | 3428f69c78cf83f1b0b00e7697fbd0ac35f6e897 /contrib | |
parent | 4782465ef5d08bd7e7a36085a3013ed379e90ec2 (diff) | |
download | basic-hdl-template-8e55b5eee512c3088ff01719875249640cf1efca.tar.gz basic-hdl-template-8e55b5eee512c3088ff01719875249640cf1efca.zip |
add a "complicated" Makefile for testing
Also the corresponding top-level module (for Xula2)
Diffstat (limited to 'contrib')
-rw-r--r-- | contrib/Makefile.complicated | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/contrib/Makefile.complicated b/contrib/Makefile.complicated new file mode 100644 index 0000000..883248a --- /dev/null +++ b/contrib/Makefile.complicated @@ -0,0 +1,42 @@ +# This makefile is helpful for build system development because it exersizes +# more features (eg, coregen stuff). +# You may wish to symlink it from the top-level Makefile + +project := complicatedproj +top_module := complicated +vendor := xilinx + +include ./contrib/xula2/settings.mk +extra_includes += ./contrib/xula2/targets.mk + +part := $(device)$(speedgrade)-$(device_package) + +hostbits := 64 + +iseenv := /opt/Xilinx/14.3/ISE_DS/ +#iseenv := /opt/Xilinx/14.7/ISE_DS/ + +verilog_files += hdl/complicated.v +verilog_files += hdl/rot13.v + +vhdl_files += + +extra_prj += + +tbfiles += tb/rot13_tb.v + +gitcommit = $(shell (git log --abbrev=8 --oneline -n 1 2> /dev/null || echo "00000000") | head -c 8) +build_unixtime = $(shell date +%s || echo "0") +vgenerics += "GIT_COMMIT=h$(gitcommit)" +vgenerics += "BUILD_UNIX_TIME=d$(build_unixtime)" + +xilinx_cores += cores/bram.xco + +mcs_datawidth := 32 + +bmm_file := contrib/empty.bmm + +include ./contrib/xilinx.mk + +include $(extra_includes) + |