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| author | bryan newbold <bnewbold@leaflabs.com> | 2014-03-24 15:32:08 -0400 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2014-03-24 15:32:08 -0400 |
| commit | 746e334cdf3f45cbcdfa0f5cc7c5974a77875224 (patch) | |
| tree | 87f4c02ed79b3c1d0465c289f3d207344a1f7309 /contrib | |
| parent | 758fc78e0ef900c8207718c03e7d385d6ab3c0b4 (diff) | |
| download | basic-hdl-template-746e334cdf3f45cbcdfa0f5cc7c5974a77875224.tar.gz basic-hdl-template-746e334cdf3f45cbcdfa0f5cc7c5974a77875224.zip | |
lint: add color, recursive include, Xilinx primitives
All subdirectories below ./hdl are now added to the lint search path.
%Error and %Warning get colorized.
Xilinx Unisim primitives use empty template definitions; errors in this
file are ignored using a verilator config file.
Diffstat (limited to 'contrib')
| -rw-r--r-- | contrib/xilinx.mk | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/contrib/xilinx.mk b/contrib/xilinx.mk index 3d2a927..adcb792 100644 --- a/contrib/xilinx.mk +++ b/contrib/xilinx.mk @@ -103,6 +103,10 @@ PWD := $(shell pwd) # The following are used to color-code console build output colorize ?= 2>&1 | python $(PWD)/contrib/colorize.py red ERROR: yellow WARNING: green \"Number of error messages: 0\" green \"Number of error messages:\t0\" green \"Number of errors: 0\" colorizetest ?= 2>&1 | python $(PWD)/contrib/colorize.py red FAIL green PASS +colorizelint ?= 2>&1 | python $(PWD)/contrib/colorize.py red %Error yellow %Warning + +# Build up lint include path from all paths below ./hdl/ +lint_search += $(foreach d, $(shell /usr/bin/find ./hdl/ -type d), -I$(d)) # Library stuff (TODO: untested) libs ?= @@ -397,7 +401,10 @@ par_timingan: build/$(project)_post_par.twr timingan -ucf ../$(ucf_file) $(project)_par.ncd $(project).pcf $(project)_post_par.twx &" lint: - verilator --lint-only -I./hdl -I./cores -Wall -Wno-DECLFILENAME hdl/$(top_module)_$(board) || true + @mkdir -p build + @echo "\`verilator_config" > build/verilator_opts.vlt + @echo 'lint_off -file "$(iseenv)/ISE/verilog/src/iSE/unisim_comp.v"' >> build/verilator_opts.vlt + verilator --lint-only -I./cores $(lint_search) -Wall -Wno-DECLFILENAME -v $(iseenv)/ISE/verilog/src/iSE/unisim_comp.v build/verilator_opts.vlt $(lint_extra) hdl/$(top_module)_$(board) $(colorizelint) || true help: @cat ./contrib/README |