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author | bryan newbold <bnewbold@leaflabs.com> | 2013-11-13 09:48:53 -0500 |
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committer | bryan newbold <bnewbold@leaflabs.com> | 2013-11-13 09:48:53 -0500 |
commit | 46750548a529068726f74764d752badc231b2b4d (patch) | |
tree | e2d012e1e91c975fec202a228a0b0b94b2d28c76 /contrib/TODO.template | |
parent | dc35d064b8b3b5e1cc62d5f58a24dd4d5aa36996 (diff) | |
download | basic-hdl-template-46750548a529068726f74764d752badc231b2b4d.tar.gz basic-hdl-template-46750548a529068726f74764d752badc231b2b4d.zip |
update template's TODO file
Diffstat (limited to 'contrib/TODO.template')
-rw-r--r-- | contrib/TODO.template | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/contrib/TODO.template b/contrib/TODO.template deleted file mode 100644 index cc47521..0000000 --- a/contrib/TODO.template +++ /dev/null @@ -1,45 +0,0 @@ - -switch to .EXPORT_ALL_VARIABLES and/or .ONESHELL (as a refactor/cleanup)? - or is that too gmake specific... - -BUG: synth still seems to continue even if first build (verilog compile) - fails - -add .PRECIOUS for intermediate files we don't want to get deleted - -'lint' should use vfiles, not -I./hdl - -for fpga_editor: - DISPLAY=`echo $DISPLAY |sed s/'\.0'//` fpga_editor <.ncd file> - -effort levels seem high by default: - Overall effort level (-ol): High - Router effort level (-rl): High - -impact: - impact -mode bscan -b build/sp605.bit -port auto -autoassign (needs testing) - -requests from AJ: - anything related to not rebuilding all the coregen when not necessary. - - e.g. want a make clean equivalent to removing the build dir but not the - cores. This should actually be the default behavior, with different - operator for nixing the cores. - - not auto rebuilding the cores when switching branches/commits if not - strictly necessary. Because git touches all the files, this may be - difficult. - - make isim/simulate will run to completion even if there were errors on - the build. - - In the case of make isim, isim will load and run the previously valid - simulation. Unless you happen to see the error go by in the build log, - you will unknowingly be simulating your previous build, whereas your - current build failed to compile. - - The solution is to have make simulate begin by deleting the previous - simulation executable, so that it must successfully create a new one - before loading isim. - -Add linting to tests (aka, tb/*_tb.v) |