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| author | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 20:36:54 -0500 |
|---|---|---|
| committer | bryan newbold <bnewbold@leaflabs.com> | 2013-11-12 20:36:54 -0500 |
| commit | dc35d064b8b3b5e1cc62d5f58a24dd4d5aa36996 (patch) | |
| tree | 5095c382cd66e89840ad89feceb062c6036b2930 /contrib/README | |
| parent | ade169c6e07f654591af61f83de5bb90898d09b1 (diff) | |
| download | basic-hdl-template-dc35d064b8b3b5e1cc62d5f58a24dd4d5aa36996.tar.gz basic-hdl-template-dc35d064b8b3b5e1cc62d5f58a24dd4d5aa36996.zip | |
misc small improvements
more aliases
help target
Diffstat (limited to 'contrib/README')
| -rw-r--r-- | contrib/README | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/contrib/README b/contrib/README new file mode 100644 index 0000000..55508f8 --- /dev/null +++ b/contrib/README @@ -0,0 +1,23 @@ + +make bitfiles - synths bitfiles and copies to ./bitfiles/ (DEFAULT) +make synth - compiles and synthesizes bitfiles (no copying) +make tests - runs all unittests +make lint - runs lint program on synthesizable Verilog files +make mostlyclean - cleans most sim and synth files +make clean - cleans all sim and synth files, incl. coregen'd + +make isim/<name>_tb - compiles sim files, then launches simulator GUI +make resim/<name>_tb - recompiles sim files w/o launching GUI +make test/<name>_tb - runs a single unit test + +make par_timingan - launches timing GUI with most recent build results +make par_fpga_editor - launches FPGA visualizer GUI for last build (slow!) + +make coregen - launches Xilinx Coregen tool +make isim - launches Xilinx simulator GUI (no testbench loaded) +make ise - launches new Xilinx IDE GUI (no project selected) +make ise - launches Xilinx IDE GUI (no project selected) +make impact - launches Xilinx JTAG program GUI (no bitfile) +make ldimpact - launches JTAG GUI with libusb libraries selected (Linux) +make timingan - launches Xilinx timing analysis GUI + |