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-rw-r--r--libmaple/exti.c234
-rw-r--r--libmaple/exti.h13
-rw-r--r--libmaple/libmaple_types.h4
-rw-r--r--libmaple/nvic.h37
-rw-r--r--wirish/boards.h102
-rw-r--r--wirish/ext_interrupts.c36
-rw-r--r--wirish/ext_interrupts.h11
7 files changed, 173 insertions, 264 deletions
diff --git a/libmaple/exti.c b/libmaple/exti.c
index 5575906..8a54457 100644
--- a/libmaple/exti.c
+++ b/libmaple/exti.c
@@ -33,10 +33,32 @@
#include "exti.h"
#include "nvic.h"
-volatile static voidFuncPtr exti_handlers[NR_EXTI_CHANNELS];
+typedef struct ExtIChannel {
+ void (*handler)(void);
+ uint32 irq_line;
+} ExtIChannel;
+
+static ExtIChannel exti_channels[] = {
+ { .handler = NULL, .irq_line = NVIC_EXTI0 }, // EXTI0
+ { .handler = NULL, .irq_line = NVIC_EXTI1 }, // EXTI1
+ { .handler = NULL, .irq_line = NVIC_EXTI2 }, // EXTI2
+ { .handler = NULL, .irq_line = NVIC_EXTI3 }, // EXTI3
+ { .handler = NULL, .irq_line = NVIC_EXTI4 }, // EXTI4
+ { .handler = NULL, .irq_line = NVIC_EXTI9_5 }, // EXTI5
+ { .handler = NULL, .irq_line = NVIC_EXTI9_5 }, // EXTI6
+ { .handler = NULL, .irq_line = NVIC_EXTI9_5 }, // EXTI7
+ { .handler = NULL, .irq_line = NVIC_EXTI9_5 }, // EXTI8
+ { .handler = NULL, .irq_line = NVIC_EXTI9_5 }, // EXTI9
+ { .handler = NULL, .irq_line = NVIC_EXTI15_10 }, // EXTI10
+ { .handler = NULL, .irq_line = NVIC_EXTI15_10 }, // EXTI11
+ { .handler = NULL, .irq_line = NVIC_EXTI15_10 }, // EXTI12
+ { .handler = NULL, .irq_line = NVIC_EXTI15_10 }, // EXTI13
+ { .handler = NULL, .irq_line = NVIC_EXTI15_10 }, // EXTI14
+ { .handler = NULL, .irq_line = NVIC_EXTI15_10 }, // EXTI15
+};
static inline void clear_pending(int bit) {
- REG_SET(EXTI_PR, BIT(bit));
+ __set_bits(EXTI_PR, BIT(bit));
/* If the pending bit is cleared as the last instruction in an ISR,
* it won't actually be cleared in time and the ISR will fire again.
* Insert a 2-cycle buffer to allow it to take effect. */
@@ -44,61 +66,39 @@ static inline void clear_pending(int bit) {
asm volatile("nop");
}
+static inline void dispatch_handler(uint32 channel) {
+ ASSERT(exti_channels[channel].handler);
+ if (exti_channels[channel].handler) {
+ (exti_channels[channel].handler)();
+ }
+}
+
/* For EXTI0 through EXTI4, only one handler
* is associated with each channel, so we
* don't have to keep track of which channel
* we came from */
void EXTI0_IRQHandler(void) {
- ASSERT(exti_handlers[EXTI0]);
- if (exti_handlers[EXTI0]) {
- exti_handlers[EXTI0]();
- }
-
- /* Clear pending bit*/
+ dispatch_handler(EXTI0);
clear_pending(EXTI0);
}
void EXTI1_IRQHandler(void) {
- ASSERT(exti_handlers[EXTI1]);
- /* Call registered handler */
- if (exti_handlers[EXTI1]) {
- exti_handlers[EXTI1]();
- }
-
- /* Clear pending bit*/
+ dispatch_handler(EXTI1);
clear_pending(EXTI1);
}
void EXTI2_IRQHandler(void) {
- ASSERT(exti_handlers[EXTI2]);
- /* Call registered handler */
- if (exti_handlers[EXTI2]) {
- exti_handlers[EXTI2]();
- }
-
- /* Clear pending bit*/
+ dispatch_handler(EXTI2);
clear_pending(EXTI2);
}
void EXTI3_IRQHandler(void) {
- ASSERT(exti_handlers[EXTI3]);
- /* Call registered handler */
- if (exti_handlers[EXTI3]) {
- exti_handlers[EXTI3]();
- }
-
- /* Clear pending bit*/
+ dispatch_handler(EXTI3);
clear_pending(EXTI3);
}
void EXTI4_IRQHandler(void) {
- ASSERT(exti_handlers[EXTI4]);
- /* Call registered handler */
- if (exti_handlers[EXTI4]) {
- exti_handlers[EXTI4]();
- }
-
- /* Clear pending bit*/
+ dispatch_handler(EXTI4);
clear_pending(EXTI4);
}
@@ -112,8 +112,7 @@ void EXTI9_5_IRQHandler(void) {
/* Dispatch every handler if the pending bit is set */
for (i = 0; i < 5; i++) {
if (pending & 0x1) {
- ASSERT(exti_handlers[EXTI5 + i]);
- exti_handlers[EXTI5 + i]();
+ dispatch_handler(EXTI5 + i);
clear_pending(EXTI5 + i);
}
pending >>= 1;
@@ -130,8 +129,7 @@ void EXTI15_10_IRQHandler(void) {
/* Dispatch every handler if the pending bit is set */
for (i = 0; i < 6; i++) {
if (pending & 0x1) {
- ASSERT(exti_handlers[EXTI10 + i]);
- exti_handlers[EXTI10 + i]();
+ dispatch_handler(EXTI10 + i);
clear_pending(EXTI10 + i);
}
pending >>= 1;
@@ -139,147 +137,73 @@ void EXTI15_10_IRQHandler(void) {
}
-void exti_attach_interrupt(uint8 channel, uint8 port, voidFuncPtr handler, uint8 mode) {
- ASSERT(channel < NR_EXTI_CHANNELS);
- ASSERT(port < NR_EXTI_PORTS);
- ASSERT(mode < NR_EXTI_MODES);
- ASSERT(EXTI0 == 0);
- ASSERT(handler);
+/**
+ * @brief Register a handler to run upon external interrupt
+ * @param port source port of pin (eg EXTI_CONFIG_PORTA)
+ * @param pin pin number on the source port
+ * @param handler function handler to execute
+ * @param mode type of transition to trigger on
+ */
+void exti_attach_interrupt(uint32 port,
+ uint32 pin,
+ voidFuncPtr handler,
+ uint32 mode) {
+ static uint32 afio_regs[] = {
+ AFIO_EXTICR1, // EXT0-3
+ AFIO_EXTICR2, // EXT4-7
+ AFIO_EXTICR3, // EXT8-11
+ AFIO_EXTICR4, // EXT12-15
+ };
/* Note: All of the following code assumes that EXTI0 = 0 */
+ ASSERT(EXTI0 == 0);
+ ASSERT(handler);
- /* Map port to the correct EXTI channel */
- switch (channel) {
- case EXTI0:
- case EXTI1:
- case EXTI2:
- case EXTI3:
- REG_SET_MASK(AFIO_EXTICR1, BIT_MASK_SHIFT(port, channel*4));
- break;
-
- case EXTI4:
- case EXTI5:
- case EXTI6:
- case EXTI7:
- REG_SET_MASK(AFIO_EXTICR2, BIT_MASK_SHIFT(port, (channel-4)*4));
- break;
-
- case EXTI8:
- case EXTI9:
- case EXTI10:
- case EXTI11:
- REG_SET_MASK(AFIO_EXTICR3, BIT_MASK_SHIFT(port, (channel-8)*4));
- break;
+ uint32 channel = pin;
- case EXTI12:
- case EXTI13:
- case EXTI14:
- case EXTI15:
- REG_SET_MASK(AFIO_EXTICR4, BIT_MASK_SHIFT(port, (channel-12)*4));
- break;
- }
+ /* map port to channel */
+ __write(afio_regs[pin/4], (port << ((pin % 4) * 4)));
/* Unmask appropriate interrupt line */
- REG_SET_BIT(EXTI_IMR, channel);
+ __set_bits(EXTI_IMR, BIT(channel));
/* Set trigger mode */
switch (mode) {
case EXTI_RISING:
- REG_SET_BIT(EXTI_RTSR, channel);
+ __set_bits(EXTI_RTSR, BIT(channel));
break;
case EXTI_FALLING:
- REG_SET_BIT(EXTI_FTSR, channel);
+ __set_bits(EXTI_FTSR, BIT(channel));
break;
case EXTI_RISING_FALLING:
- REG_SET_BIT(EXTI_RTSR, channel);
- REG_SET_BIT(EXTI_FTSR, channel);
+ __set_bits(EXTI_RTSR, BIT(channel));
+ __set_bits(EXTI_FTSR, BIT(channel));
break;
}
/* Configure the enable interrupt bits for the NVIC */
- switch (channel) {
- case EXTI0:
- case EXTI1:
- case EXTI2:
- case EXTI3:
- case EXTI4:
- REG_SET(NVIC_ISER0, BIT(channel + 6));
- break;
-
- /* EXTI5-9 map to the same isr */
- case EXTI5:
- case EXTI6:
- case EXTI7:
- case EXTI8:
- case EXTI9:
- REG_SET(NVIC_ISER0, BIT(23));
- break;
-
- /* EXTI10-15 map to the same isr */
- case EXTI10:
- case EXTI11:
- case EXTI12:
- case EXTI13:
- case EXTI14:
- case EXTI15:
- REG_SET(NVIC_ISER1, BIT(8));
- break;
- }
+ nvic_irq_enable(exti_channels[channel].irq_line);
/* Register the handler */
- exti_handlers[channel] = handler;
+ exti_channels[channel].handler = handler;
}
-void exti_detach_interrupt(uint8 channel) {
+/**
+ * @brief Unregister an external interrupt handler
+ * @param channel channel to disable (eg EXTI0)
+ */
+void exti_detach_interrupt(uint32 channel) {
ASSERT(channel < NR_EXTI_CHANNELS);
ASSERT(EXTI0 == 0);
- /* Is this interrupt actually on? */
- ASSERT((REG_GET(EXTI_IMR) >> channel) & 0x01);
-
- /* Clear EXTI_IMR line */
- REG_CLEAR_BIT(EXTI_IMR, channel);
-
- /* Clear triggers */
- REG_CLEAR_BIT(EXTI_FTSR, channel);
- REG_CLEAR_BIT(EXTI_RTSR, channel);
-
- /* Turn off the associated interrupt */
- switch (channel) {
- case EXTI0:
- case EXTI1:
- case EXTI2:
- case EXTI3:
- case EXTI4:
- REG_SET(NVIC_ICER0, BIT(channel + 6));
- break;
- case EXTI5:
- case EXTI6:
- case EXTI7:
- case EXTI8:
- case EXTI9:
- /* Are there any other channels enabled?
- * If so, don't disable the interrupt handler */
- if (GET_BITS(REG_GET(EXTI_IMR), 5, 9) == 0) {
- REG_SET(NVIC_ICER0, BIT(23));
- }
- break;
- case EXTI10:
- case EXTI11:
- case EXTI12:
- case EXTI13:
- case EXTI14:
- case EXTI15:
- /* Are there any other channels enabled?
- * If so, don't disable the interrupt handler */
- if (GET_BITS(REG_GET(EXTI_IMR), 10, 15) == 0) {
- REG_SET(NVIC_ICER1, BIT(8));
- }
- break;
- }
- /* Clear handler function pointer */
- exti_handlers[channel] = 0;
+ __clear_bits(EXTI_IMR, BIT(channel));
+ __clear_bits(EXTI_FTSR, BIT(channel));
+ __clear_bits(EXTI_RTSR, BIT(channel));
+
+ nvic_irq_disable(exti_channels[channel].irq_line);
+
+ exti_channels[channel].handler = NULL;
}
diff --git a/libmaple/exti.h b/libmaple/exti.h
index 2832e24..97cb4aa 100644
--- a/libmaple/exti.h
+++ b/libmaple/exti.h
@@ -100,6 +100,10 @@
#define NR_EXTI_CHANNELS 16
#define NR_EXTI_PORTS NR_GPIO_PORTS // board specific
+#define EXTI_RISING 0
+#define EXTI_FALLING 1
+#define EXTI_RISING_FALLING 2
+
#define EXTI_IMR 0x40010400 // Interrupt mask register
#define EXTI_EMR (EXTI_IMR + 0x04) // Event mask register
#define EXTI_RTSR (EXTI_IMR + 0x08) // Rising trigger selection register
@@ -113,10 +117,6 @@
#define AFIO_EXTICR3 (AFIO_EVCR + 0x10)
#define AFIO_EXTICR4 (AFIO_EVCR + 0x14)
-#define EXTI_RISING 0
-#define EXTI_FALLING 1
-#define EXTI_RISING_FALLING 2
-
#define EXTI0 0
#define EXTI1 1
#define EXTI2 2
@@ -142,13 +142,12 @@
#define EXTI_CONFIG_PORTF 5 // Native only
#define EXTI_CONFIG_PORTG 6 // Native only
-
#ifdef __cplusplus
extern "C"{
#endif
-void exti_attach_interrupt(uint8, uint8, voidFuncPtr, uint8);
-void exti_detach_interrupt(uint8);
+void exti_attach_interrupt(uint32, uint32, voidFuncPtr, uint32);
+void exti_detach_interrupt(uint32);
#ifdef __cplusplus
} // extern "C"
diff --git a/libmaple/libmaple_types.h b/libmaple/libmaple_types.h
index d49f95a..da3c241 100644
--- a/libmaple/libmaple_types.h
+++ b/libmaple/libmaple_types.h
@@ -45,5 +45,9 @@ typedef void (*voidFuncPtr)(void);
#define __io volatile
+#ifndef NULL
+#define NULL 0
+#endif
+
#endif
diff --git a/libmaple/nvic.h b/libmaple/nvic.h
index 3286357..ab56f0e 100644
--- a/libmaple/nvic.h
+++ b/libmaple/nvic.h
@@ -31,8 +31,6 @@
#define NVIC_INT_USBHP 19
#define NVIC_INT_USBLP 20
-#define NVIC_EXTI1_OFFSET (NVIC_ISER0 + 0x07)
-#define NVIC_EXTI9_5_OFFSET (NVIC_ISER0 + 0x17)
/* NVIC Interrupt Enable registers */
#define NVIC_ISER0 0xE000E100
@@ -57,19 +55,28 @@ extern "C"{
#endif
enum {
- NVIC_TIMER1 = 27,
- NVIC_TIMER2 = 28,
- NVIC_TIMER3 = 29,
- NVIC_TIMER4 = 30,
- NVIC_TIMER5 = 50, // high density only (Maple Native)
- NVIC_TIMER6 = 54, // high density only (Maple Native)
- NVIC_TIMER7 = 55, // high density only (Maple Native)
- NVIC_TIMER8 = 46, // high density only (Maple Native)
- NVIC_USART1 = 37,
- NVIC_USART2 = 38,
- NVIC_USART3 = 39,
- NVIC_USART4 = 52, // high density only (Maple Native)
- NVIC_USART5 = 53, // high density only (Maple Native)
+ NVIC_TIMER1 = 27,
+ NVIC_TIMER2 = 28,
+ NVIC_TIMER3 = 29,
+ NVIC_TIMER4 = 30,
+ NVIC_TIMER5 = 50, // high density only (Maple Native)
+ NVIC_TIMER6 = 54, // high density only (Maple Native)
+ NVIC_TIMER7 = 55, // high density only (Maple Native)
+ NVIC_TIMER8 = 46, // high density only (Maple Native)
+
+ NVIC_USART1 = 37,
+ NVIC_USART2 = 38,
+ NVIC_USART3 = 39,
+ NVIC_USART4 = 52, // high density only (Maple Native)
+ NVIC_USART5 = 53, // high density only (Maple Native)
+
+ NVIC_EXTI0 = 6,
+ NVIC_EXTI1 = 7,
+ NVIC_EXTI2 = 8,
+ NVIC_EXTI3 = 9,
+ NVIC_EXTI4 = 10,
+ NVIC_EXTI9_5 = 23,
+ NVIC_EXTI15_10 = 40,
};
diff --git a/wirish/boards.h b/wirish/boards.h
index 03d0b0e..0e0d159 100644
--- a/wirish/boards.h
+++ b/wirish/boards.h
@@ -64,13 +64,9 @@ typedef struct PinMapping {
uint32 pin;
uint32 adc;
TimerCCR timer_channel;
+ uint32 exti_port;
} PinMapping;
-typedef struct ExtiInfo {
- uint8 channel;
- uint8 port;
-} ExtiInfo;
-
// LeafLabs Maple rev3, rev4
#ifdef BOARD_maple
@@ -78,65 +74,47 @@ typedef struct ExtiInfo {
#define MAPLE_RELOAD_VAL 71999 /* takes a cycle to reload */
static __attribute__ ((unused)) PinMapping PIN_MAP[NR_GPIO_PINS] = {
- {GPIOA_BASE, 3, ADC3, TIMER2_CH4_CCR}, // D0/PA3
- {GPIOA_BASE, 2, ADC2, TIMER2_CH3_CCR}, // D1/PA2
- {GPIOA_BASE, 0, ADC0, TIMER2_CH1_CCR}, // D2/PA0
- {GPIOA_BASE, 1, ADC1, TIMER2_CH2_CCR}, // D3/PA1
- {GPIOB_BASE, 5, ADC_INVALID, TIMER_INVALID}, // D4/PB5
- {GPIOB_BASE, 6, ADC_INVALID, TIMER4_CH1_CCR}, // D5/PB6
- {GPIOA_BASE, 8, ADC_INVALID, TIMER1_CH1_CCR}, // D6/PA8
- {GPIOA_BASE, 9, ADC_INVALID, TIMER1_CH2_CCR}, // D7/PA9
- {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR}, // D8/PA10
- {GPIOB_BASE, 7, ADC_INVALID, TIMER4_CH2_CCR}, // D9/PB7
- {GPIOA_BASE, 4, ADC4, TIMER_INVALID}, // D10/PA4
- {GPIOA_BASE, 7, ADC7, TIMER3_CH2_CCR}, // D11/PA7
- {GPIOA_BASE, 6, ADC6, TIMER3_CH1_CCR}, // D12/PA6
- {GPIOA_BASE, 5, ADC5, TIMER_INVALID}, // D13/PA5
- {GPIOB_BASE, 8, ADC_INVALID, TIMER4_CH3_CCR}, // D14/PB8
+ {GPIOA_BASE, 3, ADC3, TIMER2_CH4_CCR, EXTI_CONFIG_PORTA}, // D0/PA3
+ {GPIOA_BASE, 2, ADC2, TIMER2_CH3_CCR, EXTI_CONFIG_PORTA}, // D1/PA2
+ {GPIOA_BASE, 0, ADC0, TIMER2_CH1_CCR, EXTI_CONFIG_PORTA}, // D2/PA0
+ {GPIOA_BASE, 1, ADC1, TIMER2_CH2_CCR, EXTI_CONFIG_PORTA}, // D3/PA1
+ {GPIOB_BASE, 5, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D4/PB5
+ {GPIOB_BASE, 6, ADC_INVALID, TIMER4_CH1_CCR, EXTI_CONFIG_PORTB}, // D5/PB6
+ {GPIOA_BASE, 8, ADC_INVALID, TIMER1_CH1_CCR, EXTI_CONFIG_PORTA}, // D6/PA8
+ {GPIOA_BASE, 9, ADC_INVALID, TIMER1_CH2_CCR, EXTI_CONFIG_PORTA}, // D7/PA9
+ {GPIOA_BASE, 10, ADC_INVALID, TIMER1_CH3_CCR, EXTI_CONFIG_PORTA}, // D8/PA10
+ {GPIOB_BASE, 7, ADC_INVALID, TIMER4_CH2_CCR, EXTI_CONFIG_PORTB}, // D9/PB7
+ {GPIOA_BASE, 4, ADC4, TIMER_INVALID, EXTI_CONFIG_PORTA}, // D10/PA4
+ {GPIOA_BASE, 7, ADC7, TIMER3_CH2_CCR, EXTI_CONFIG_PORTA}, // D11/PA7
+ {GPIOA_BASE, 6, ADC6, TIMER3_CH1_CCR, EXTI_CONFIG_PORTA}, // D12/PA6
+ {GPIOA_BASE, 5, ADC5, TIMER_INVALID, EXTI_CONFIG_PORTA}, // D13/PA5
+ {GPIOB_BASE, 8, ADC_INVALID, TIMER4_CH3_CCR, EXTI_CONFIG_PORTB}, // D14/PB8
/* Little header */
- {GPIOC_BASE, 0, ADC10, TIMER_INVALID}, // D15/PC0
- {GPIOC_BASE, 1, ADC11, TIMER_INVALID}, // D16/PC1
- {GPIOC_BASE, 2, ADC12, TIMER_INVALID}, // D17/PC2
- {GPIOC_BASE, 3, ADC13, TIMER_INVALID}, // D18/PC3
- {GPIOC_BASE, 4, ADC14, TIMER_INVALID}, // D19/PC4
- {GPIOC_BASE, 5, ADC15, TIMER_INVALID}, // D20/PC5
+ {GPIOC_BASE, 0, ADC10, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D15/PC0
+ {GPIOC_BASE, 1, ADC11, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D16/PC1
+ {GPIOC_BASE, 2, ADC12, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D17/PC2
+ {GPIOC_BASE, 3, ADC13, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D18/PC3
+ {GPIOC_BASE, 4, ADC14, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D19/PC4
+ {GPIOC_BASE, 5, ADC15, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D20/PC5
/* External header */
- {GPIOC_BASE, 13, ADC_INVALID, TIMER_INVALID}, // D21/PC13
- {GPIOC_BASE, 14, ADC_INVALID, TIMER_INVALID}, // D22/PC14
- {GPIOC_BASE, 15, ADC_INVALID, TIMER_INVALID}, // D23/PC15
- {GPIOB_BASE, 9, ADC_INVALID, TIMER4_CH4_CCR}, // D24/PB9
- {GPIOD_BASE, 2, ADC_INVALID, TIMER_INVALID}, // D25/PD2
- {GPIOC_BASE, 10, ADC_INVALID, TIMER_INVALID}, // D26/PC10
- {GPIOB_BASE, 0, ADC8, TIMER3_CH3_CCR}, // D27/PB0
- {GPIOB_BASE, 1, ADC9, TIMER3_CH4_CCR}, // D28/PB1
- {GPIOB_BASE, 10, ADC_INVALID, TIMER_INVALID}, // D29/PB10
- {GPIOB_BASE, 11, ADC_INVALID, TIMER_INVALID}, // D30/PB11
- {GPIOB_BASE, 12, ADC_INVALID, TIMER_INVALID}, // D31/PB12
- {GPIOB_BASE, 13, ADC_INVALID, TIMER_INVALID}, // D32/PB13
- {GPIOB_BASE, 14, ADC_INVALID, TIMER_INVALID}, // D33/PB14
- {GPIOB_BASE, 15, ADC_INVALID, TIMER_INVALID}, // D34/PB15
- {GPIOC_BASE, 6, ADC_INVALID, TIMER_INVALID}, // D35/PC6
- {GPIOC_BASE, 7, ADC_INVALID, TIMER_INVALID}, // D36/PC7
- {GPIOC_BASE, 8, ADC_INVALID, TIMER_INVALID}, // D37/PC8
- {GPIOC_BASE, 9, ADC_INVALID, TIMER_INVALID} // D38/PC9 (BUT)
- };
-
- static __attribute__ ((unused)) ExtiInfo PIN_TO_EXTI_CHANNEL[NR_GPIO_PINS] =
- {
- {EXTI3, EXTI_CONFIG_PORTA}, // D0/PA3
- {EXTI2, EXTI_CONFIG_PORTA}, // D1/PA2
- {EXTI0, EXTI_CONFIG_PORTA}, // D2/PA0
- {EXTI1, EXTI_CONFIG_PORTA}, // D3/PA1
- {EXTI5, EXTI_CONFIG_PORTB}, // D4/PB5
- {EXTI6, EXTI_CONFIG_PORTB}, // D5/PB6
- {EXTI8, EXTI_CONFIG_PORTA}, // D6/PA8
- {EXTI9, EXTI_CONFIG_PORTA}, // D7/PA9
- {EXTI10, EXTI_CONFIG_PORTA}, // D8/PA10
- {EXTI7, EXTI_CONFIG_PORTB}, // D9/PB7
- {EXTI4, EXTI_CONFIG_PORTA}, // D10/PA4
- {EXTI7, EXTI_CONFIG_PORTA}, // D11/PA7
- {EXTI6, EXTI_CONFIG_PORTA}, // D12/PA6
- {EXTI5, EXTI_CONFIG_PORTA}, // D13/PA5
+ {GPIOC_BASE, 13, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D21/PC13
+ {GPIOC_BASE, 14, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D22/PC14
+ {GPIOC_BASE, 15, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D23/PC15
+ {GPIOB_BASE, 9, ADC_INVALID, TIMER4_CH4_CCR, EXTI_CONFIG_PORTB}, // D24/PB9
+ {GPIOD_BASE, 2, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTD}, // D25/PD2
+ {GPIOC_BASE, 10, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D26/PC10
+ {GPIOB_BASE, 0, ADC8, TIMER3_CH3_CCR, EXTI_CONFIG_PORTB}, // D27/PB0
+ {GPIOB_BASE, 1, ADC9, TIMER3_CH4_CCR, EXTI_CONFIG_PORTB}, // D28/PB1
+ {GPIOB_BASE, 10, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D29/PB10
+ {GPIOB_BASE, 11, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D30/PB11
+ {GPIOB_BASE, 12, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D31/PB12
+ {GPIOB_BASE, 13, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D32/PB13
+ {GPIOB_BASE, 14, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D33/PB14
+ {GPIOB_BASE, 15, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTB}, // D34/PB15
+ {GPIOC_BASE, 6, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D35/PC6
+ {GPIOC_BASE, 7, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D36/PC7
+ {GPIOC_BASE, 8, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC}, // D37/PC8
+ {GPIOC_BASE, 9, ADC_INVALID, TIMER_INVALID, EXTI_CONFIG_PORTC} // D38/PC9 (BUT)
};
#endif
diff --git a/wirish/ext_interrupts.c b/wirish/ext_interrupts.c
index 6ba1d05..5009d75 100644
--- a/wirish/ext_interrupts.c
+++ b/wirish/ext_interrupts.c
@@ -36,22 +36,21 @@
* @brief Attach an interrupt handler to be triggered on a given
* transition on the pin. Runs in interrupt context
*
- * @param[in] pin Maple pin number
- * @param[in] handler Function to run upon external interrupt trigger.
- * @param[in] mode Type of transition to trigger on, eg falling, rising, etc.
+ * @param pin Maple pin number
+ * @param handler Function to run upon external interrupt trigger.
+ * @param mode Type of transition to trigger on, eg falling, rising, etc.
*
* @sideeffect Registers a handler
*/
-int attachInterrupt(uint8 pin, voidFuncPtr handler, uint32 mode) {
+void attachInterrupt(uint8 pin, voidFuncPtr handler, uint32 mode) {
uint8 outMode;
/* Parameter checking */
if (pin >= NR_GPIO_PINS) {
- return EXT_INTERRUPT_INVALID_PIN;
+ return;
}
if (!handler) {
- ASSERT(0);
- return EXT_INTERRUPT_INVALID_FUNCTION;
+ return;
}
switch (mode) {
@@ -65,22 +64,27 @@ int attachInterrupt(uint8 pin, voidFuncPtr handler, uint32 mode) {
outMode = EXTI_RISING_FALLING;
break;
default:
- ASSERT(0);
- return EXT_INTERRUPT_INVALID_MODE;;
+ return;
}
- exti_attach_interrupt(PIN_TO_EXTI_CHANNEL[pin].channel,
- PIN_TO_EXTI_CHANNEL[pin].port,
- handler, mode);
+ exti_attach_interrupt(PIN_MAP[pin].exti_port,
+ PIN_MAP[pin].pin,
+ handler,
+ mode);
- return 0;
+ return;
}
-int detachInterrupt(uint8 pin) {
+/**
+ * @brief Disable an external interrupt
+ * @param pin maple pin number
+ * @sideeffect unregisters external interrupt handler
+ */
+void detachInterrupt(uint8 pin) {
if (!(pin < NR_GPIO_PINS)) {
- return EXT_INTERRUPT_INVALID_PIN;
+ return;
}
- exti_detach_interrupt(PIN_TO_EXTI_CHANNEL[pin].channel);
+ exti_detach_interrupt(PIN_MAP[pin].pin);
}
diff --git a/wirish/ext_interrupts.h b/wirish/ext_interrupts.h
index 7449685..62f31bb 100644
--- a/wirish/ext_interrupts.h
+++ b/wirish/ext_interrupts.h
@@ -37,19 +37,12 @@ enum {
CHANGE
};
-
-enum {
- EXT_INTERRUPT_INVALID_PIN = (-1),
- EXT_INTERRUPT_INVALID_FUNCTION = (-2),
- EXT_INTERRUPT_INVALID_MODE = (-3),
-};
-
#ifdef __cplusplus
extern "C"{
#endif
-int attachInterrupt(uint8 pin, voidFuncPtr, uint32 mode);
-int detachInterrupt(uint8 pin);
+void attachInterrupt(uint8 pin, voidFuncPtr, uint32 mode);
+void detachInterrupt(uint8 pin);
#ifdef __cplusplus
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-01 09:01:11 +0000