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| author | Manuel Odendahl <wesen@ruinwesen.com> | 2013-01-08 16:43:38 +0100 |
|---|---|---|
| committer | Manuel Odendahl <wesen@ruinwesen.com> | 2013-01-17 20:54:54 +0100 |
| commit | b6e2d2a9d3acd89cdace2a535cfb183bce66fe58 (patch) | |
| tree | 4c9eabb3486f1d59c5b86b9ef1813e55c04fde33 /libmaple/stm32f1 | |
| parent | be005eb7acc1fa08aa92b47d905e5a8ec38f5d6e (diff) | |
| download | librambutan-b6e2d2a9d3acd89cdace2a535cfb183bce66fe58.tar.gz librambutan-b6e2d2a9d3acd89cdace2a535cfb183bce66fe58.zip | |
Set DCNTR before starting DMA transfer.
I am not sure why this would work for most DMA transfers but I ran into trouble when doing
SDIO DMA.
Signed-off-by: Manuel Odendahl <wesen@ruinwesen.com>
Diffstat (limited to 'libmaple/stm32f1')
| -rw-r--r-- | libmaple/stm32f1/dma.c | 1 | ||||
| -rw-r--r-- | libmaple/stm32f1/include/series/dma.h | 10 |
2 files changed, 11 insertions, 0 deletions
diff --git a/libmaple/stm32f1/dma.c b/libmaple/stm32f1/dma.c index 5364a04..6400d15 100644 --- a/libmaple/stm32f1/dma.c +++ b/libmaple/stm32f1/dma.c @@ -145,6 +145,7 @@ static int config_to_per(dma_tube_reg_map *chregs, dma_tube_config *cfg) { cfg->tube_src_size, cfg->tube_flags & DMA_CFG_SRC_INC, cfg->tube_dst_size, cfg->tube_flags & DMA_CFG_DST_INC, (cfg_ccr_flags(cfg->tube_flags) | DMA_CCR_DIR_FROM_MEM)); + chregs->CNDTR = cfg->tube_nr_xfers; chregs->CMAR = (uint32)cfg->tube_src; chregs->CPAR = (uint32)cfg->tube_dst; return DMA_TUBE_CFG_SUCCESS; diff --git a/libmaple/stm32f1/include/series/dma.h b/libmaple/stm32f1/include/series/dma.h index 3b19e2b..bedb602 100644 --- a/libmaple/stm32f1/include/series/dma.h +++ b/libmaple/stm32f1/include/series/dma.h @@ -145,6 +145,16 @@ typedef struct dma_tube_reg_map { /* Interrupt status register */ +#define DMA_ISR_TEIF_BIT 3 +#define DMA_ISR_HTIF_BIT 2 +#define DMA_ISR_TCIF_BIT 1 +#define DMA_ISR_GIF_BIT 0 + +#define DMA_ISR_TEIF (1 << DMA_ISR_TEIF_BIT) +#define DMA_ISR_HTIF (1 << DMA_ISR_HTIF_BIT) +#define DMA_ISR_TCID (1 << DMA_ISR_TCIF_BIT) +#define DMA_ISR_GIF (1 << DMA_ISR_GIF_BIT) + #define DMA_ISR_TEIF7_BIT 27 #define DMA_ISR_HTIF7_BIT 26 #define DMA_ISR_TCIF7_BIT 25 |