RCC: Clean up and sanitize interfaces across F1, F2 series.

Additions:

- rcc_switch_sysclk():

  For changing the clock used as SYSCLK's source.

- enum rcc_clk:

  One for each system and secondary clock source (e.g. HSE,
  LSE). These are defined on a per-series basis in each of the
  <series/rcc.h>.

- rcc_turn_on_clk(),
  rcc_turn_off_clk(),
  rcc_is_clk_ready():

  For turning on system and secondary clock sources, and checking
  whether or not they're ready. Uses enum rcc_clk.

Removals:

- rcc_clk_init(): There's no way to port this to F2. Move it to the F1
  header. This also means we can remove the empty implementation and
  enum rcc_pll_multiplier from the F2 RCC header, where it doesn't
  make any sense.

Also fix up some includes, and rewrite rcc_clk_init() in terms of the
new clock source management functions.

Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>

2 files changed, 38 insertions, 19 deletions

diff --git a/libmaple/stm32f1/include/series/rcc.h b/libmaple/stm32f1/include/series/rcc.h
index 261dc5d..474aaf7 100644
--- a/libmaple/stm32f1/include/series/rcc.h
+++ b/libmaple/stm32f1/include/series/rcc.h
@@ -37,6 +37,8 @@
 extern "C"{
 #endif
 
+#include <libmaple/libmaple.h>
+
 /*
  * Register map
  */
@@ -383,7 +385,7 @@ typedef struct rcc_reg_map {
 #define RCC_CSR_LSION                   BIT(RCC_CSR_LSION_BIT)
 
 /*
- * Other types
+ * libmaple-mandated enumeration types.
  */
 
 /**
@@ -546,6 +548,33 @@ typedef enum rcc_ahb_divider {
     RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
 } rcc_ahb_divider;
 
+/**
+ * @brief Available clock sources.
+ */
+typedef enum rcc_clk {
+    RCC_CLK_PLL    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_PLLON_BIT), /**< Main PLL, clocked by
+                                                    HSI or HSE. */
+    RCC_CLK_HSE    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_HSEON_BIT), /**< High speed external. */
+    RCC_CLK_HSI    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_HSION_BIT), /**< High speed internal. */
+    RCC_CLK_LSE    = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) |
+                              RCC_BDCR_LSEON_BIT), /**< Low-speed external
+                                                    * (32.768 KHz). */
+    RCC_CLK_LSI    = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) |
+                              RCC_CSR_LSION_BIT), /**< Low-speed internal
+                                                   * (approximately 32 KHz). */
+} rcc_clk;
+
+/*
+ * Series-specific functionality.
+ */
+
+void rcc_clk_init(rcc_sysclk_src sysclk_src,
+                  rcc_pllsrc pll_src,
+                  rcc_pll_multiplier pll_mul);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/libmaple/stm32f1/rcc.c b/libmaple/stm32f1/rcc.c
index 2b78e89..2d31482 100644
--- a/libmaple/stm32f1/rcc.c
+++ b/libmaple/stm32f1/rcc.c
@@ -105,9 +105,6 @@ const struct rcc_dev_info rcc_dev_table[] = {
 void rcc_clk_init(rcc_sysclk_src sysclk_src,
                   rcc_pllsrc pll_src,
                   rcc_pll_multiplier pll_mul) {
-    uint32 cfgr = 0;
-    uint32 cr;
-
     /* Assume that we're going to clock the chip off the PLL, fed by
      * the HSE */
     ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
@@ -115,25 +112,18 @@ void rcc_clk_init(rcc_sysclk_src sysclk_src,
 
     RCC_BASE->CFGR = pll_src | pll_mul;
 
-    /* Turn on the HSE */
-    cr = RCC_BASE->CR;
-    cr |= RCC_CR_HSEON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_HSERDY))
+    /* Turn on, and wait for, HSE. */
+    rcc_turn_on_clk(RCC_CLK_HSE);
+    while (!rcc_is_clk_ready(RCC_CLK_HSE))
         ;
 
-    /* Now the PLL */
-    cr |= RCC_CR_PLLON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_PLLRDY))
+    /* Do the same for the main PLL. */
+    rcc_turn_on_clk(RCC_CLK_PLL);
+    while(!rcc_is_clk_ready(RCC_CLK_PLL))
         ;
 
-    /* Finally, let's switch over to the PLL */
-    cfgr &= ~RCC_CFGR_SW;
-    cfgr |= RCC_CFGR_SW_PLL;
-    RCC_BASE->CFGR = cfgr;
-    while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
-        ;
+    /* Finally, switch over to the PLL. */
+    rcc_switch_sysclk(RCC_CLKSRC_PLL);
 }
 
 /**