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authorMarti Bolivar <mbolivar@leaflabs.com>2012-06-04 00:06:43 -0400
committerMarti Bolivar <mbolivar@leaflabs.com>2012-06-04 00:20:21 -0400
commit23d81a1044ac3c3694d58d7659be8476ebe9ee15 (patch)
tree9ab62e9244aae91d344eaca8cab926ce8c560287 /libmaple/include
parent6ad1757e62dcfe112a473ef6474b9f4c1317cf9e (diff)
downloadlibrambutan-23d81a1044ac3c3694d58d7659be8476ebe9ee15.tar.gz
librambutan-23d81a1044ac3c3694d58d7659be8476ebe9ee15.zip
Bring back libmaple/dac.h.
Minor variations on F2: DMA underrun interrupts, and a status register to hold the notification bits. Signed-off-by: Marti Bolivar <mbolivar@leaflabs.com>
Diffstat (limited to 'libmaple/include')
-rw-r--r--libmaple/include/libmaple/dac.h124
1 files changed, 56 insertions, 68 deletions
diff --git a/libmaple/include/libmaple/dac.h b/libmaple/include/libmaple/dac.h
index 047f874..56bfdc4 100644
--- a/libmaple/include/libmaple/dac.h
+++ b/libmaple/include/libmaple/dac.h
@@ -1,7 +1,7 @@
/******************************************************************************
* The MIT License
*
- * Copyright (c) 2011 LeafLabs, LLC.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
* Copyright (c) 2010 Bryan Newbold.
*
* Permission is hereby granted, free of charge, to any person
@@ -39,124 +39,112 @@
extern "C"{
#endif
+#include <series/dac.h>
#include <libmaple/libmaple_types.h>
#include <libmaple/rcc.h>
+#include <libmaple/stm32.h>
/*
- * Register maps
+ * Register map base and device pointers.
+ *
+ * The DACs are the same on all supported targets, so it's not worth
+ * repeating these in the series headers.
*/
-/** DAC register map. */
-typedef struct dac_reg_map {
- __io uint32 CR; /**< Control register */
- __io uint32 SWTRIGR; /**< Software trigger register */
- __io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
- holding register */
- __io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
- holding register */
- __io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
- holding register */
- __io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
- holding register */
- __io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
- holding register */
- __io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
- holding register */
- __io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
- holding register */
- __io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
- holding register */
- __io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
- register */
- __io uint32 DOR1; /**< Channel 1 data output register */
- __io uint32 DOR2; /**< Channel 2 data output register */
-} dac_reg_map;
-
-/** DAC register map base address */
#define DAC_BASE ((struct dac_reg_map*)0x40007400)
-/*
- * Devices
- */
-
/** DAC device type. */
typedef struct dac_dev {
dac_reg_map *regs; /**< Register map */
} dac_dev;
+#if STM32_HAVE_DAC
extern const dac_dev *DAC;
+#endif
/*
* Register bit definitions
*/
/* Control register */
+
/* Channel 1 control */
-#define DAC_CR_EN1 BIT(0) /* Enable */
-#define DAC_CR_BOFF1 BIT(1) /* Output buffer disable */
-#define DAC_CR_TEN1 BIT(2) /* Trigger enable */
-#define DAC_CR_TSEL1 (0x7 << 3) /* Trigger selection */
-#define DAC_CR_WAVE1 (0x3 << 6) /* Noise/triangle wave enable */
-#define DAC_CR_MAMP1 (0xF << 8) /* Mask/amplitude selector */
-#define DAC_CR_DMAEN1 BIT(12) /* DMA enable */
+#define DAC_CR_EN1 (1U << 0) /* Enable */
+#define DAC_CR_BOFF1 (1U << 1) /* Output buffer disable */
+#define DAC_CR_TEN1 (1U << 2) /* Trigger enable */
+#define DAC_CR_TSEL1 (0x7 << 3) /* Trigger selection */
+#define DAC_CR_WAVE1 (0x3 << 6) /* Noise/triangle wave */
+#define DAC_CR_MAMP1 (0xF << 8) /* Mask/amplitude selector */
+#define DAC_CR_DMAEN1 (1U << 12) /* DMA enable */
/* Channel 2 control */
-#define DAC_CR_EN2 BIT(16) /* Enable */
-#define DAC_CR_BOFF2 BIT(17) /* Output buffer disable */
-#define DAC_CR_TEN2 BIT(18) /* Trigger enable */
-#define DAC_CR_TSEL2 (0x7 << 19) /* Trigger selection */
-#define DAC_CR_WAVE2 (0x3 << 22) /* Noise/triangle wave generation*/
-#define DAC_CR_MAMP2 (0xF << 24) /* Mask/amplitude selector */
-#define DAC_CR_DMAEN2 BIT(28) /* DMA enable */
+#define DAC_CR_EN2 (1U << 16) /* Enable */
+#define DAC_CR_BOFF2 (1U << 17) /* Output buffer disable */
+#define DAC_CR_TEN2 (1U << 18) /* Trigger enable */
+#define DAC_CR_TSEL2 (0x7 << 19) /* Trigger selection */
+#define DAC_CR_WAVE2 (0x3 << 22) /* Noise/triangle wave */
+#define DAC_CR_MAMP2 (0xF << 24) /* Mask/amplitude selector */
+#define DAC_CR_DMAEN2 (1U << 28) /* DMA enable */
/* Software trigger register */
-#define DAC_SWTRIGR_SWTRIG1 BIT(0) /* Channel 1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 BIT(1) /* Channel 2 software trigger */
+
+#define DAC_SWTRIGR_SWTRIG1 (1U << 0) /* Channel 1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 (1U << 1) /* Channel 2 software trigger */
/* Channel 1 12-bit right-aligned data holding register */
-#define DAC_DHR12R1_DACC1DHR 0x00000FFF
+
+#define DAC_DHR12R1_DACC1DHR 0x00000FFF
/* Channel 1 12-bit left-aligned data holding register */
-#define DAC_DHR12L1_DACC1DHR 0x0000FFF0
+
+#define DAC_DHR12L1_DACC1DHR 0x0000FFF0
/* Channel 1 8-bit left-aligned data holding register */
-#define DAC_DHR8R1_DACC1DHR 0x000000FF
+
+#define DAC_DHR8R1_DACC1DHR 0x000000FF
/* Channel 2 12-bit right-aligned data holding register */
-#define DAC_DHR12R2_DACC2DHR 0x00000FFF
+
+#define DAC_DHR12R2_DACC2DHR 0x00000FFF
/* Channel 2 12-bit left-aligned data holding register */
-#define DAC_DHR12L2_DACC2DHR 0x0000FFF0
+
+#define DAC_DHR12L2_DACC2DHR 0x0000FFF0
/* Channel 2 8-bit left-aligned data holding register */
-#define DAC_DHR8R2_DACC2DHR 0x000000FF
+
+#define DAC_DHR8R2_DACC2DHR 0x000000FF
/* Dual DAC 12-bit right-aligned data holding register */
-#define DAC_DHR12RD_DACC1DHR 0x00000FFF
-#define DAC_DHR12RD_DACC2DHR 0x0FFF0000
+
+#define DAC_DHR12RD_DACC1DHR 0x00000FFF
+#define DAC_DHR12RD_DACC2DHR 0x0FFF0000
/* Dual DAC 12-bit left-aligned data holding register */
-#define DAC_DHR12LD_DACC1DHR 0x0000FFF0
-#define DAC_DHR12LD_DACC2DHR 0xFFF00000
+
+#define DAC_DHR12LD_DACC1DHR 0x0000FFF0
+#define DAC_DHR12LD_DACC2DHR 0xFFF00000
/* Dual DAC 8-bit left-aligned data holding register */
-#define DAC_DHR8RD_DACC1DHR 0x000000FF
-#define DAC_DHR8RD_DACC2DHR 0x0000FF00
+
+#define DAC_DHR8RD_DACC1DHR 0x000000FF
+#define DAC_DHR8RD_DACC2DHR 0x0000FF00
/* Channel 1 data output register */
-#define DAC_DOR1_DACC1DOR 0x00000FFF
+
+#define DAC_DOR1_DACC1DOR 0x00000FFF
/* Channel 1 data output register */
-#define DAC_DOR2_DACC2DOR 0x00000FFF
+
+#define DAC_DOR2_DACC2DOR 0x00000FFF
/*
- * Convenience functions
+ * Routines
*/
-/* We take the dev argument in these convenience functions for
- * future-proofing */
+/* We take the dev argument in these for future-proofing */
-#define DAC_CH1 0x1
-#define DAC_CH2 0x2
+#define DAC_CH1 0x1
+#define DAC_CH2 0x2
void dac_init(const dac_dev *dev, uint32 flags);
void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val);